CN104881654A - Pre-amplification infrared imaging image recognition system based on noise reduction - Google Patents

Pre-amplification infrared imaging image recognition system based on noise reduction Download PDF

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Publication number
CN104881654A
CN104881654A CN201510292446.0A CN201510292446A CN104881654A CN 104881654 A CN104881654 A CN 104881654A CN 201510292446 A CN201510292446 A CN 201510292446A CN 104881654 A CN104881654 A CN 104881654A
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triode
resistance
pin
electric capacity
pole
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CN104881654B (en
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刘霖
刘永
邱会中
杨先明
张晓奕
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Tianjin Huaguoren Cartoon Creation Co ltd
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Ningbo Momi Innovation Works Electronic Technology Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06VIMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12Fingerprints or palmprints
    • G06V40/13Sensors therefor
    • G06V40/1318Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing

Abstract

The invention discloses a pre-amplification infrared imaging image recognition system based on noise reduction. The pre-amplification infrared imaging image recognition system is composed of an infrared imaging system (1) and an image recognition system (2) connected with the infrared imaging system (1). The image recognition system (2) comprises a central processing module (21), and an image processing system (22), a display (23), an alarm (24) and a memory (25), all of which are connected with the central processing module (21). The image recognition system (2) is further provided with a noise reduction module (26), and the noise reduction module (26) is connected with the image processing system (22). Through a pre-amplification circuit, image signals can be amplified without distortion, images after amplification are clearer, and the recognition accuracy of the system is further improved. Meanwhile, the system is provided with the noise reduction module which can filter interference noise of image signals in the process of transmission and restore the image signals to an original effect.

Description

A kind of enlarge leadingly formula infrared imaging image identification system based on noise reduction process
Technical field
The present invention relates to a kind of image identification system, specifically refer to a kind of enlarge leadingly formula infrared imaging image identification system based on noise reduction process.
Background technology
In order to differentiate user's identity, or in order to security consideration use in some cases monitoring system be current safety ensure a usual way.Traditional way is that monitoring system is arranged password, and this password only has specific people to know.But if password leaks, other users just can carry out this system, and security can be made equally to reduce.Some signs of people cannot copy, so using the sign of people, fingerprint or face as judging that the biological recognition system development of user's identity is very fast.
Wherein, face recognition technology is as a hot issue of field of biological recognition, and a lot of research institution and company all in the research of positive carrying out and corresponding product development, and investigated multiple face recognition algorithms.Use face recognition algorithms to carry out recognition of face thus to carry out the accuracy rate of identity judgement high, a lot of product can reach the discrimination of more than 90%.But the product of current various algorithm all can not adapt to the change of illumination completely, that is when discrimination being caused to reduce after ambient lighting change.Internal authority test (FRVT2002) shows, discrimination is reduced to about 50% from more than 97% by the change of illumination.In order to solve the problem, there is a kind of new disposal route, namely adopt infrared imaging principle to carry out picture signal collection to being identified target, then can improve the precision of image acquisition thus.Even if but the precision of images collected is high, but picture signal is in the process of transmission, is inevitably subject to the interference of noise.Therefore, how to recover original image, avoid image in identifying, go out picture and identify it is then that people are badly in need of solving by mistake.
Summary of the invention
The object of the invention is to overcome its picture signal of image identification system traditional at present in the process of transmission, be easily subject to the defect of the interference of noise, a kind of enlarge leadingly formula infrared imaging image identification system based on noise reduction process is provided.
Object of the present invention is achieved through the following technical solutions: a kind of enlarge leadingly formula infrared imaging image identification system based on noise reduction process, and it is by infrared imaging system, and the image identification system be connected with infrared imaging system forms; Described infrared imaging system is by infrared light supply, the optical system be connected with infrared light supply, the scanning mechanism be connected with optical system, the infrared eye be connected with scanning mechanism, the image capture module be connected with infrared eye, and the pre-amplification circuit be connected with image capture module forms; Described image identification system is then by central processing module, the image processing system be connected with central processing module, display, alarm and storer form, in order to reach object of the present invention, described image identification system is also provided with noise reduction module, and this noise reduction module is connected with image processing system.
Further, described noise reduction module is by amplifier P1, amplifier P2, triode Q6, triode Q7, triode Q8, field effect transistor MOS2, Sheffer stroke gate IC1, Sheffer stroke gate IC2, N pole is connected with the output terminal of amplifier P1, the diode D5 of ground connection while P pole is then connected with second input end of Sheffer stroke gate IC1 after resistance R20, one end is connected with the first input end of Sheffer stroke gate IC1, the resistance R21 that the other end is then connected with the output terminal of Sheffer stroke gate IC2 after electric capacity C17, one end is connected with the output terminal of Sheffer stroke gate IC1, the resistance R22 that the other end is then connected with the tie point of electric capacity C17 with resistance R21, and the resistance R23 between the emitter and collector being serially connected in triode Q7 forms, the minus earth of described amplifier P1, its positive pole are then then connected with the emitter of triode Q6 as the input end of this noise reduction module, its output terminal, the base stage of described triode Q7 is connected with the base stage of triode Q6, its collector is then connected with the collector of triode Q6, its emitter is then connected with the drain electrode of field effect transistor MOS2, the drain electrode of described field effect transistor MOS2 is connected with the negative pole of amplifier P2, its grid is then connected with the output terminal of amplifier P2, its source electrode is then connected with the emitter of triode Q8, the negative pole of described amplifier P2 is then as output terminal, its plus earth of this noise reduction module, the base stage of described triode Q8 is connected with the tie point of electric capacity C17 with resistance R21, its collector then ground connection, the second input end grounding, its first input end of described Sheffer stroke gate IC2 are then connected with the output terminal of Sheffer stroke gate IC1.
Described pre-amplification circuit is then by amplification chip U1, triode Q5, field effect transistor MOS1, negative pole is connected with the IN pin of amplification chip U1 after resistance R17, positive pole is then as the electric capacity C14 of the input end of this pre-amplification circuit, positive pole is connected with the negative pole of electric capacity C14, negative pole is then in turn through electric capacity C15 that diode D3 is connected with the VCC pin of amplification chip U1 after resistance R18, positive pole is connected with the NF pin of amplification chip U1 after resistance R15, the electric capacity C13 that negative pole is then connected with the source electrode of field effect transistor MOS1 after resistance R19, one end is connected with the NF pin of amplification chip U1, the resistance R16 of ground connection while the other end is then connected with the GND pin of amplification chip U1, positive pole is connected with the NSC pin of amplification chip U1, the electric capacity C16 that negative pole is then connected with the emitter of triode Q5, and N pole is connected with the emitter pole of triode Q5, the diode D4 that P pole is then connected with the drain electrode of field effect transistor MOS1 forms, the base stage of described triode Q5 is connected with the OUT pin of amplification chip U1, its grounded emitter, its collector are then connected with the ALC pin of amplification chip U1, the grid of described field effect transistor MOS1 is then connected with the collector of triode Q5, the emitter of described triode Q5 also as this pre-amplification circuit output terminal.
Described image processing system then by signal input circuit, the signal processing circuit be connected with signal input circuit, and the trigger circuit be connected with signal processing circuit and tuned circuit form.
Described signal input circuit is by triode Q1, one end is connected with the base stage of triode Q1, the other end is then in turn through resistance R3 that resistance R2 is connected with the emitter of triode Q1 after resistance R1, positive pole is connected with the emitter of triode Q1, the electric capacity C1 of minus earth, and while positive pole is connected with the collector of triode Q1, negative pole is then connected with signal processing circuit, the electric capacity C2 of ground connection forms; The emitter of described triode Q1 is connected with signal processing circuit.
Described signal processing circuit is by process chip U, P pole is connected with the SW1 pin of process chip U, N pole is the diode D1 of ground connection after electric capacity C3 then, one end is connected with the N pole of diode D1, the resistance R4 of ground connection while the other end is then connected with the GND pin of process chip U after resistance R5, positive pole is connected with the CTRL pin of process chip U, the electric capacity C4 of minus earth, one end is connected with the CTRL pin of process chip U, the other end is the resistance R6 of ground connection after electric capacity C5 then, positive pole is connected with the SS pin of process chip U, the electric capacity C6 that negative pole is then connected with trigger circuit, and one end is connected with the PGOOD pin of process chip U, the resistance R7 that the other end is then connected with tuned circuit forms, the VIN pin of described process chip U is connected with the emitter of triode Q1, its FB pin is then connected with the tie point of resistance R5 with resistance R4, its CTRL pin is then connected with the negative pole of electric capacity C2, its SHDN pin is then connected with trigger circuit.
Described trigger circuit are by flip chip K, triode Q4, the resistance R12 that one end is connected with the base stage of triode Q4, the other end is then connected with the OUT pin of flip chip K, the resistance R14 that one end is connected with the emitter of triode Q4, the other end is then connected with the GND pin of flip chip K after electric capacity C12, and the resistance R13 that one end is connected with the LX pin of flip chip K, the other end is then connected with the FB pin of flip chip K after electric capacity C11 forms; The IN pin of described flip chip K is connected with the SHDN pin of process chip U, its EN pin is then connected with the negative pole of electric capacity C6, its GND pin ground connection; The collector of described triode Q4 is then connected with tuned circuit.
Described tuned circuit is by triode Q2, triode Q3, N pole is connected with the collector of triode Q2 after resistance R8 through inductance L 1 in turn, the varactor D2 that P pole is then connected with the emitter of triode Q3 after electric capacity C8, one end is connected with the P pole of varactor D2, the other end then meets the resistance R11 of-15V voltage, positive pole is connected with the P pole of varactor D2, the electric capacity C9 that negative pole is then connected with the collector of triode Q4, positive pole is connected with the emitter of triode Q3, the tunable capacitor C10 of negative pole then ground connection, one end is connected with the emitter of triode Q2, the other end then connects the inductance L 2 of+15V voltage after resistance R9, positive pole is connected with the tie point of inductance L 2 with resistance R9, the electric capacity C7 of minus earth, and one end is connected with the positive pole of electric capacity C7, the resistance R10 that the other end is then connected with the base stage of triode Q3 forms, the base stage of described triode Q2 is connected with the PGOOD pin of process chip U after resistance R7, the collector then ground connection of triode Q3.
In order to ensure effect, described process chip U is preferably LT1942 integrated circuit, and flip chip K is then preferably EMD2050 integrated circuit, and amplification chip U1 is then preferably MC2830 integrated circuit and realizes.
The present invention comparatively prior art compares, and has the following advantages and beneficial effect:
(1) the present invention can suppress the optical content in natural light in a large number, adapts to night, daytime, and the use of the changeable environments such as side, inverse, positive light, substantially increases application scenario of the present invention.
(2) the present invention adopts infrared imaging principle to catch target, and therefore it is not vulnerable to extraneous factor interference, and the abundant information obtained, improve the degree of accuracy of image identification system to a great extent.
(3) image acquisition device that image-forming range of the present invention is more traditional wants far away, as the present invention be applied in gate control system time, be identified and then do not need face to lean on very closely can carry out man face image acquiring to picture, make that identifying is more clean, health.
(4) recognition speed of the present invention is fast, meets the demand of the fast pace life of current people.
(5) the present invention is provided with pre-amplification circuit, and it can distortionlessly amplify picture signal, and the image after amplification is more clear, further improves accuracy of identification of the present invention.
(6) the present invention is provided with noise reduction module, and it can filter out the interference noise that picture signal occurs in transmitting procedure, makes picture signal return to original effect.
Accompanying drawing explanation
Fig. 1 is one-piece construction schematic diagram of the present invention.
Fig. 2 is image processing system electrical block diagram of the present invention.
Fig. 3 is pre-amplification circuit structural representation of the present invention.
Fig. 4 is noise reduction module electrical block diagram of the present invention.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
Embodiment
As shown in Figure 1, the present invention is by infrared imaging system 1, and the image identification system 2 be connected with infrared imaging system 1 forms.This infrared imaging system 1 is for gathering the picture signal being identified object, it is by infrared light supply 11, the optical system 12 be connected with infrared light supply 11, the scanning mechanism 13 be connected with optical system 12, the infrared eye 14 be connected with scanning mechanism 13, the image capture module 15 be connected with infrared eye 14, and the pre-amplification circuit 16 be connected with image capture module 15 forms.
Wherein, infrared light supply 11 is for sending near infrared light, and this near infrared light is narrow light beam, it can make to be identified target and appear suddenly out in visual field, make itself and background form large contrast, thus image comparatively clearly can be obtained, make the present invention be applied to night-environment.When infrared illumination be mapped to be identified target time, being identified target can reflect infrared light, and this infrared light carries out optically filtering through optical system 12 again.Scanning mechanism 13 is then collected the infrared light after optically filtering, and flows to infrared eye 14.This infrared eye 14 exports for infrared radiation signal being transformed into electric signal, and image capture module 15 is then for being transformed into corresponding digital picture by sightless for human eye signal.Pre-amplification circuit 16 for carrying out distortionless amplification to digital picture, and flows to image identification system 2.
This infrared light supply 1 adopts existing infrarede emitting diode to realize, the infrared eye 14 then preferential WS-600HW type infrared eye adopting Guangzhou Ai Li electron rich Science and Technology Ltd. to produce realizes, the operating temperature range of the infrared eye of this model is-10 DEG C ~+50 DEG C, and detection range is far away.Optical system 12 and scanning mechanism 13 and image capture module 15 then all adopt existing technology to realize.
Image identification system 2 identifies for the image collected this infrared imaging system 1.It is by central processing module 21, the image processing system 22 be connected with central processing module 21, display 23, alarm 24, storer 25, and the noise reduction module 26 be connected with image processing system 22 forms.
Wherein, central processing module 21 is as the control center of this image identification system 2, and it adopts existing single-chip microcomputer to realize.Display 23 is for showing the image being identified target, and storer 25 is then for storing the image of measured target in advance.When image identification system 2 receives the realtime graphic of measured target, storer 25 can contrast the measured target image that this image and its inside store in advance, if contrast unsuccessful, storer 25 can send signal to central processing module 21, allows it start alarm 24 and reports to the police.Image processing system 22, then for processing data image, makes image more clear.Because picture signal is easily subject to the interference of noise in the process of transmission, noise reduction module 26 then can filter out interference noise, makes picture signal return to original effect.
As shown in Figure 2, this image processing system 22 by signal input circuit, the signal processing circuit be connected with signal input circuit, and the trigger circuit be connected with signal processing circuit and tuned circuit form.
Wherein, signal input circuit is by triode Q1, one end is connected with the base stage of triode Q1, the other end is then in turn through resistance R3 that resistance R2 is connected with the emitter of triode Q1 after resistance R1, positive pole is connected with the emitter of triode Q1, the electric capacity C1 of minus earth, and while positive pole is connected with the collector of triode Q1, negative pole is then connected with signal processing circuit, the electric capacity C2 of ground connection forms.The emitter of described triode Q1 is connected with signal processing circuit.
And signal processing circuit is by process chip U, resistance R4, resistance R5, resistance R6, resistance R7, electric capacity C3, electric capacity C4, electric capacity C5, electric capacity C6 and diode D1 form.
During connection, the P pole of this diode D1 is connected with the SW1 pin of process chip U, its N pole is ground connection after electric capacity C3 then, one end of resistance R4 is connected with the N pole of diode D1, ground connection while its other end is then connected with the GND pin of process chip U after resistance R5, the positive pole of electric capacity C4 is connected with the CTRL pin of process chip U, its minus earth, one end of resistance R6 is connected with the CTRL pin of process chip U, its other end is ground connection after electric capacity C5 then, the positive pole of electric capacity C6 is connected with the SS pin of process chip U, its negative pole is then connected with trigger circuit, one end of resistance R7 is connected with the PGOOD pin of process chip U, its other end is then connected with tuned circuit.
Meanwhile, the VIN pin of described process chip U is connected with the emitter of triode Q1, its FB pin is then connected with the tie point of resistance R5 with resistance R4, its CTRL pin is then connected with the negative pole of electric capacity C2, its SHDN pin is then connected with trigger circuit.In order to ensure implementation result, this process chip U preferentially adopts LT1942 integrated circuit to realize.
Trigger circuit are then by flip chip K, and triode Q4, resistance R12, resistance R13, resistance R14, electric capacity C11 and electric capacity C12 form.During connection, one end of this resistance R12 is connected with the base stage of triode Q4, its other end is then connected with the OUT pin of flip chip K, one end of resistance R14 is connected with the emitter of triode Q4, its other end is then connected with the GND pin of flip chip K after electric capacity C12, and one end of resistance R13 is connected with the LX pin of flip chip K, its other end is then connected with the FB pin of flip chip K after electric capacity C11.The IN pin of described flip chip K is connected with the SHDN pin of process chip U, its EN pin is then connected with the negative pole of electric capacity C6, its GND pin ground connection; The collector of described triode Q4 is then connected with tuned circuit.In order to better implement the present invention, this flip chip K is preferably EMD2050 integrated circuit to realize.
Tuned circuit can make image more stable, be beneficial to the present invention to identify image, it is by triode Q2, triode Q3, N pole is connected with the collector of triode Q2 after resistance R8 through inductance L 1 in turn, the varactor D2 that P pole is then connected with the emitter of triode Q3 after electric capacity C8, one end is connected with the P pole of varactor D2, the other end then meets the resistance R11 of-15V voltage, positive pole is connected with the P pole of varactor D2, the electric capacity C9 that negative pole is then connected with the collector of triode Q4, positive pole is connected with the emitter of triode Q3, the tunable capacitor C10 of negative pole then ground connection, one end is connected with the emitter of triode Q2, the other end then connects the inductance L 2 of+15V voltage after resistance R9, positive pole is connected with the tie point of inductance L 2 with resistance R9, the electric capacity C7 of minus earth, and one end is connected with the positive pole of electric capacity C7, the resistance R10 that the other end is then connected with the base stage of triode Q3 forms.The base stage of described triode Q2 is connected with the PGOOD pin of process chip U after resistance R7, the collector then ground connection of triode Q3.
As shown in Figure 3, this pre-amplification circuit 16 is by amplification chip U1, and triode Q5, field effect transistor MOS1, resistance R15, resistance R16, resistance R17, resistance R18, resistance R19, electric capacity C13, electric capacity C14, electric capacity C15, electric capacity C16, diode D3 and diode D4 form.
During connection, the negative pole of electric capacity C14 is connected with the IN pin of amplification chip U1 after resistance R17, its positive pole is then as the input end of this pre-amplification circuit 16, the positive pole of electric capacity C15 is connected with the negative pole of electric capacity C14, its negative pole is then connected with the VCC pin of amplification chip U1 after resistance R18 through diode D3 in turn, the positive pole of electric capacity C13 is connected with the NF pin of amplification chip U1 after resistance R15, its negative pole is then connected with the source electrode of field effect transistor MOS1 after resistance R19, one end of resistance R16 is connected with the NF pin of amplification chip U1, ground connection while its other end is then connected with the GND pin of amplification chip U1, the positive pole of electric capacity C16 is connected with the NSC pin of amplification chip U1, its negative pole is then connected with the emitter of triode Q5, the N pole of diode D4 is connected with the emitter pole of triode Q5, its P pole is then connected with the drain electrode of field effect transistor MOS1.
The base stage of described triode Q5 is connected with the OUT pin of amplification chip U1, its grounded emitter, its collector are then connected with the ALC pin of amplification chip U1.The grid of described field effect transistor MOS1 is then connected with the collector of triode Q5.The emitter of described triode Q5 also as this pre-amplification circuit 16 output terminal.
The amplifier formed through amplification chip U1, resistance R17 and resistance R16 after picture signal conveying is come in amplifies, the signal lock frequency circuit that picture signal after amplification is made up of triode Q5, diode D4 and MOS1 processes, thus the picture signal that this pre-amplification circuit is exported is more clear.Electric capacity C13 and electric capacity C14 then can suppress fluctuation voltage, avoids fluctuation voltage to impact picture signal.In order to reach better implementation result, this amplification chip U1 is preferably MC2830 integrated circuit to realize.
Noise reduction module 26 is emphasis place of the present invention, and as shown in Figure 4, it is by amplifier P1, amplifier P2, triode Q6, triode Q7, triode Q8, field effect transistor MOS2, Sheffer stroke gate IC1, Sheffer stroke gate IC2, resistance R20, resistance R21, resistance R22, resistance R23, electric capacity C17 and diode D5 form.
During connection, ground connection while the N pole of this diode D5 is connected with the output terminal of amplifier P1, its P pole is then connected with second input end of Sheffer stroke gate IC1 after resistance R20, one end of resistance R21 is connected with the first input end of Sheffer stroke gate IC1, its other end is then connected with the output terminal of Sheffer stroke gate IC2 after electric capacity C17, one end of resistance R22 is connected with the output terminal of Sheffer stroke gate IC1, its other end is then connected with the tie point of electric capacity C17 with resistance R21, and resistance R23 is then serially connected between the emitter and collector of triode Q7.
Meanwhile, the minus earth of described amplifier P1, its positive pole are then then connected with the emitter of triode Q6 as the input end of this noise reduction module 26, its output terminal.The base stage of described triode Q7 is connected with the base stage of triode Q6, its collector is then connected with the collector of triode Q6, its emitter is then connected with the drain electrode of field effect transistor MOS2.The drain electrode of described field effect transistor MOS2 is connected with the negative pole of amplifier P2, its grid is then connected with the output terminal of amplifier P2, its source electrode is then connected with the emitter of triode Q8.The negative pole of described amplifier P2 is then as output terminal, its plus earth of this noise reduction module 26.The base stage of described triode Q8 is connected with the tie point of electric capacity C17 with resistance R21, its collector then ground connection.The second input end grounding, its first input end of described Sheffer stroke gate IC2 are then connected with the output terminal of Sheffer stroke gate IC1.
Picture signal conveying carries out amplification process through amplifier P1 after coming in, picture signal after this amplification is then again via triode Q6, triode Q7, resistance R23, the mean filter that field effect transistor MOS2 and amplifier P2 is formed carries out filtering process, this mean filter effectively can filter out the additive noise in picture signal, avoids picture signal to be subject to the interference of noise.
As mentioned above, just the present invention can well be realized.

Claims (9)

1. based on an enlarge leadingly formula infrared imaging image identification system for noise reduction process, it is by infrared imaging system (1), and the image identification system (2) be connected with infrared imaging system (1) forms, described infrared imaging system (1) is by infrared light supply (11), the optical system (12) be connected with infrared light supply (11), the scanning mechanism (13) be connected with optical system (12), the infrared eye (14) be connected with scanning mechanism (13), the image capture module (15) be connected with infrared eye (14), and the pre-amplification circuit (16) be connected with image capture module (15) forms, described image identification system (2) is then by central processing module (21), and the image processing system (22) be connected with central processing module (21), display (23), alarm (24) and storer (25) form, it is characterized in that: described image identification system (2) is also provided with noise reduction module (26), and this noise reduction module (26) is connected with image processing system (22), described noise reduction module (26) is by amplifier P1, amplifier P2, triode Q6, triode Q7, triode Q8, field effect transistor MOS2, Sheffer stroke gate IC1, Sheffer stroke gate IC2, N pole is connected with the output terminal of amplifier P1, the diode D5 of ground connection while P pole is then connected with second input end of Sheffer stroke gate IC1 after resistance R20, one end is connected with the first input end of Sheffer stroke gate IC1, the resistance R21 that the other end is then connected with the output terminal of Sheffer stroke gate IC2 after electric capacity C17, one end is connected with the output terminal of Sheffer stroke gate IC1, the resistance R22 that the other end is then connected with the tie point of electric capacity C17 with resistance R21, and the resistance R23 between the emitter and collector being serially connected in triode Q7 forms, the minus earth of described amplifier P1, its positive pole are then then connected with the emitter of triode Q6 as the input end of this noise reduction module (26), its output terminal, the base stage of described triode Q7 is connected with the base stage of triode Q6, its collector is then connected with the collector of triode Q6, its emitter is then connected with the drain electrode of field effect transistor MOS2, the drain electrode of described field effect transistor MOS2 is connected with the negative pole of amplifier P2, its grid is then connected with the output terminal of amplifier P2, its source electrode is then connected with the emitter of triode Q8, the negative pole of described amplifier P2 is then as output terminal, its plus earth of this noise reduction module (26), the base stage of described triode Q8 is connected with the tie point of electric capacity C17 with resistance R21, its collector then ground connection, the second input end grounding, its first input end of described Sheffer stroke gate IC2 are then connected with the output terminal of Sheffer stroke gate IC1.
2. a kind of enlarge leadingly formula infrared imaging image identification system based on noise reduction process according to claim 1, it is characterized in that: described pre-amplification circuit (16) is then by amplification chip U1, triode Q5, field effect transistor MOS1, negative pole is connected with the IN pin of amplification chip U1 after resistance R17, positive pole is then as the electric capacity C14 of the input end of this pre-amplification circuit (16), positive pole is connected with the negative pole of electric capacity C14, negative pole is then in turn through electric capacity C15 that diode D3 is connected with the VCC pin of amplification chip U1 after resistance R18, positive pole is connected with the NF pin of amplification chip U1 after resistance R15, the electric capacity C13 that negative pole is then connected with the source electrode of field effect transistor MOS1 after resistance R19, one end is connected with the NF pin of amplification chip U1, the resistance R16 of ground connection while the other end is then connected with the GND pin of amplification chip U1, positive pole is connected with the NSC pin of amplification chip U1, the electric capacity C16 that negative pole is then connected with the emitter of triode Q5, and N pole is connected with the emitter pole of triode Q5, the diode D4 that P pole is then connected with the drain electrode of field effect transistor MOS1 forms, the base stage of described triode Q5 is connected with the OUT pin of amplification chip U1, its grounded emitter, its collector are then connected with the ALC pin of amplification chip U1, the grid of described field effect transistor MOS1 is then connected with the collector of triode Q5, the emitter of described triode Q5 is also as the output terminal of (16) of this pre-amplification circuit.
3. a kind of enlarge leadingly formula infrared imaging image identification system based on noise reduction process according to claim 2, it is characterized in that: described image processing system (22) is then by signal input circuit, the signal processing circuit be connected with signal input circuit, and the trigger circuit be connected with signal processing circuit and tuned circuit form; Described signal input circuit is by triode Q1, one end is connected with the base stage of triode Q1, the other end is then in turn through resistance R3 that resistance R2 is connected with the emitter of triode Q1 after resistance R1, positive pole is connected with the emitter of triode Q1, the electric capacity C1 of minus earth, and while positive pole is connected with the collector of triode Q1, negative pole is then connected with signal processing circuit, the electric capacity C2 of ground connection forms; The emitter of described triode Q1 is connected with signal processing circuit.
4. a kind of enlarge leadingly formula infrared imaging image identification system based on noise reduction process according to claim 3, it is characterized in that: described signal processing circuit is by process chip U, P pole is connected with the SW1 pin of process chip U, N pole is the diode D1 of ground connection after electric capacity C3 then, one end is connected with the N pole of diode D1, the resistance R4 of ground connection while the other end is then connected with the GND pin of process chip U after resistance R5, positive pole is connected with the CTRL pin of process chip U, the electric capacity C4 of minus earth, one end is connected with the CTRL pin of process chip U, the other end is the resistance R6 of ground connection after electric capacity C5 then, positive pole is connected with the SS pin of process chip U, the electric capacity C6 that negative pole is then connected with trigger circuit, and one end is connected with the PGOOD pin of process chip U, the resistance R7 that the other end is then connected with tuned circuit forms, the VIN pin of described process chip U is connected with the emitter of triode Q1, its FB pin is then connected with the tie point of resistance R5 with resistance R4, its CTRL pin is then connected with the negative pole of electric capacity C2, its SHDN pin is then connected with trigger circuit.
5. a kind of enlarge leadingly formula infrared imaging image identification system based on noise reduction process according to claim 4, it is characterized in that: described trigger circuit are by flip chip K, triode Q4, one end is connected with the base stage of triode Q4, the resistance R12 that the other end is then connected with the OUT pin of flip chip K, one end is connected with the emitter of triode Q4, the resistance R14 that the other end is then connected with the GND pin of flip chip K after electric capacity C12, and one end is connected with the LX pin of flip chip K, the resistance R13 that the other end is then connected with the FB pin of flip chip K after electric capacity C11 forms, the IN pin of described flip chip K is connected with the SHDN pin of process chip U, its EN pin is then connected with the negative pole of electric capacity C6, its GND pin ground connection, the collector of described triode Q4 is then connected with tuned circuit.
6. a kind of enlarge leadingly formula infrared imaging image identification system based on noise reduction process according to claim 5, it is characterized in that: described tuned circuit is by triode Q2, triode Q3, N pole is connected with the collector of triode Q2 after resistance R8 through inductance L 1 in turn, the varactor D2 that P pole is then connected with the emitter of triode Q3 after electric capacity C8, one end is connected with the P pole of varactor D2, the other end then meets the resistance R11 of-15V voltage, positive pole is connected with the P pole of varactor D2, the electric capacity C9 that negative pole is then connected with the collector of triode Q4, positive pole is connected with the emitter of triode Q3, the tunable capacitor C10 of negative pole then ground connection, one end is connected with the emitter of triode Q2, the other end then connects the inductance L 2 of+15V voltage after resistance R9, positive pole is connected with the tie point of inductance L 2 with resistance R9, the electric capacity C7 of minus earth, and one end is connected with the positive pole of electric capacity C7, the resistance R10 that the other end is then connected with the base stage of triode Q3 forms, the base stage of described triode Q2 is connected with the PGOOD pin of process chip U after resistance R7, the collector then ground connection of triode Q3.
7. a kind of enlarge leadingly formula infrared imaging image identification system based on noise reduction process according to any one of claim 4 ~ 6, is characterized in that: described process chip U is LT1942 integrated circuit.
8. a kind of enlarge leadingly formula infrared imaging image identification system based on noise reduction process according to claim 5 or 6, is characterized in that: described flip chip K is EMD2050 integrated circuit.
9. a kind of enlarge leadingly formula infrared imaging image identification system based on noise reduction process according to any one of claim 2 ~ 6, is characterized in that: described amplification chip U1 is MC2830 integrated circuit.
CN201510292446.0A 2015-05-30 2015-05-30 A kind of preposition amplifying type infrared imaging image identification system based on noise reduction process Expired - Fee Related CN104881654B (en)

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