CN104867928B - The preparation method of gate metal and contact metal in a kind of cmos device - Google Patents
The preparation method of gate metal and contact metal in a kind of cmos device Download PDFInfo
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- CN104867928B CN104867928B CN201510215886.6A CN201510215886A CN104867928B CN 104867928 B CN104867928 B CN 104867928B CN 201510215886 A CN201510215886 A CN 201510215886A CN 104867928 B CN104867928 B CN 104867928B
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Abstract
The invention discloses the preparation method of gate metal and contact metal in a kind of cmos device, it is included in using high K dielectric and polysilicon to cover buffer layer between first layer in the CMOS structure of grid, and it is planarized to polysilicon and exposes, lithographic definition contacts hole site, etching forms contact hole, remove the polysilicon in grid, form gate trench, cover the first metal successively on gate trench and contact hole, second metal is as gate work-function metal, contact hole diffusion impervious layer and gate metal, contact metal, second metal is planarized, the second metal upright post of protrusion is formed above gate trench and contact hole site using photoetching and etching, etching barrier layer is covered on the second metal upright post, two inter-level dielectric separation layer of growth regulation is simultaneously planarized, second metal upright post is exposed.The present invention can reduce the influence to device performance, realize the disposal molding of gate metal and contact metal, reduce processing step.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, more particularly, in a kind of advanced cmos device
The preparation method of gate metal and contact metal.
Background technology
In the MOS transistor technique of 45nm technology nodes and the above, typically using silica as gate oxidation
Layer, using polysilicon as grid material.Further with semiconductor devices physical dimension reduces, gate oxide thickness also with
Reduction, this will bring higher and higher gate leak current.In 32nm technology nodes and following, it is situated between on a large scale using high K
Matter/metal gate (HKMG) structure replaces gate oxide/polysilicon gate construction as solution.At present in 32nm technology sections
On point, after HKMG structures, gate leak current has been reduced to original 1/10th.
The process aspect of HKMG structure transistors is being made, there is two kinds of Integrated Solutions：Front gate Integrated Solution (Gate-
) and rear grid Integrated Solution (Gate-Last) First.Use Gate-Last Integrated Solutions, the benefit of the program substantially now
It is to eliminate the multiple heat treatment that metal gates are subject to including the annealing of high temperature knot, and then cause the drift of electric property
Influence.Gate-Last can be divided into high K dielectric (HK) again first to be done, (HK First＆MG Last) and HK/MG is after metal gate (MG)
(HK＆MG Last) both schemes are all done afterwards.
The high dielectric material of high K dielectric, that is, dielectric constant；Metal gate then generally comprises workfunction metal and gate metal
(or being trench fill material).Suitable transistor threshold voltage (Vt) is capable of providing using suitable workfunction metal, and
And it can effectively alleviate electron mobility degeneration；Gate metal then needs to select the gold good with workfunction metal adhesion, resistance is low
Belong to.
The processing step of current rear grid Integrated Solution is usually：
1) metal gates are made using HK+ polysilicon process, is then covering silica separation layer above；
2) (CMP) planarization is chemically-mechanicapolish polished to silica separation layer, until polysilicon exposes, is then passed through
Wet etching removes the polysilicon in grid, forms gate trench；
3) workfunction metal and gate metal are deposited respectively in gate trench；
4) gate metal and workfunction metal outside CMP gate trench, then deposits etching barrier layer (generally respectively
SiN or SiCN) and silica, and carry out the making in subsequent touch hole.
Using the device made by above-mentioned grid Integrated Solution afterwards as shown in Figure 1, Fig. 1 is existing use HKMG structures and makes
Make the CMOS structure schematic diagram after contact hole.The CMOS structure includes the shallow trench isolation being formed in semiconductor substrate layer 100
(STI), metal silicide 103 conductive on source and drain injection zone (Source, Drain) and source-drain area, and be formed at and partly lead
HKMG structures on body substrate layer, contact hole；Wherein HKMG structures include HK the dielectric materials 109, (bag of MG materials 108 and 107
Include workfunction metal 108 and gate metal 107), its sidepiece has grid curb wall 106；Contact hole is filled with contact metal
104, and there is metal barrier 105；Covered with silica separation layer 101,102 outside HKMG structures and contact hole.Should
CMOS structure includes the PMOS area and NMOS area of diagram.
In the above-mentioned latter in grid Integrated Solution, it usually needs use to three CMP process, that is, open polysilicon CMP (Poly
Opening CMP), metal gates CMP (Metal gate CMP) and contact metal CMP (Contact CMP).Moreover,
Also there are following problems during Metal gate CMP：
1) grid caused by short circuit caused by polishing not enough and excessive crossing polish are thinning, and cause what high gate resistance was brought
Small process window；
2) the interior uniformity of good chip unit (Die) is needed；
3) small-sized due to grid (gate), influence of the defects of CMP causes (defect) to yield of devices is very big.
With the development of device Integrated Solution, the metal material of grid is also changed, from traditional DOPOS doped polycrystalline silicon
(Poly) change to the metallic aluminium (Al) used suitable for the first generation HKMG of 28nm~45nm, then change to suitable for 28nm with
The tungsten (W) that lower second generation HKMG is used；And workfunction metal generally also originally can be used for making using TiN, TaN etc.
Make the material of diffusion impervious layer.2 points of the above is the present invention provides improved possibility.
The content of the invention
It is an object of the invention to overcome drawbacks described above existing in the prior art, there is provided gate metal in a kind of cmos device
With the preparation method of contact metal, in the rear grid Integrated Solution for making HKMG structure transistors, substituted by using etching
CMP process carries out the making of gate metal and contact metal, can greatly reduce traditional handicraft to device performance
Influence, and can realize the disposable formation of gate metal and contact metal.
To achieve the above object, technical scheme is as follows：
The preparation method of gate metal and contact metal in a kind of cmos device, comprises the following steps：
Step S01：One is provided using high K dielectric and polysilicon as the CMOS structure of grid, is covered in the CMOS structure
First interlayer buffer layer, and cmp planarization to polysilicon exposes；
Step S02：Go out the position of contact hole by lithographic definition, and etch and form contact hole；Remove the polycrystalline in grid
Silicon, forms gate trench；
Step S03：The first metal is covered on the gate trench and contact hole as gate work-function metal and contact
Hole diffusion impervious layer, then, two metal of growth regulation is as gate metal and contact metal；
Step S04：Cmp planarization is carried out to second metal, unwanted the is removed successively using photoetching and etching
Two metals and the first metal, to form the second metal upright post of protrusion above gate trench and contact hole site；
Step S05：Etching barrier layer is covered on second metal upright post, then, the isolation of two inter-level dielectric of growth regulation
Layer simultaneously carries out cmp planarization, and second metal upright post is exposed.
Preferably, first metal is TiN, TiAl, TaN, TiC or TaC.
Preferably, first metal is formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition processes.
Preferably, the thickness of first metal is 15~25 nanometers.
Preferably, second metal is Al, W, Ti, AlCu or TiAl.
Preferably, second metal is formed by chemical vapor deposition or physical vapor deposition process.
Preferably, the etching barrier layer materials are SiN or SiCN.
Preferably, the etching barrier layer is formed by chemical vapor deposition or atomic layer deposition processes.
Preferably, the thickness of the etching barrier layer is 15~25 nanometers.
Preferably, in step S02, the polysilicon in grid is removed by dry or wet etch.
It is an advantage of the current invention that the present invention is prepared into the integrated approach of contact hole preparation with rear grid technique, by adopting
The making of gate metal and contact metal is carried out with etching replacement CMP process, is only utilized in some committed steps and interface
CMP process carries out planarization application, and is not involved in the formation of resulting devices, thus reduces its influence to device performance；This
Outside, the present invention uses the first identical metal as gate work-function metal and contact metal diffusion impervious layer, and uses
The second identical metal as gate metal and contact metal, it can be achieved that gate metal and contact metal it is disposable into
Type, so as to reduce processing step using this new integrated manufacturing method.
Brief description of the drawings
Fig. 1 is existing using HKMG structures and to make the CMOS structure schematic diagram after contact hole；
Fig. 2 is the flow chart of the preparation method of gate metal and contact metal in a kind of cmos device of the present invention；
Fig. 3~Fig. 8 is the structure diagram that a preferred embodiment of the present invention forms device according to the method for Fig. 2.
Embodiment
Below in conjunction with the accompanying drawings, the embodiment of the present invention is described in further detail.
It should be noted that in following embodiments, when embodiments of the present invention are described in detail, in order to clear
Ground represents the structure of the present invention in order to illustrate, special not draw to the structure in attached drawing according to general proportion, and has carried out part
Amplification, deformation and simplified processing, therefore, should avoid in this, as limitation of the invention to understand.
In embodiment of the invention below, referring to Fig. 2, Fig. 2 is grid in a kind of cmos device of the present invention
The flow chart of the preparation method of metal and contact metal；Meanwhile Fig. 3~Fig. 8 is referred to, Fig. 3~Fig. 8 is that the present invention one is preferable
Embodiment forms the structure diagram of device according to the method for Fig. 2.As shown in Fig. 2, grid gold in a kind of cmos device of the present invention
Belong to the preparation method with contact metal, comprise the following steps：
As shown in frame 01, step S01：A CMOS structure using high K dielectric and polysilicon as grid is provided, in the CMOS
Buffer layer between covering first layer in structure, and cmp planarization to polysilicon exposes.
Refer to Fig. 3.First, a CMOS structure substrate is prepared using rear grid Integrated Solution (Gate-Last).The CMOS
Structural substrates can include substrate layer 100 and the grid layer 200 containing the first interlayer buffer layer 204.The substrate layer 100 can
With using known any types in electronic field, as body silicon, semiconductor on insulator (SOI), completely depleted, part depletion,
FIN types or other types substrate.Also the internal structure of the substrate layer 100 can be prepared using existing common process, including
Prepare metal silicide conductive on shallow trench isolation (STI), source and drain injection zone (Source, Drain) and source-drain area
103.The grid layer 200 can be made using such as HK first＆MG last techniques (i.e. high K dielectric first do, done after metal gate)
It is standby, including prepare HK dielectric materials 201, sacrificial gate of polysilicon 202, side wall 203 and the first interlayer is covered between grid
Buffer layer 204, then planarizes the first interlayer buffer layer 204 by chemically-mechanicapolish polishing (CMP), polishes
Expose to sacrificial gate of polysilicon 202, and form the surface of planarization, so that obtaining the present invention prepares gate metal and contact hole
CMOS structure substrate needed for the method for metal.The CMOS structure substrate includes the PMOS area and NMOS area of diagram.
As shown in frame 02, step S02：Go out the position of contact hole by lithographic definition, and etch and form contact hole；Remove grid
Extremely interior polysilicon, forms gate trench.
Refer to Fig. 4.Next, contact hole 205 is gone out by lithographic definition on the first interlayer buffer layer 204
Position, and etch contact hole groove to the source and drain areas and metal silicide Ohmic contact of bottom, form source/drain contact hole
205 lower areas；Also, 202 material of sacrificial gate of polysilicon in wet method or dry etching removal grid can be used, forms grid
Pole groove 206.
As shown in frame 03, step S03：The first metal is covered on the gate trench and contact hole as gate work-function
Metal and contact hole diffusion impervious layer, then, two metal of growth regulation is as gate metal and contact metal.
Refer to Fig. 5.Next, the deposited metal 300 on the grid layer 200 of the substrate, including is deposited successively
One metal 301 and the second metal 302, metal layer 300 are covered gate trench 206 and contact hole 205.Wherein, by first
Metal 301 is used in conjunction with material as gate work-function metal and contact hole diffusion impervious layer, using the second metal 302 as grid
Pole metal and contact metal are used in conjunction with material, so as to form contact hole respectively on contact hole 205 and gate trench 206
Hypomere metal 207 and grid 208 (it is located at grid layer 200).
As optional embodiment, first metal 301 can use TiN, TiAl, TaN, TiC or TaC material.
Further, first metal 301 can pass through chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition
(ALD) etc. technique is formed.Preferably, the thickness of first metal 301 is 15~25 nanometers.
As optional embodiment, second metal 302 can use Al, W, Ti, AlCu or TiAl material.Into one
Step ground, second metal 302 can be formed by the technique such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).
As shown in frame 04, step S04：Cmp planarization is carried out to second metal, is removed successively using photoetching and etching
Unwanted second metal and the first metal, are stood with forming the second metal of protrusion above gate trench and contact hole site
Column.
Refer to Fig. 6.Next, cmp planarization is carried out to second metal 302 (carries out CMP to metal layer 300
Planarization), during thickness (being determined according to technological requirement) certain to residue by cmp planarizationization, defined using photoresist 303
Contact hole, then, as shown in fig. 7, removing unwanted second metal and the first metal successively using etching, that is, removes contact hole
With the second metal and the first metal of exterior domain.After over etching, protrusion is formd above gate trench and contact hole site
The second metal upright post 304, i.e. contact metal column 304.This, which founds columnar contact metal, includes connecing positioned at source-drain electrode
Contact hole metal and the contact metal on grid.That is, part of second metal in gate trench is formed
Gate metal, in the position of source-drain electrode contact hole forms contact metal column, which is really lower part edge
In the first interlayer buffer layer 204 of grid layer 200, upper part is exposed on surface, and grid of extending out on grid
Contact metal.
As shown in frame 05, step S05：Etching barrier layer is covered on second metal upright post, then, grows the second layer
Between buffer layer and carry out cmp planarization, second metal upright post is exposed.
Refer to Fig. 8.Next, covering one layer of etching barrier layer 305 on the second metal upright post 304, on the one hand can be
Follow-up etching provides barrier layer, on the other hand can be as the barrier layer of contact metal 304.As optional embodiment party
Formula, 305 material of etching barrier layer can use SiN or SiCN.Further, the etching barrier layer 305 can pass through chemistry
The technique such as vapor deposition (CVD) or atomic layer deposition (ALD) is formed.Preferably, the thickness of the etching barrier layer 305 for 15~
25 nanometers.Then, the two inter-level dielectric separation layer 401 of growth regulation on etching barrier layer 305, forms contact metal separation layer
400, and carry out cmp planarization, after being polished to certain thickness, second metal upright post 304 is exposed, that is, expose source and drain and
The contact metal 304 of grid.First, second inter-level dielectric separation layer 204,401 materials can use such as silica.It
Afterwards, existing subsequent interconnection technique can be used to complete the making of whole device.
In conclusion the present invention is prepared into the integrated approach of contact hole preparation with rear grid technique, replaced by using etching
The making of gate metal and contact metal is carried out for CMP process, only in some committed steps and interface using CMP process into
Row planarization application, and the formation of resulting devices is not involved in, thus reduce its influence to device performance；It is in addition, of the invention
Using the first identical metal as gate work-function metal and contact metal diffusion impervious layer, and use identical second
Metal as gate metal and contact metal, it can be achieved that the disposal molding of gate metal and contact metal, so as to utilize
This new integrated manufacturing method reduces processing step.
It is above-described to be merely a preferred embodiment of the present invention, the embodiment and the patent guarantor for being not used to the limitation present invention
Scope, therefore the equivalent structure change that every specification and accompanying drawing content with the present invention is made are protected, similarly should be included in
In protection scope of the present invention.
Claims (10)
1. the preparation method of gate metal and contact metal in a kind of cmos device, it is characterised in that comprise the following steps：
Step S01：One is provided using high K dielectric and polysilicon as the CMOS structure of grid, first is covered in the CMOS structure
Inter-level dielectric separation layer, and cmp planarization to polysilicon exposes；
Step S02：Go out the position of contact hole by lithographic definition, and etch and form contact hole；Remove the polysilicon in grid, shape
Into gate trench；
Step S03：The first metal is covered on the gate trench and contact hole as gate work-function metal and contact hole to expand
Barrier layer is dissipated, then, two metal of growth regulation is as gate metal and contact metal；
Step S04：Cmp planarization is carried out to second metal, unwanted second gold medal is removed using photoetching and etching successively
Category and the first metal, to form the second metal upright post of protrusion above gate trench and contact hole site；
Step S05：Etching barrier layer is covered on second metal upright post, then, two inter-level dielectric separation layer of growth regulation is simultaneously
Cmp planarization is carried out, second metal upright post is exposed.
2. the preparation method of gate metal and contact metal in cmos device according to claim 1, it is characterised in that
First metal is TiN, TiAl, TaN, TiC or TaC.
3. the preparation method of gate metal and contact metal in cmos device according to claim 2, it is characterised in that
First metal is formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition processes.
4. the preparation method of gate metal and contact metal in cmos device according to claim 1 or 2, its feature exists
In the thickness of first metal is 15~25 nanometers.
5. the preparation method of gate metal and contact metal in cmos device according to claim 1, it is characterised in that
Second metal is Al, W, Ti, AlCu or TiAl.
6. the preparation method of gate metal and contact metal in cmos device according to claim 5, it is characterised in that
Second metal is formed by chemical vapor deposition or physical vapor deposition process.
7. the preparation method of gate metal and contact metal in cmos device according to claim 1, it is characterised in that
The etching barrier layer materials are SiN or SiCN.
8. the preparation method of gate metal and contact metal in cmos device according to claim 7, it is characterised in that
The etching barrier layer is formed by chemical vapor deposition or atomic layer deposition processes.
9. the preparation method of gate metal and contact metal in the cmos device according to claim 1 or 7, its feature exists
In the thickness of the etching barrier layer is 15~25 nanometers.
10. the preparation method of gate metal and contact metal in cmos device according to claim 1, its feature exists
In, in step S02, pass through dry or wet etch remove grid in polysilicon.
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| CN102881573A (en) * | 2011-07-11 | 2013-01-16 | 中国科学院微电子研究所 | Transistor and semiconductor device, and production methods of transistor and semiconductor device |
| CN102983098A (en) * | 2011-09-07 | 2013-03-20 | 中国科学院微电子研究所 | Manufacturing method of electrode and connecting wire in rear grid technology |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020142531A1 (en) * | 2001-03-29 | 2002-10-03 | Hsu Sheng Teng | Dual damascene copper gate and interconnect therefore |
| US7863123B2 (en) * | 2009-01-19 | 2011-01-04 | International Business Machines Corporation | Direct contact between high-κ/metal gate and wiring process flow |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6329232B1 (en) * | 1999-06-30 | 2001-12-11 | Hyundai Electronics Co., Ltd. | Method of manufacturing a semiconductor device |
| CN101471379A (en) * | 2007-12-25 | 2009-07-01 | 恩益禧电子股份有限公司 | Semiconductor device and process for manufacturing same |
| CN102468221A (en) * | 2010-11-11 | 2012-05-23 | 中国科学院微电子研究所 | Method for processing contact holes in complementary metal oxide semiconductor (CMOS) device by gate-last process |
| CN102881573A (en) * | 2011-07-11 | 2013-01-16 | 中国科学院微电子研究所 | Transistor and semiconductor device, and production methods of transistor and semiconductor device |
| CN102983098A (en) * | 2011-09-07 | 2013-03-20 | 中国科学院微电子研究所 | Manufacturing method of electrode and connecting wire in rear grid technology |
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