CN104867914A - Multi-chip system - Google Patents
Multi-chip system Download PDFInfo
- Publication number
- CN104867914A CN104867914A CN201410062792.5A CN201410062792A CN104867914A CN 104867914 A CN104867914 A CN 104867914A CN 201410062792 A CN201410062792 A CN 201410062792A CN 104867914 A CN104867914 A CN 104867914A
- Authority
- CN
- China
- Prior art keywords
- chip layer
- multichip system
- chip
- voltage
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a multi-chip system. The multi-chip system comprises multiple chip layers, the chip layers are stacked vertically and are electrically connected via a TSV (Through-Silicon-Via) connecting piece, and at least one of the chip layers comprises a single voltage domain. Thus, the multi-chip system has the advantages that power consumption can be reduced more effectively, manufacture is simplified, and the manufacture cost is reduced.
Description
Technical field
The present invention relates in general to integrated technology.Particularly, the present invention relates to SOC (system on a chip) (System-on-Chip(SOC)) design, specifically relate to the voltage-island designs for the SOC (system on a chip) in the multichip system comprising multiple chip layer.
Background technology
For system-on-chip designs, power consumption is an important Consideration.The fast development of manufacturing process makes designer can integrated more function on a single chip.But integrated more function is applied with a lot of strict restriction to Power budgets on a single chip.
The use of multiple voltage island is a kind of method reducing power consumption.There is provided lower voltage to reduce dynamically and this idea of leakage power by the part being utilized as the design not in critical path, multiple voltage island concept can reduce the cost of the voltage of the different piece being provided to chip, and multiple voltage island concept relates to the voltage island being concentrated into by multiple core and running in same electrical pressure, and provides single voltage to the module in this voltage island.
Such as, Fig. 1 shows the illustrative example of traditional 2D chip system 100, and this system 100 has three voltage island A, B and C.As shown in Figure 1, block (block) b1-b3 in voltage island C, and at V
ddrun under=1.4V, this voltage is chip-scale voltage.Block b4, b5 and b6 are in voltage island A and at V
ddrun under the lower voltage of=1.3V, block b7, b8 and b9 are in voltage island B and at V
ddrun under the voltage of=1.2V.
Summary of the invention
Although voltage island technology can relax the power problems in two dimension (2D) system-on-chip designs, its power-supply wiring, pre-layout (floor planning), timing closure (timingclosure) and to region and postpone relevant level translator cost etc. in make chip design technique more complicated.Therefore, how effectively block that is compatible, that have identical voltage is flocked together and other drawingdimension such as such as conductor length and key path time sequence etc. can not be disturbed to be a very crucial problem.Particularly, there are some and be limited in during 2D SOC designs the limiting factor using the benefit of voltage island, such as: in 2D SOC designs, set up the complexity that multiple power rail (power supply rails) adds this design, and add the size of chip; Because needs carry out level conversion between two voltage island, cause being difficult to realize fine-grained voltage-island designs; And be all arranged on identical silicon chip due to all designs, be therefore not easy the isolation guaranteeing voltage domain.
In order to alleviate the problems referred to above, various aspects of the present invention provide a kind of voltage-island designs in multichip system, this system comprise multiple vertical stacking and via silicon perforation (Through-Silicon-Via(TSV)) connector electrical connection chip layer.
In the illustrative embodiments embodying first aspect present invention, provide a kind of multichip system.This system comprises multiple vertical stacking and the chip layer be electrically connected by TSV connector, and at least one in wherein said multiple chip layer comprises single voltage domain.
In the illustrative embodiments embodying second aspect present invention, provide a kind of method configuring voltage island in multichip system.This multichip system comprises multiple vertical stacking and the chip layer be electrically connected by TSV connector, and the method comprises at least one in described multiple chip layer is configured to have single voltage domain.
The application described below is other side of the present invention and execution mode.
Accompanying drawing explanation
Accompanying drawing illustrates the present invention in an illustrative manner, and it is not construed as limiting the invention.The parts that numeral identical is in the accompanying drawings identical, wherein:
Fig. 1 shows the illustrative examples of 2D chip system 100 with three voltage island A, B and C;
Fig. 2 shows the schematic diagram of the multichip system 200 according to illustrative embodiments;
Fig. 3 shows the schematic diagram of the multichip system 300 according to illustrative embodiments;
Fig. 4 shows can the schematic diagram of flexible configuration according to the multichip system 400 of illustrative embodiments; And
Fig. 5 is the schematic flow sheet configuring the method for voltage domain in multichip system of the present invention
Embodiment
Some embodiments below with reference to accompanying drawings specifically describe illustrative embodiments more of the present invention.In the following description, some concrete details are described to provide darker understanding of the present invention.But even if it is obvious to those skilled in the art that some that do not have in these details, the present invention also can be implemented.On the other hand, some known processing steps and/or structure are not described in detail to avoid unnecessarily making the present invention become indigestion.
Fig. 2 is the schematic diagram of multichip system 200 according to an illustrative embodiment of the invention.As shown in Figure 2, this multichip system 200 comprises three chip layer, i.e. chip layer 1, chip layer 2 and chip layer 3, and these three chip layer vertical stackings TSV connector (not shown) by cross-layer connect successively.The quantity of chip layer is not limited to three, and this multichip system can be configured to comprise two chip layer or more than three chip layer.A notable feature of multichip system 200 is that chip layer 2 and 3 is wherein configured to have single voltage domain.That is, all blocks in chip layer 2 all run under identical voltage, and all blocks in chip layer 3 also all run under identical voltage.Such as, all in chip layer 2 block b4, b5 and b6 run with the voltage of 1.3v; Block b7, b8 and b9 all in chip layer 3 run with the voltage of 1.2v, and wherein, above-mentioned magnitude of voltage is only as an example, also can be other suitable magnitudes of voltage.
Fig. 3 shows another illustrative embodiments of the present invention.As shown in Figure 3, multichip system 300 comprises three chip layer, i.e. chip layer 1, chip layer 2 and chip layer 3, and these three chip layer vertical stackings TSV connector (not shown) by cross-layer connect successively.Similar to shown in Fig. 2 of illustrative embodiments shown in Fig. 3, but with Fig. 2 unlike, all chip layer 1,2 and 3 in the multichip system shown in Fig. 3 are configured to have single voltage domain all separately.
As shown in Figures 2 and 3, multichip system comprises at least two chip layer, and each layer in described two layers is configured to run under mutually different single voltage domains.Level translator can be set between the level with different voltage domain.Such as, level translator can be configured to change from the chip layer with low voltage territory to the level of chip layer signal with higher voltage domains.This level translator can be asynchronous (that is, not having clock to drive it) or synchronous level translator.This level conversion can be built into trigger (flip-flop) or latch, thus this trigger or latch have some transistors at certain one deck and have other transistor at another layer.
As shown in Figure 5, present invention also offers a kind of method configuring voltage domain in multichip system, this system comprises multiple vertical stacking and the chip layer be electrically connected by TSV connector, and the method comprises at least one in described multiple chip layer is configured to have single voltage domain.The method can comprise and at least two-layer being configured in described multiple chip layer being worked under voltage domain different from each other, and between these two chip layer, configures level translator for the level changing the signal transmitted between these two layers there.The method comprises further and is configured to each chip layer in described multiple chip layer to have their respective single voltage domains.
In one aspect of the invention, because at least one chip layer is configured to have single voltage domain, therefore make electric power network design become more simple, thus pre-layout region can be saved, such as power source planning.
In addition, because at least one chip layer has its oneself voltage domain, thus the present invention can provide better voltage domain to isolate.
Such as, the present invention allows voltage island or voltage domain design flexibly, thus can save power consumption better.Particularly, because silicon perforation connector can provide connection quickly between each chip layer, and level conversion also have been bored a hole (the signal demand level conversion only from low voltage territory to higher voltage domains by silicon, such as, in Fig. 2 from bottom to intermediate layer or intermediate layer to top layer, or in Fig. 3 from bottom to intermediate layer or intermediate layer to top layer), therefore, it is possible to there is greater flexibility to arrange block to obtain better lower power consumption effect.Such as, in FIG, if block b2 is non-sequential key, but have more signal contact with block b1 and b4, therefore it can not be assigned to during this 2D designs the voltage island with low voltage, and needs to be assigned to V
ddthe voltage island of=1.4v.Execution mode according to Fig. 4 of the present invention, because the perforation of silicon fast between chip layer each in multichip system connects, b2 can be moved into chip layer 3(and have V
dd=1.2v), but itself and chip layer 2(V
dd=1.3v) in b4 and chip layer 1(V
dd=1.4v) in b1 still have and connect fast, thus can more power be saved and the restriction of wiring and sequential can not be violated.
The present invention can also simplify and manufactures and reduce manufacturing cost.Such as, multichip system of the present invention can use different technology nodes and different voltage island.Such as, chip layer (chip layer 2 in such as Fig. 2) can be run under the voltage domain of such as 1.4v with the manufacture of 65nm technology node, and another chip layer (chip layer 3 in such as Fig. 2) can be run under the voltage domain of such as 1.0v with the technology node manufacture of 32nm, this not only can lower power consumption, and can save manufacturing cost.And such voltage-island designs is impossible in 2D SOC designs.
Technical scheme of the present invention can also reduce substrate noise.In the modification of embodiments of the present invention, the voltage island concept be separated can be used in mixed signal SOC design, wherein the simulation part of circuit is assigned to and has more high-tension voltage island, and the numerical portion of circuit is assigned to the voltage island with more low-voltage and more high-tech node, to reduce substrate noise.
And the present invention also can provide better timing closure, because compared with the situation in 2D SOC, the level conversion in the present invention is carried out under the silicon perforation had quickly of crossing over chip layer connects.
It is obvious to those skilled in the art that and can make different amendments and modification when not deviating from the scope of spirit of the present invention and claim to the present invention.Therefore, if fall in the scope of claim and their equivalent to amendment of the present invention and modification, so will be understood that the amendment and modification that present invention covers different embodiments described in the invention.
Claims (15)
1. a multichip system, this system comprises multiple vertical stacking and the chip layer be electrically connected by silicon perforation connector, and at least one in wherein said multiple chip layer comprises single voltage domain.
2. multichip system according to claim 1, wherein said system comprises at least two chip layer, each in these two chip layer is configured to run under different single voltage domains, also be included in the level translator at least between these two chip layer, for the signal between conversion chip layer.
3. multichip system according to claim 2, each of wherein said multiple chip layer comprises single voltage domain.
4. multichip system according to claim 3, at least one in wherein said level translator is synchronous.
5. multichip system according to claim 3, at least one in wherein said level translator is asynchronous.
6. multichip system according to claim 4, at least one in wherein said level translator is included in the transistor in more than one chip layer.
7. multichip system according to claim 5, at least one in wherein said level translator is included in the transistor in more than one chip layer.
8. the multichip system according to any one of claim 1-7, at least one in wherein said multiple chip layer comprises single technology node.
9. multichip system according to claim 8, at least the first chip layer in wherein said multiple chip layer comprises single technology node, and the second chip becomes to comprise single technology node, and the technology node of described first and second chip layer is different.
10. the multichip system according to any one of claim 1-7, wherein said multichip system comprises analog circuit and digital circuit, described analog circuit is included in a chip layer of this multichip system, and described digital circuit is included in another different chip layer, and the chip layer comprising described analog circuit has higher voltage domain than the chip layer comprising described digital circuit.
11. 1 kinds of methods configuring voltage domain in multichip system.This multichip system comprises multiple vertical stacking and by the chip layer of silicon perforation connector electrical connection, the method comprises at least one in described multiple chip layer is configured to have single voltage domain.
12. methods according to claim 11, comprise further and at least two chip layer in described multiple chip layer are configured to run under voltage different from each other, and configure level translator with the level of the signal between conversion chip layer between these at least two chip layer.
13. methods according to claim 12, comprise further and each in described multiple chip layer are configured to have single voltage domain.
14. methods according to claim 13, comprise further and at least one in described multiple chip layer are configured to have single technology node.
15. methods according to claim 13, comprise further and the simulation of the circuit in described multichip system is partly arranged in a chip layer, be configured in by the numerical portion of the circuit in described multichip system in another different chip layer, the voltage domain of this different chip layer is lower than the described described chip layer being configured with described simulation part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410062792.5A CN104867914A (en) | 2014-02-24 | 2014-02-24 | Multi-chip system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410062792.5A CN104867914A (en) | 2014-02-24 | 2014-02-24 | Multi-chip system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104867914A true CN104867914A (en) | 2015-08-26 |
Family
ID=53913645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410062792.5A Pending CN104867914A (en) | 2014-02-24 | 2014-02-24 | Multi-chip system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104867914A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022267030A1 (en) * | 2021-06-25 | 2022-12-29 | 华为技术有限公司 | Switch chip and power supply method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090087196A1 (en) * | 2007-10-02 | 2009-04-02 | Brian Welch | Method and system for split voltage domain transmitter circuits |
| CN102362266A (en) * | 2009-04-13 | 2012-02-22 | 国际商业机器公司 | Voltage conversion and integrated circuits with stacked voltage domains |
-
2014
- 2014-02-24 CN CN201410062792.5A patent/CN104867914A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090087196A1 (en) * | 2007-10-02 | 2009-04-02 | Brian Welch | Method and system for split voltage domain transmitter circuits |
| CN102362266A (en) * | 2009-04-13 | 2012-02-22 | 国际商业机器公司 | Voltage conversion and integrated circuits with stacked voltage domains |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022267030A1 (en) * | 2021-06-25 | 2022-12-29 | 华为技术有限公司 | Switch chip and power supply method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105428349B (en) | Integrated circuit structure | |
| CN104009736B (en) | Low-power consumption master-slave flip-flop | |
| JP2004022877A (en) | Standard cell for multiple power sources, standard cell library for automatic arrangement and wiring, power supply wiring method, and semiconductor integrated device | |
| CN107683474B (en) | Cross-coupled clock signal distribution topology in multi-height sequential cells for uni-directional M1 | |
| US8884662B2 (en) | Method for charge sharing/reuse of electronic circuits | |
| JP2008251666A (en) | Three-dimensional structure semiconductor device | |
| Chan et al. | A resonant global clock distribution for the cell broadband engine processor | |
| JP2007329894A (en) | Signal supply structure and semiconductor device | |
| CN103779325B (en) | Placement scheme for cascaded MOS transistors | |
| CN105680843A (en) | Input output for an integrated circuit | |
| CN105279124B (en) | Integrated circuit with interface circuitry and interface unit for interface circuitry | |
| US20140292374A1 (en) | Method for controlling an integrated circuit | |
| CN104835821A (en) | Integrated circuit chip with global routing channels and application-specific integrated circuits | |
| JP2012227395A (en) | Semiconductor integrated circuit device | |
| JP2012222151A (en) | Semiconductor integrated circuit device | |
| KR20150061588A (en) | Power gate switch architecture | |
| US7844923B2 (en) | Semiconductor integrated circuit designing method, semiconductor integrated circuit device, and electronic device | |
| CN104867914A (en) | Multi-chip system | |
| US8987786B1 (en) | State retention power gated cell | |
| CN204966495U (en) | Cause integrated circuit that reverse engineering is more difficult to integrated circuit | |
| US7212031B2 (en) | Semiconductor device and manufacturing method of the same | |
| JP6640385B2 (en) | System and method for separating power domains in a processing device | |
| CN105680107B (en) | A kind of battery management chip circuit based on SOI technology | |
| US9628077B2 (en) | Dual power swing pipeline design with separation of combinational and sequential logics | |
| US9537471B2 (en) | Three dimensional logic circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150826 |