CN104866459B

CN104866459B - Memory chip

Info

Publication number: CN104866459B
Application number: CN201510289518.6A
Authority: CN
Inventors: 景蔚亮
Original assignee: Shanghai Xinchu Integrated Circuit Co Ltd
Current assignee: Shanghai Xinchu Integrated Circuit Co Ltd
Priority date: 2015-05-29
Filing date: 2015-05-29
Publication date: 2020-01-07
Anticipated expiration: 2035-05-29
Also published as: CN104866459A

Abstract

The invention relates to the field of semiconductor integration, in particular to a memory chip. The invention fully utilizes the unused space of the silicon chip below the 3D storage array, integrates the functions of a south bridge and an IO device function module thereof and/or a trusted platform module/trusted cryptography module (TPM/TCM) chip, and can also take one part of a 3D novel nonvolatile storage chip as the function of a Basic Input Output System (BIOS), and the 3D novel nonvolatile storage chip can also be taken as the nonvolatile part of a hybrid memory or a hybrid buffer. The 3D novel nonvolatile memory chip, the processor and the last-level volatile cache chip outside the chip are stored and packaged in a packaging body through a multi-chip packaging technology, so that the area and wiring of a mother board are greatly reduced, power consumption and cost are saved, meanwhile, the 3D novel nonvolatile memory and the processor are packaged in the same packaging body, the reading speed is greatly improved, and the overall performance of a computer can be improved.

Description

Memory chip

Technical Field

The invention relates to the field of semiconductor integration, in particular to a memory chip.

Background

In a conventional computer architecture, as shown in FIG. 1, a chip on a computer motherboard that is connected to a CPU is called a "Northbridge Chipset" (Northbridge Chipset). The North Bridge (North Bridge) is the dominant component of the motherboard chipset and is used to handle high speed signals, typically CPU and memory (DRAM), Accelerated Graphics Port (AGP) or Serial bus (PCI Express) communications with the south Bridge. The other large-scale chip is a South Bridge Chipset (South Bridge Chipset), which is responsible for communication between I/O buses and has a relatively slow processing speed, such as PCI bus, USB, LAN, ATA, SATA, audio controller, keyboard controller, real-time clock controller, advanced power management, etc. Intel is outstanding in processor technology and market, a memory controller is integrated into a processor from the beginning of an X58 chip, and by the period of P55 and H55/H57, Intel integrates most functions of a north bridge chip into the processor, and the rest is shared by a south bridge chip, the north bridge chip disappears completely, the south bridge chip is also named as a Platform Control Hub (PCH), and only a PCH chip is left on the whole mainboard of the processor chip, and the structure is shown in FIG. 2. This has the advantage of saving more space on the motherboard to add various functional chips, such as USB3.0 chips, hybrid chips, and NF200 chips of NVIDIA.

The Basic Input Output System (BIOS) is a set of programs that are fixed on a chip on a main board in a computer, and stores the most important basic Input and Output programs of the computer, system setting information, a self-test program after power-on and a system self-starting program, and has the main functions of providing the bottommost and most direct hardware setting and control for the computer, and using the BIOS setting program to eliminate system faults or diagnose system problems, and the conventional BIOS chip is made of ROM or Flash. A Trusted Platform Module (TPM) security chip refers to a security chip conforming to the TPM standard, which can effectively protect a personal computer and prevent an illegal user from accessing the security chip. In 10 months 1999, multiple IT macros jointly launch a Trusted Computing Platform Alliance (TCPA), initial joiners include Corbina, HP, IBM, Intel, Microsoft and the like, in 3 months 2003, the TCPA adds the addition of manufacturers in Nokia, Sony and the like, and changes the TCPA into a Trusted Computing Group (TCG), and the Trusted Computing Group hopes to establish Trusted computer related standards and specifications from two aspects of hardware and software of cross-Platform and operating environment, and provides TPM specifications. Similar to TPM, a security chip composed of a cryptographic algorithm and an engine developed autonomously at home is called Trusted Cryptography Module (TCM), and there are already related product suppliers such as association, mega-day technology, etc. whose functions are basically similar to those of foreign TPM products. At present, China enterprises such as the association, Huashi and the like are members of the TCG, and Wuhan university, Qinghua university and Beijing industry university are members of the TCG. The TPM compliant chip must first have the capability to generate cryptographic keys, and must also be able to perform high speed encryption and decryption of material and act as an auxiliary processor to protect the BIOS and operating system from modification. Nowadays, TPM security chips have wide application, and can realize the following applications by matching with special software: 1. and storing and managing the BIOS starting password and the hard disk password. Compared with the BIOS management password, the security of the TPM security chip is greatly improved. 2. The TPM security chip can perform a wide range of encryption. The TPM security chip can encrypt system login and application software login except for traditional startup encryption and hard disk encryption. 3. Any partition of the hard disk is encrypted. People can encrypt any hard disk partition on the notebook, and you can put some sensitive files into the partition to make the security.

Disclosure of Invention

In view of the above problem, the present invention provides a memory chip, comprising:

a silicon substrate;

a dielectric layer having a first region and a second region, the dielectric layer disposed on the silicon substrate;

the storage array is arranged on the dielectric layer;

the peripheral logic circuit is positioned in the first area and embedded in the dielectric layer;

and a plurality of functional modules are embedded in the dielectric layer in the second region.

In the memory chip, the peripheral logic circuit in the first region includes a voltage boost circuit, a decoding circuit, an induction circuit, a control circuit, and an IO circuit.

In the above memory chip, the functional module includes a south bridge and an IO device functional module thereof and/or a trusted platform module and/or a trusted cryptography module.

The memory chip is provided with a basic input/output system chip function.

In the above memory chip, the memory chip is a nonvolatile portion of a hybrid memory or a nonvolatile portion of a hybrid cache.

In the above memory chip, the memory chip is packaged in a package, and the package further includes a central processing unit and/or an off-chip last-level volatile cache chip.

In the above memory chip, the central processing unit and/or the last level of off-chip volatile cache chip are packaged in the package by using a multi-chip packaging technology.

In the above memory chip, the package is externally connected to a heat dissipation fan for reducing heat generated by the package.

In summary, the present invention provides a 3D novel nonvolatile memory chip, which fully utilizes the unused space of the silicon chip under the 3D memory array, integrates the functions of the south bridge and its related IO device function module and/or trusted platform module/trusted cryptography module (TPM/TCM) chip, and can also use a part of the 3D novel nonvolatile memory chip as the Basic Input Output System (BIOS) function, while the 3D novel nonvolatile memory chip can also be used as the nonvolatile part of the hybrid memory or the hybrid buffer. The 3D novel nonvolatile memory chip, the processor and the last-level volatile cache chip outside the chip are stored and packaged in a packaging body through a multi-chip packaging technology, so that the area and wiring of a mother board are greatly reduced, power consumption and cost are saved, meanwhile, the 3D novel nonvolatile memory and the processor are packaged in the same packaging body, the reading speed is greatly improved, and the overall performance of a computer can be improved.

Drawings

Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. The drawings are, however, to be regarded as illustrative and explanatory only and are not restrictive of the scope of the invention.

FIG. 1 is a schematic diagram of a conventional computer architecture;

FIG. 2 is a schematic diagram of a highly integrated computer architecture;

FIG. 3 is a schematic diagram of a 3D novel non-volatile memory chip;

FIG. 4 is a schematic diagram of a multi-chip package structure of a 3D novel nonvolatile memory chip according to the present invention;

FIG. 5 is a schematic diagram of a side structure of a 3D novel nonvolatile memory chip according to the present invention;

FIG. 6 is a schematic diagram of a top view of a 3D novel non-volatile memory chip according to the present invention;

FIG. 7 is a diagram of a conventional computer system motherboard configuration;

fig. 8 is a computer motherboard structure of a multi-chip package of the 3D novel non-volatile memory chip of the present invention.

Detailed Description

In order to make the technical solution and advantages of the present invention easier to understand, the following detailed description is made with reference to the accompanying drawings. It should be noted that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The 3D nonvolatile memory technology is a technology for changing a memory cell from a planar to a 3D vertical stacking, for example, a 3D phase change memory technology (PCM) which is gradually mature in the prior art, so that the memory density of each chip can be made very large, such as a 3D phase change memory being developed by Intel, and the memory capacity of each chip can reach 128Gb or 256Gb, and even higher in the near future, such as reaching Tb level. The random read-write speed of the 3D nonvolatile memory is high, and the 3D nonvolatile memory can even be used as the last level off-chip cache of a processor. Since the memory array of the 3D non-volatile memory is above the silicon, there is much space left under the silicon to fabricate the transistor logic. With the increasing demand for memory capacity, the memory array on the silicon chip is also larger and larger, and the corresponding logic circuit under the silicon chip is not increased much, so that a lot of area space is left, and how to effectively utilize the silicon chip space to achieve cost optimization is a problem that needs to be considered by manufacturers at present.

As shown in fig. 3, the present invention provides a 3D novel non-volatile memory chip, which includes a silicon substrate 1, a dielectric layer 2 and a memory array 3 from bottom to top in sequence, and the 3D novel non-volatile memory chip is packaged in a package with at least a central processing unit and/or an off-chip last-level volatile cache chip by a multi-chip package technology (MCP), and the structure of the chip is shown in fig. 4. The off-chip last level volatile cache chip serves as an off-chip cache of the processor and may be an embedded dynamic random access memory chip (eDRAM). The 3D novel nonvolatile memory chip is a nonvolatile memory chip manufactured by a 3D vertical stacking process, is not stacked by a 3D packaging technology, can be a 3D phase change memory chip (3D PCM) with gradually mature technology, and can also be other 3D novel nonvolatile memory chips. The method is characterized in that a lot of redundant silicon substrate space can be used for manufacturing other logic circuits under the 3D memory array, and the logic circuits do not influence the memory array. The multi-chip package is provided with a cooling fan, so that the heat generated by a processor and the last-level volatile cache chip outside the chip can be reduced, and the 3D nonvolatile memory chip can work in an acceptable temperature range, because the problem of reduced data retention capability of the 3D nonvolatile memory chip occurs at higher temperature.

The structural side view of the 3D novel nonvolatile memory chip is shown in FIG. 5, and a memory array is positioned on a silicon substrate 1 by adopting a 3D vertical stacking manufacturing process; the dielectric layer 2 is located on the silicon substrate 1, and in combination with the area of the dielectric layer 2 shown in fig. 3 being equal to the area of the memory array 3, the area of the dielectric layer 2 shown in fig. 5 is larger than the area of the memory array 3. The dielectric layer is used for preparing a logic circuit and consists of a first area 4 and a second area 5, and the top view is shown in fig. 6, wherein the first area 4 of the dielectric layer is a peripheral logic circuit of the 3D novel nonvolatile memory chip, such as a boosting circuit, a decoding circuit, a sensing circuit, a control circuit, an IO circuit and the like, and the circuit only occupies a small part of the whole dielectric layer 2, because the 3D memory array occupies a large part. The second region 5 of the dielectric layer is the inventive focus of the 3D nonvolatile memory of the present invention, and can be used to implement the functions of the south bridge and its IO device functional modules (the south bridge and its IO device functional modules in this application are configured as one functional module), and/or TPM/TCM security functions, part or all of the entire 3D novel non-volatile memory may also be used to implement the non-volatile portion of the hybrid memory or the hybrid buffer, and a part of the capacity of the entire 3D novel non-volatile memory chip may also be used to implement the function of acting as an input output system (BIOS) chip, which is not the real shape shown in fig. 6, and only for the purpose of illustrating the present invention, the sum of the areas of the second region 5 of the dielectric layer and the peripheral circuit (the first region 4 of the dielectric layer) of the 3D novel non-volatile memory chip is the area of the entire silicon substrate 1 under the 3D memory array. The second region 5 of the dielectric layer of the present invention comprises at least: a conventional south bridge and its IO device function modules, and/or a Trusted Platform Module (TPM) or a Trusted Cryptography Module (TCM). The Basic Input Output System (BIOS) can also be replaced by part of the storage space of the 3D novel nonvolatile memory. The novel 3D nonvolatile memory chip can integrate the south bridge and the IO device functional modules thereof, because the south bridge and the IO device functional modules thereof are mainly responsible for processing communication between IO buses, and the processing speed is lower than that of a north bridge or a processor chip, the process nodes of the novel 3D nonvolatile memory chip are not advanced too much, and the novel 3D nonvolatile memory chip can conform to the process technology of the conventional novel 3D nonvolatile memory chip. The 3D novel nonvolatile memory chip not only integrates the functions of a traditional south bridge and related IO equipment thereof, but also can integrate the TPM/TCM security function, can realize the functions of a traditional BIOS chip on one part of the whole 3D nonvolatile memory chip, and can be used as a nonvolatile part of a hybrid memory or a hybrid buffer. Therefore, the integration level of the 3D novel nonvolatile memory chip is greatly increased, the area utilization rate of the silicon substrate is maximized, the wiring of a mother board is reduced, and the power consumption and the cost are saved.

The following is a further description of an embodiment.

In a conventional computer system, a processor, a south bridge, an IO device function module thereof, and an off-chip last-level cache chip form a chip in a multi-chip package manner, and only one main body package chip is provided on a motherboard, which is shown in fig. 7. An important component on the motherboard is a memory (DRAM), which, if a non-volatile hybrid memory, also contains a non-volatile memory to store data in the volatile DRAM; besides, the motherboard also comprises a BIOS chip, a TPM/TCM chip, a disk or a solid state disk and other peripheral devices. The 3D novel nonvolatile memory chip has a simplified structure of the whole computer system motherboard as shown in FIG. 8, and the whole motherboard is also provided with only one main chip, and the multi-chip package comprises a central processing unit chip, an off-chip last-level cache and the 3D novel nonvolatile memory chip. The 3D novel nonvolatile memory chip integrates the functions of a traditional south bridge chip, simultaneously comprises the functions of a TPM/TCM chip and a BIOS chip, and can also be used as a nonvolatile part in a hybrid memory. Therefore, the whole motherboard structure is greatly simplified, and only comprises a volatile part (traditional DRAM) in the hybrid memory and peripherals such as a magnetic disk or a solid state disk. Compared with the traditional computer structure, the computer structure based on the 3D novel nonvolatile memory chip structure greatly saves the area of a motherboard and wiring, thereby being beneficial to reducing power consumption and cost.

The invention provides a 3D novel nonvolatile memory chip, which fully utilizes the unused space of a silicon wafer below a 3D memory array, simultaneously integrates the functions of a south bridge and an IO (input/output) device function module thereof and/or a trusted platform module/trusted cryptography module (TPM/TCM) chip, and simultaneously can also take one part of the 3D novel nonvolatile memory chip as the function of a basic input/output system (BIOS), and the 3D novel nonvolatile memory chip can also be taken as the nonvolatile part of a mixed memory or a mixed buffer. The 3D novel nonvolatile memory chip, the processor and the last-level volatile cache chip outside the chip are stored and packaged in a packaging body through a multi-chip packaging technology, so that the area and wiring of a mother board are greatly reduced, power consumption and cost are saved, meanwhile, the 3D novel nonvolatile memory and the processor are packaged in the same packaging body, the reading speed is greatly improved, and the overall performance of a computer can be improved.

While the specification concludes with claims defining exemplary embodiments of particular structures for practicing the invention, it is believed that other modifications will be made in the spirit of the invention. While the above invention sets forth presently preferred embodiments, these are not intended as limitations.

Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. Therefore, the appended claims should be construed to cover all such variations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.

Claims

1. A memory chip, comprising:

a silicon substrate;

the storage array is arranged on the dielectric layer;

the peripheral logic circuit is positioned in the first area and embedded in the dielectric layer; the peripheral logic circuit comprises a booster circuit, a decoding circuit, an induction circuit, a control circuit and an IO circuit;

the medium layer in the second area is also embedded with a south bridge and an IO device function module and/or a trusted platform module and/or a trusted password module thereof;

the memory chip is packaged in a package body, the package body also comprises a central processing unit and/or an off-chip last-level volatile cache chip, and the package is carried out by adopting a multi-chip packaging technology;

the contact area of the dielectric layer and the storage array is not larger than the area of the upper surface of the silicon substrate;

the memory chip is configured to have basic input output system functionality and is a non-volatile portion of a hybrid memory or a non-volatile portion of a hybrid cache.