CN104853170A - Integrated circuit chip for receiver collecting signals from satellites - Google Patents

Integrated circuit chip for receiver collecting signals from satellites Download PDF

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Publication number
CN104853170A
CN104853170A CN201510020742.5A CN201510020742A CN104853170A CN 104853170 A CN104853170 A CN 104853170A CN 201510020742 A CN201510020742 A CN 201510020742A CN 104853170 A CN104853170 A CN 104853170A
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CN
China
Prior art keywords
differential
amplifier
ended
switching circuit
differential amplifier
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Granted
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CN201510020742.5A
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Chinese (zh)
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CN104853170B (en
Inventor
甘孟平
吴偲铭
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Rafael microelectronics Inc
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Rafael microelectronics Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H04B1/12—Neutralising, balancing, or compensation arrangements
    • H04B1/123—Neutralising, balancing, or compensation arrangements using adaptive balancing or compensation means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0277—Selecting one or more amplifiers from a plurality of amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/14—Relay systems
    • H04B7/15—Active relay systems
    • H04B7/185—Space-based or airborne stations; Stations for satellite systems
    • H04B7/1851—Systems using a satellite or space-based relay
    • H04B7/18513—Transmission in a satellite or space-based system
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/405—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising more than three power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/408—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising three power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/411—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising two power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/414—A switch being coupled in the output circuit of an amplifier to switch the output on/off
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/421—Multiple switches coupled in the output circuit of an amplifier are controlled by a circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21142—Output signals of a plurality of power amplifiers are parallel combined to a common output
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21175—An output signal of a power amplifier being on/off switched
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45051—Two or more differential amplifiers cascade coupled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H03F2203/7221—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by a switch at the output of the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H03F2203/7236—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Astronomy & Astrophysics (AREA)
  • Aviation & Aerospace Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Amplifiers (AREA)

Abstract

An integrated circuit chip includes a first single-ended-to-differential amplifier configured to generate a differential output associated with an input of said first single-ended-to-differential amplifier; a second single-ended-to-differential amplifier arranged in parallel with said first single-ended-to-differential amplifier; a first set of switch circuits arranged downstream of said first single-ended-to-differential amplifier; a second set of switch circuits arranged downstream of said second single-ended-to-differential amplifier; and a first differential-to-single-ended amplifier arranged downstream of a first one of said switch circuits in said first set and downstream of a first one of said switch circuits in said second set.

Description

A kind of integrated circuit (IC) chip of the receiver for collecting satellite-signal
Technical field
The present invention relates to a kind of integrated circuit (IC) chip for satellite receiver, particularly about a kind of include a switch matrix, multiple arranged in parallel and be positioned at the signal upstream extremity of this switch matrix single-ended to differential amplifier and multiple arranged in parallel and be positioned at the differential integrated circuit (IC) chip to single-ended amplifier of the signal downstream of this switch matrix.
Background technology
Because diversified content, satellite television becomes more and more popular.A satellite television system generally includes antenna array and the satellite receiver that is used for collecting satellite-signal.This satellite receiver comprises: (1) multiple amplifier, and it can be used to amplify the signal (hereinafter referred to as " collection signal ") collected; (2) multiple band pass filter (band-pass filter is called for short BPF), its collection signal that can be used to allow frequency in a certain frequency range passes through, and the collection signal of frequency of fadings outside this frequency range; And (3) multiple mixer (mixer), it can be used to the collection signal collection signal of radio frequency (radio frequency) being converted to intermediate frequency (intermediate frequency).Therefore, collect signal and can be processed into the best amplifying signal of frequency at fundamental frequency (base frequency) or intermediate frequency, so demodulated in box (set top box) on machine.
Summary of the invention
The invention provides a kind of integrated circuit (IC) chip for signal receiver, wherein signal receiver can be used to collect the signal from the one or more satellites within the scope of signal receiver.
This integrated circuit (IC) chip can comprise: one first single-ended to differential amplifier (single-ended-to-differential amplifier), and it can in order to produce the differential output (differential output) relevant with this first single-ended input to differential amplifier (input); One second single-endedly first single-endedly to be arranged in parallel to differential amplifier to differential amplifier and this, this second single-ended to differential amplifier in order to produce the differential output (differential output) relevant with this second single-ended input to differential amplifier (input); One first group of switching circuit is positioned at this first single-ended signal downstream to differential amplifier, and this one of them first switching circuit of first group of switching circuit comprises a differential input relevant with this first single-ended differential output to differential amplifier; One second group of switching circuit is positioned at this second single-ended signal downstream to differential amplifier, and this one of them second switch circuit of second group of switching circuit comprises a differential input relevant with this second single-ended differential output to differential amplifier; And one first is differentially positioned at the signal downstream of this first switching circuit to single-ended amplifier and is positioned at the signal downstream of this second switch circuit, wherein this first differentially comprises a differential input relevant with a differential output of this first switching circuit to single-ended amplifier.
In addition, this integrated circuit (IC) chip more can comprise one second and is differentially positioned at the signal downstream of this one of them the 3rd switching circuit of first group of switching circuit to single-ended amplifier and is positioned at the signal downstream of this one of them the 4th switching circuit of second group of switching circuit, wherein this second differential to single-ended amplifier comprise with a differential output of the 3rd switching circuit about or a differential input relevant with a differential output of the 4th switching circuit.
In addition, this integrated circuit (IC) chip more can comprise one first group and is differentially positioned at this first single-ended signal downstream to differential amplifier to differential amplifier and is positioned at the signal upstream extremity of this first group of switching circuit, wherein this first group differential to differential amplifier, one of them first differentially comprises a differential input relevant with this first single-ended this differential output to differential amplifier to differential amplifier, and a differential output relevant with this differential input of this first switching circuit, this integrated circuit (IC) chip more can comprise one second group and differentially be positioned to differential amplifier that this is second single-ended to the signal downstream of differential amplifier and the signal upstream extremity of this second group of switching circuit, wherein this second group differential to differential amplifier, one of them second differentially comprises a differential input relevant with this second single-ended this differential output to differential amplifier to differential amplifier, and a differential output relevant with this differential input of this second switch circuit.
In addition, this first single-ended this differential output to differential amplifier has in fact 180 degree of phase differences, this differential output of this first switching circuit has in fact 180 degree of phase differences, this differential input of this first switching circuit has in fact 180 degree of phase differences, and this first differential this differential input to single-ended amplifier has in fact 180 degree of phase differences.
In addition, this integrated circuit (IC) chip is arranged in a signal receiver, in order to process the signal transmitted from one or more satellite.
Accompanying drawing explanation
One integrated circuit chip structure calcspar of open the first application of the present invention of Fig. 1.
The pin configuration figure of this integrated circuit (IC) chip of open the first application of the present invention of Fig. 2.
One integrated circuit chip structure calcspar of the open the second application of the present invention of Fig. 3.
A kind of Electronic Packaging module generalized section of the open integrated circuit (IC) chip of the present invention of Fig. 4.
Schematic block diagram of the first configuration of the first integrated circuit (IC) chip described in application of the open the present invention of Fig. 5.
The schematic block diagram of the second configuration of the first integrated circuit (IC) chip described in application of the open the present invention of Fig. 6.
Schematic block diagram of the third configuration of the first integrated circuit (IC) chip described in application of the open the present invention of Fig. 7.
The schematic block diagram of the 4th kind of configuration of the first integrated circuit (IC) chip described in application of the open the present invention of Fig. 8.
The schematic block diagram of the 4th kind of configuration of the first integrated circuit (IC) chip described in application of the open the present invention of Fig. 9.
Embodiment
When following description is read together with alterations, can understand configuration of the present invention more fully, the character of these alterations should be considered as illustrative and nonrestrictive.These are graphic may not draw in proportion, but emphasizes principle of the present invention.
Graphic announcement illustrative application circuit of the present invention.It does not set forth all application circuits.In addition or can substitute and use other application circuit.For saving space or more effectively illustrating, apparent or unnecessary details can be omitted.On the contrary, some application circuits can be implemented and not disclose all details.When same numbers occurs in different drawings, it refers to identical or similar assembly or step.
The circuit structure calcspar of open the first the application integrated circuit chip 10 of the present invention of Fig. 1.Integrated circuit (IC) chip 10 can be used in a signal receiver, such as be used in a lnb (low-noise block, LNB) in, the data flow that one or more satellite of range of receiving being positioned at signal receiver in order to process transmits or signal.
As shown in Figure 1, this integrated circuit (IC) chip 10 can comprise (1) four be arranged in parallel single-ended to differential amplifier 11, (2) first groups four are differential to differential amplifier 16a, that is four of top in FIG, for be arrangeding in parallel, and be positioned at the first single-ended signal downstream to differential amplifier 11 of Fig. 1 top, (3) second groups four differential to differential amplifier 16b, that is secondary high four in FIG, for be arrangeding in parallel, and is positioned at the second secondary high single-ended signal downstream to differential amplifier 11 of Fig. 1, (4) the 3rd groups four differential to differential amplifier 16c, that is secondary low four in FIG, for be arrangeding in parallel, and is positioned at the 3rd secondary low single-ended signal downstream to differential amplifier 11 of Fig. 1, (5) the 4th groups four differential to differential amplifier 16d, that is minimum four of Fig. 1, for be arrangeding in parallel, and be positioned at the 4th minimum single-ended signal downstream to differential amplifier 11 of Fig. 1, (6) one switch matrix comprise first group of four switching circuit 12a, second group of four switching circuit 12b, 3rd group of four switching circuit 12c and the 4th groups of four switching circuit 12d, wherein first group of four switching circuit 12a is set in parallel in these first group four the differential signal downstream to differential amplifier 16a, namely be positioned at four switching circuit 12a of Fig. 1 top, second group of four switching circuit 12b is set in parallel in these second group four the differential signal downstream to differential amplifier 16b, namely be positioned at Fig. 1 high four switching circuit 12b, 3rd group of four switching circuit 12c are set in parallel in the 3rd group four the differential signal downstream to differential amplifier 16c, namely be positioned at Fig. 1 low four switching circuit 12c, 4th group of four switching circuit 12d are set in parallel in the 4th group four the differential signal downstream to differential amplifier 16d, namely be positioned at four switching circuit 12d that Fig. 1 is minimum, (7) four differential signal downstream being set in parallel in this switch matrix to single-ended amplifier 13, these four differential the first differential signal downstream being arranged in the switching circuit of each group switching circuit 12a-12d top to single-ended amplifier to top in single-ended amplifier 13, these four differential to single-ended amplifier 13 time high second differential signal downstream being arranged in the high switching circuit of each group switching circuit 12a-12d time to single-ended amplifier, these four differential to single-ended amplifier 13 time low 3rd differential signal downstream being arranged in the low switching circuit of each group switching circuit 12a-12d time to single-ended amplifier, these four differential the 4th differential signal downstream being arranged in the minimum switching circuit of each group switching circuit 12a-to single-ended amplifier minimum to single-ended amplifier 13.
As shown in Figure 1, each this single-ended input to differential amplifier 11 can be exaggerated as this single-ended differential output to differential amplifier 11, this single-ended to differential amplifier 11 be such as differential amplifier, wherein those the single-ended inputs to differential amplifier 11 of each those single-ended these differential outputs and each to differential amplifier 11 about and there is in fact the phase difference of 180 degree.Those first group to the 4th group differential to each in differential amplifier 16a-16d this differential to differential amplifier have a differential input be respectively exaggerated as a respective differential output, wherein each those differential these differential output to differential amplifier has in fact the phase difference of 180 degree, and each those differential these differential input to differential amplifier has in fact the phase difference of 180 degree, and to be differentially associated with this respective differential input respectively to those differential these differential outputs to differential amplifier of each in differential amplifier 16a-16d at those first group to the 4th group.Each those differential input to single-ended amplifier 13 can be exaggerated and export as it, each those differential to single-ended amplifier 13 be such as differential amplifier, wherein each those differential these output to single-ended amplifier 13 is relevant with its differential input, and this differential input has in fact the phase difference of 180 degree.
As shown in Figure 1, this switch matrix of the present invention can be a differential passive switch matrix, this switch matrix comprises first group of switching circuit to the 4th group of switching circuit 12a-12d, each group switching circuit 12a, 12b, 12c and 12d has four switching circuits respectively, it is differential to differential amplifier that its differential input couples those four of those first group to the 4th group differential one of them group to differential amplifier 16a-16d respectively, and its differential output couple respectively those four differential to single-ended amplifier 13.By these first group of four switching circuit 12a can control these first group four differential to couple respectively to differential amplifier 16a or not to be coupled to those four differential to single-ended amplifier 13.By these second group of four switching circuit 12b can control these second group four differential to couple respectively to differential amplifier 16b or not to be coupled to those four differential to single-ended amplifier 13.By the 3rd group of four switching circuit 12c can control the 3rd group four differential to couple respectively to differential amplifier 16c or not to be coupled to those four differential to single-ended amplifier 13.By the 4th group of four switching circuit 12d can control the 4th group four differential to couple respectively to differential amplifier 16d or not to be coupled to those four differential to single-ended amplifier 13.
As shown in Figure 1, when a certain switching circuit of those switching circuits 12a-12d be switched make those differential to differential amplifier 16a-16d a certain differential to differential amplifier be coupled to those differential to single-ended amplifier 13 one of them time, this is a certain differentially can switch to power opening state to differential amplifier, and wherein this differential input of this certain switching circuit couples this certain differential this differential output to differential amplifier.When this certain switching circuit of those switching circuits 12a-12d be switched make those differential these to differential amplifier 16a-16d a certain differential to differential amplifier be not coupled to those differential to single-ended amplifier 13 one of them time, this is a certain differentially can switch to power down state to differential amplifier.Such as, when this switching circuit 12a of top be switched make this of top differential to differential amplifier 16a be coupled to this of top differential to single-ended amplifier 13 time, this of top is differential will switch to power opening state to differential amplifier 16a.Anti-, when this switching circuit 12a of top be switched make this of top differential to differential amplifier 16a be not coupled to this of top differential to single-ended amplifier 13 time, this of top is differential will switch to power down state to differential amplifier 16a.
As shown in Figure 1, single-ended to differential amplifier 11 wherein this, first single-ended be coupled to four to differential amplifier this is differential first differential to single-ended amplifier and this is second differential to single-ended amplifier to single-ended amplifier 13 wherein this for changeable four of such as this switch matrix, and switching four, single-ended to differential amplifier 11 wherein this, second single-ended be coupled to four to differential amplifier this is differential to single-ended amplifier 13 wherein the 3rd differential to single-ended amplifier and the 4th differential to single-ended amplifier.Therefore, four this differentially first to be differentially single-endedly associated to differential amplifier 11 this first single-ended input to differential amplifier wherein with four to single-ended amplifier and this second differential output to single-ended amplifier to single-ended amplifier 13 wherein this; Four this is differential to single-ended amplifier 13 the 3rd to be differentially single-endedly associated to differential amplifier 11 this second single-ended input to differential amplifier wherein with four to single-ended amplifier and the 4th differential output to single-ended amplifier wherein.Four this differentially first differentially second differentially there are two respective outputs to single-ended amplifier to single-ended amplifier and this to single-ended amplifier 13 wherein this, this two output function is under one first centre frequency and have identical one first frequency range (band width), is same as four these single-ended frequency of operation to differential amplifier 11 this first single-ended input to differential amplifier wherein and frequency ranges, four this differential to single-ended amplifier 13 wherein the 3rd differentially differentially there are two respective outputs to single-ended amplifier to single-ended amplifier and the 4th, this two output function is under one second centre frequency and have one second identical frequency range, be same as four these single-ended frequency of operation to differential amplifier 11 this second single-ended input to differential amplifier wherein and frequency ranges, wherein this first frequency range can have identical frequency range with this second frequency range, and this first centre frequency can be different from this second centre frequency, and four this single-endedly first single-endedly there is identical polarization (polarization) to differential amplifier and this second single-ended input to differential amplifier to differential amplifier 11 wherein this, it is such as perpendicular polarization, horizontal polarization, right-hand polarization or left-handed polarization.In addition, this first centre frequency also can be identical with this second centre frequency, and four this single-endedly first single-endedly can have different polarization (polarization) to differential amplifier and this second single-ended input to differential amplifier to differential amplifier 11 wherein this, be such as perpendicular polarization and horizontal polarization respectively or be right-hand polarization and left-handed polarization respectively.In addition, this first centre frequency also can be different from this second centre frequency, and these four this single-endedly first single-endedly can have different polarization (polarization) to differential amplifier and this second single-ended input to differential amplifier to differential amplifier 11 wherein this, be such as perpendicular polarization and horizontal polarization respectively or be right-hand polarization and left-handed polarization respectively.
As shown in Figure 1, in another example, this switch matrix changeable four this single-ended to differential amplifier 11 wherein this, first single-ended be coupled to four to differential amplifier this is differential first differential to single-ended amplifier to single-ended amplifier 13 wherein this, switch four this single-ended to differential amplifier 11 wherein this, second single-ended be coupled to four to differential amplifier this is differential second differential to single-ended amplifier to single-ended amplifier 13 wherein this, switch four this single-ended to differential amplifier 11 wherein the 3rd single-ended to differential amplifier be coupled to four this differential to single-ended amplifier 13 wherein the 3rd differential to single-ended amplifier and switch four this single-ended to differential amplifier 11 wherein the 4th single-ended be coupled to four to differential amplifier this is differential to single-ended amplifier 13 wherein the 4th differential to single-ended amplifier.Therefore, those are differentially associated to single-ended amplifier 13 this first differential output to single-ended amplifier wherein and those are single-ended to differential amplifier 11 this first single-ended input to differential amplifier wherein; Those are differential is associated to single-ended amplifier 13 this second differential output to single-ended amplifier wherein and those are single-ended to differential amplifier 11 this second single-ended input to differential amplifier wherein; Those are differential is associated to single-ended amplifier 13 the 3rd differential output to single-ended amplifier wherein and those are single-ended to differential amplifier 11 the 3rd single-ended input to differential amplifier wherein; Those are differential is associated to single-ended amplifier 13 the 4th differential output to single-ended amplifier wherein and those are single-ended to differential amplifier 11 the 4th single-ended input to differential amplifier wherein.Four this differentially first differentially can have an output to single-ended amplifier to single-ended amplifier 13 wherein this, operate in this first centre frequency and there is this first frequency range, being same as four these single-ended frequency of operation to differential amplifier 11 this first single-ended input to differential amplifier wherein and frequency ranges; Four this differentially second differentially can have an output to single-ended amplifier to single-ended amplifier 13 wherein this, operate in this second centre frequency and there is this second frequency range, being same as four these single-ended frequency of operation to differential amplifier 11 this second single-ended input to differential amplifier wherein and frequency ranges; Four this differential to single-ended amplifier 13 wherein the 3rd differentially can have an output to single-ended amplifier, operate in the 3rd centre frequency and there is the 3rd frequency range, being same as four these single-ended frequency of operation to differential amplifier 11 the 3rd single-ended input to differential amplifier wherein and frequency ranges; Four this differential to single-ended amplifier 13 wherein the 4th differentially can have an output to single-ended amplifier, operate the 4th centre frequency and there is the 4th frequency range, be same as four these single-ended frequency of operation to differential amplifier 11 the 4th single-ended input to differential amplifier wherein and frequency ranges, wherein this first frequency range, this second frequency range, the 3rd frequency range and the 4th frequency range can have identical frequency range.When considering polarization, four this single-ended to differential amplifier 11 wherein this first this single-ended to differential amplifier and the 3rd this be single-endedly input as perpendicular polarization to differential amplifier, and four this single-ended to differential amplifier 11 wherein this second this single-ended to differential amplifier and the 4th this be single-endedly input as horizontal polarization to differential amplifier.Or, four this single-ended to differential amplifier 11 wherein this first this single-ended to differential amplifier and the 3rd this be single-endedly input as right-hand polarization to differential amplifier, and four this single-ended to differential amplifier 11 wherein this, second this is single-ended to differential amplifier and the 4th this single-ended left-handed polarization that is input as to differential amplifier, it can be applied to following Several combinations.This first centre frequency can be identical with this second centre frequency, and four this single-endedly first single-endedly second single-endedly to the respective input of differential amplifier, there is different polarization to differential amplifier and this to differential amplifier 11 wherein this, be such as perpendicular polarization and horizontal polarization respectively or be right-hand polarization and left-handed polarization respectively; This first centre frequency can be not identical with the 3rd centre frequency, and four this single-endedly first single-endedly to differential amplifier and the 3rd single-ended input respective to differential amplifier 11, there is identical polarization to differential amplifier 11 wherein this, be such as perpendicular polarization, horizontal polarization, right-hand polarization or left-handed polarization; This first centre frequency can be not identical with the 4th centre frequency, and four this single-ended to differential amplifier 11 wherein this first this single-endedly single-endedly to the respective input of differential amplifier, there is different polarization to differential amplifier and the 4th, be such as perpendicular polarization and horizontal polarization respectively or be right-hand polarization and left-handed polarization respectively.
As shown in Figure 1, four each to single-ended amplifier 13 differential have respective differential input and are exaggerated as each Self-differential to the output of single-ended amplifier 13, and each differentially has an optimal 1dB compression point (P1dB) to single-ended amplifier 13, prevent when an excessive electric current by four differential to single-ended amplifier 13 one of them time, cause the electronic equipment of its signal downstream to be burnt.
Therefore, this integrated circuit (IC) chip 10 can provide this switching circuit 12a-12d, in order to switch the differential wave of tool 180 degree of phase differences, makes the separating property between the crosstalk between signal (crosstalk) reduction and signal better.In addition, this differential signal upstream extremity that can be positioned at this switching circuit 12a-12d to differential amplifier 16a-16d, in order to amplify the input signal of this switching circuit 12a-12d, uses and obtains preferably gain balance.
The pin configuration figure of this integrated circuit (IC) chip 10 of open the first application of the present invention of Fig. 2.As shown in Figure 2, this integrated circuit (IC) chip 10 comprises four pins IN1, IN2, IN3 and IN4, be coupled to those single-ended four inputs to differential amplifier 11 respectively, integrated circuit (IC) chip 10 separately comprises four pins Out1, Out2, Out3 and Out4, be coupled to those differential four outputs to single-ended amplifier 13 respectively, integrated circuit (IC) chip 10 separately comprises a circuit module 12, has the differential to differential amplifier 16a-16d of this first group to the 4th group switching circuit 12a-12d described in above-described embodiment and this first group and the 4th group.
As shown in Figure 2, this integrated circuit (IC) chip 10 more comprises one voltage-frequency modulation detector (voltage and tone detector) 14 and a decoder (decoder) 15, voltage-frequency modulation detector 14 has four pins VT1, VT2, VT3 and VT4 that four inputs are coupled to integrated circuit (IC) chip 10 respectively, and decoder 15 is positioned at the signal upstream extremity of the signal downstream of this voltage-frequency modulation detector 14 and the switch matrix of circuit module 12.Voltage-frequency modulation detector 14 can detect four pins VT1, VT2, VT3 and VT4 and be in a high logic level (high logic level) or a low logic level (low logic level), its testing result respectively as the output of this voltage-frequency modulation detector 14 correspondence, and is coupled to the corresponding input of this decoder 15.Inputted signal can be carried out decoding by decoder 15, and with the switch matrix of decode results control circuit module 12, and then control four this single-ended to differential amplifier 11 one of them be coupled to four this differential to single-ended amplifier 13 one of them, simultaneously also controlling those differential is be in electric power starting or closed condition to differential amplifier 16a-16d.
As shown in Figure 2, integrated circuit (IC) chip 10 more can comprise the ground contact that plural pin GND is coupled to above-mentioned amplifier 11,13 and 16a-16d, switching circuit 12a-12d, voltage-frequency modulation detector 14 and decoder 15, or be coupled to a ground connection reference of this integrated circuit (IC) chip 10, these pins GND can provide an earthed voltage to above-mentioned amplifier 11,13 and 16a-16d, switching circuit 12a-12d, voltage-frequency modulation detector 14 and decoder 15.Integrated circuit (IC) chip 10 more can comprise pin VDD5V and export from pin LDO_O in order to input 5V power supply and to convert 3.7V voltage to, the 3.7V voltage that pin LDO_O exports by being provided directly to plural pin VIN and then the power supply contact being coupled to above-mentioned amplifier 11,13 and 16a-16d, switching circuit 12a-12d, voltage-frequency modulation detector 14 and decoder 15, in order to supply amplifier 11,13 and 16a-16d, switching circuit 12a-12d, voltage-frequency modulation detector 14 and decoder 15 power supply.Integrated circuit (IC) chip 10 more can comprise pin AVDDRX and hold electrical ground (internal alternate-current (AC) ground) as an internal communication.Integrated circuit (IC) chip 10 more can comprise pin VHM and ABSEL, and these two pins will be coupled to above-mentioned decoder 15, in order to change the switch situation to switching circuit 12a-12d corresponding to logic level.
Fig. 3 discloses the calcspar of semiconductor chip of the second of the present invention application, and wherein the assembly of label identical with Fig. 1 has identical function in figure 3, and can consult Fig. 1 about the relevant of this assembly and describe.As shown in Figure 3, integrated circuit (IC) chip 10 can comprise (1) four be arranged in parallel single-ended to differential amplifier 11, (2) first groups two are differential to differential amplifier 16a, that is two of top in figure 3, for be arrangeding in parallel, and be positioned at the first single-ended signal downstream to differential amplifier 11 of Fig. 3 top, (3) second groups two differential to differential amplifier 16b, that is secondary high two in figure 3, for be arrangeding in parallel, and is positioned at the second secondary high single-ended signal downstream to differential amplifier 11 of Fig. 3, (4) the 3rd groups two differential to differential amplifier 16c, that is secondary low two in figure 3, for be arrangeding in parallel, and is positioned at the 3rd secondary low single-ended signal downstream to differential amplifier 11 of Fig. 3, (5) the 4th groups two differential to differential amplifier 16d, that is minimum two of Fig. 3, for be arrangeding in parallel, and be positioned at the 4th minimum single-ended signal downstream to differential amplifier 11 of Fig. 3, (6) one switch matrix comprise first group of two switching circuit 12a, second group of two switching circuit 12b, 3rd group of two switching circuit 12c and the 4th groups of two switching circuit 12d, wherein first group of two switching circuit 12a is set in parallel in these first group two the differential signal downstream to differential amplifier 16a, namely be positioned at two switching circuit 12a of Fig. 3 top, second group of two switching circuit 12b is set in parallel in these second group two the differential signal downstream to differential amplifier 16b, namely be positioned at Fig. 3 high two switching circuit 12b, 3rd group of two switching circuit 12c are set in parallel in the 3rd group two the differential signal downstream to differential amplifier 16c, namely be positioned at Fig. 3 low two switching circuit 12c, 4th group of two switching circuit 12d are set in parallel in the 4th group two the differential signal downstream to differential amplifier 16d, namely be positioned at two switching circuit 12d that Fig. 3 is minimum, (7) two differential signal downstream being set in parallel in this switch matrix to single-ended amplifier 13, these two differential the first differential signal downstream being arranged in the switching circuit on each group switching circuit 12a-12d top to single-ended amplifier to top in single-ended amplifier 13, these two differential the second differential signal downstream being arranged in the switching circuit of each group switching circuit 12a-12d bottom to single-ended amplifier 13 to bottom in single-ended amplifier 13.
The Entity Architecture of integrated circuit (IC) chip of the present invention
As shown in Figure 1 to Figure 3, this integrated circuit (IC) chip 10 can comprise semiconductor substrate, form/have a plurality of driving component, plural passive component and complex conduction circuit on a semiconductor substrate, a wherein semiconductor substrate such as silicon substrate, driving component is such as transistor (transistors), passive component is resistance, electric capacity and/or inductance such as, and conducting wire that electro-coppering (damascene electroplated cupper) processing procedure formed and/or the conducting wire that sputtering aluminum processing procedure is formed such as are inlayed in conducting wire.
As shown in Figure 1 to Figure 3, amplifier 11 in the first application and the second application, 13 and 16a-16d, switching circuit 12a-12d, voltage-frequency modulation detector 14 and decoder 15 are all by these driving components, passive component and conducting wire form and are formed on semiconductor substrate, and it is single-ended to the differential connecting line between differential amplifier 16a-16d corresponding to differential amplifier 11 and difference at each, each differential connecting line between the switching circuit 12a-12d corresponding to differential amplifier 16a-16d and difference, each differential to single-ended amplifier 13 and respectively corresponding to switching circuit 12a-12d between connecting line, connecting line between decoder 15 and switching circuit 12a-12d, connecting line between decoder 15 and voltage-frequency modulation detector 14 can be formed by those conducting wires.
The encapsulating structure of integrated circuit (IC) chip of the present invention
The generalized section of open integrated circuit (IC) chip one encapsulating structure of the present invention of Fig. 4, as shown in Figure 4, an electron package structure 40 can comprise (1) one lead frame (lead frame) 41; (2) one integrated circuit (IC) chip 42 are positioned on lead frame 41; (3) plural pound line 43 is electrically connected the metallic pad 44 of integrated circuit (IC) chip 42 respectively in routing mode, and the metallic pad (or pin) 45 on the border and lead frame 41 of crossing over integrated circuit (IC) chip 42 is connected; (4) one Encapsulation Moulds (mold) 46 are formed in coated integrated circuit (IC) chip 42 and pound line 43 on lead frame 41.
As shown in Figures 1 to 4, integrated circuit (IC) chip 42 can be the integrated circuit (IC) chip 10 described in above-described embodiment.Some metallic pad 44 of integrated circuit (IC) chip 42 can be connected to the single-ended input to differential amplifier respectively, and other metallic pad 44 of integrated circuit (IC) chip 42 can be connected to the differential output to single-ended amplifier respectively; Further, other these metallic pad 44 also can have the electric function of above-mentioned pin IN1-IN4, VHM, ABSEL, VIN, VT1-VT4, LDO_O, VDD5V, AVDDRX, Out1-Out4 and GND respectively.
The first configuration of the first application integrated circuit chip of the present invention
Schematic block diagram of the first configuration of the first integrated circuit (IC) chip 10 described in application of the open the present invention of Fig. 5, wherein in Fig. 1, Fig. 2 and Fig. 5, the assembly of identical label has identical function, and can consult in Fig. 1 and Fig. 2 about the relevant of this assembly describes.
The first configuration as shown in Figure 5, the signal that in the range of receiving that one signal receiver 50 can come from signal receiver 50 in order to process, a satellite transmits, wherein this signal can be perpendicular polarization and horizontal polarization signals or right-hand polarization and left-hand polarized signals, this signal can by be positioned at a dish-like reflector (reflector dish) focus a feed horn antenna (antenna feed horn) collected by, wherein this signal receiver 50 is such as a lnb (low-noise block, LNB).Signal receiver 50 can comprise (1) this integrated circuit (IC) chip 10, (2) four amplifiers 51 are set in parallel in the signal upstream extremity of the corresponding amplifier 11 of four of this integrated circuit (IC) chip 10 respectively, (3) four mixers (mixer) 52 are set in parallel in the signal upstream extremity of four amplifiers 51, (4) two local oscillator (local oscillators, LO) 53 two in four mixers 52 are coupled to respectively, the first local oscillator being wherein arranged in the local oscillator 53 above Fig. 5 is coupled to first mixer and second mixer of the mixer 52 be arranged in above Fig. 5, and the second local oscillator being arranged in the local oscillator 53 below Fig. 5 is then coupled to the 3rd mixer and the 4th mixer of the mixer 52 be arranged in below Fig. 5, (5) four band pass filter (band-pass filter, BPF) the 54 signal upstream extremities being set in parallel in four corresponding mixers 52, the output of the first band pass filter wherein in these four band pass filters 54, the second band pass filter, the 3rd band pass filter and the 4th band pass filter (from high to low) is coupled to the input of this first mixer of corresponding mixer 23, this second mixer, the 3rd mixer and the 4th mixer respectively, (6) two channel-splitting filters (splitter) 55 are set in parallel in the signal upstream extremity of band pass filter 54, the first channel-splitting filter being wherein arranged in the channel-splitting filter 55 above Fig. 5 has two outputs and is coupled to band pass filter 54 this first band pass filter wherein and the input of this second band pass filter respectively, and the first channel-splitting filter being arranged in the channel-splitting filter 55 below Fig. 5 has two outputs is coupled to band pass filter 54 the 3rd band pass filter wherein and the input of the 4th band pass filter respectively, wherein each channel-splitting filter 55 such as power splitter (power divider), (7) two groups of third stage amplifiers (three-stage amplifiers) 56 are set in parallel in the signal upstream extremity of corresponding channel-splitting filter 55, and wherein each group third stage amplifier 56 comprises the amplifier of three arranged in series.In addition these two groups of third stage amplifiers 56 can replace by two groups of two-stage amplifiers, these two groups of two-stage amplifiers are set in parallel in the signal upstream extremity of corresponding channel-splitting filter 55 equally, or these two groups of third stage amplifiers 56 can replace by two one-stage amplifiers, this two one-stage amplifier is set in parallel in the signal upstream extremity of corresponding channel-splitting filter 55 equally.
As shown in Figure 5, each amplifier 51 can be a power amplifier, and this power amplifier such as can be inputted to carry out power amplification and export as it.
As shown in Figure 5, this first mixer in mixer 52 and this second mixer are converted to one second frequency range (F2) in order to the operation frequency range inputted from one first frequency range (F1) and export as it, wherein this first frequency range (F1) is such as between 3.0GHz to 22.0GHz, and preferred range is between 10.7GHz to 12.75GHz, and the second frequency range (F2) is such as between 10.0Hz to 4.0GHz, and preferred range is between 950MHz to 2150MHz, and the upper frequency limit of the second frequency range (F2) is lower than the lower-frequency limit of the first frequency range (F1), and this first mixer and this second mixer are changed according to the output frequency of this first local oscillator in local oscillator 53, wherein conversion regime deducts the output frequency of this first local oscillator by the first frequency range (F1) and obtains this second frequency range (F2), the output frequency of this first machine oscillator is such as between 3.0GHz to 20.0GHz, and preferred range (being such as 9.75GHz) between 8.0GHz to 12.0GHz.
The 3rd mixer in mixer 52 and the 4th mixer are converted to one the 3rd frequency range (F3) in order to the operation frequency range inputted from one first frequency range (F1) and export as it, wherein the 3rd frequency range (F3) is such as between 10.0Hz to 4.0GHz, and preferred range is between 950MHz to 2150MHz, and the 3rd mixer and the 4th mixer are changed according to the output frequency of this second local oscillator in local oscillator 53, wherein conversion regime deducts the output frequency of this second local oscillator by the first frequency range (F1) and obtains the 3rd frequency range (F3), the output frequency of the second local oscillator is such as between 3.0GHz to 20.0GHz, and preferred range (being such as 9.75GHz) between 8.0GHz to 12.0GHz, wherein the upper frequency limit of the 3rd frequency range (F3) is lower than the lower-frequency limit of the first frequency range (F1), the lower-frequency limit of the 3rd frequency range (F3) is lower than the lower-frequency limit of the second frequency range (F2), the upper frequency limit of the 3rd frequency range (F3) is lower than the upper frequency limit of the second frequency range (F2).The output of these four mixers 52 can be coupled to the input of these four amplifiers 51 respectively.
As shown in Figure 5, each band pass filter 54 can allow the input signal in a particular frequency range pass through, and is decayed by the input signal exceeded outside particular frequency range, using the output as each band pass filter 54.In band pass filter 54 this first, second, third and the 4th the output of band pass filter be coupled to the input of this first, the 3rd, second and the 4th mixer in mixer 54 respectively.
As shown in Figure 5, inputted signal can be divided into the output signal of two essence equal-wattages by each channel-splitting filter 55, two of this first channel-splitting filter wherein in channel-splitting filter 55 exports the input of this first band pass filter and this second band pass filter be coupled to respectively in band pass filter 54, and the input that two of this second channel-splitting filter in channel-splitting filter 55 export the 3rd band pass filter and the 4th band pass filter be coupled to respectively in band pass filter 54.
As shown in Figure 5, each amplifier in each group third stage amplifier 56 is such as a low noise amplifier (low noise amplifier, LNA), respective inputted signal respective inputted signal can be amplified and exports, so can amplify and produce the output of low noise by each group third stage amplifier 56 step by step.The input of one of them group of two groups of third stage amplifiers 56 can be sent to from the perpendicular polarization signal collected by this feed horn antenna, such as be sent to this group third stage amplifier being arranged in figure top, and this horizontal polarization signals collected by feed horn antenna can be sent to input of two groups of third stage amplifiers 56 another group wherein, such as, be sent to this group third stage amplifier being positioned at Figure below.Or, the input of one of them group of two groups of third stage amplifiers 56 can be sent to from the right-hand polarized signals collected by this feed horn antenna, it is such as this group third stage amplifier being sent to top in figure, and this left-hand polarized signals collected by feed horn antenna can be sent to input of two groups of third stage amplifiers 56 another group wherein, such as, it is this group third stage amplifier being sent to Figure below.
As shown in Figure 5, signal receiver 50 can produce four output signals respectively via box (set top box) on four groups of corresponding machines four cable transmission to indoor system from four of an integrated circuit (IC) chip 10 corresponding amplifier 13.
As shown in Figure 5, integrated circuit (IC) chip 10 can be encapsulated in electron package structure 40 as shown in Figure 4 above, and be arranged on a host circuit board (not shown) via metal pins 45, and each amplifier 51, each mixer 52, each local oscillator 53, each band pass filter 54, each channel-splitting filter 55 and each group third stage amplifier 56 such as can be separately positioned on other independently in integrated circuit (IC) chip, and be encapsulated in other electron package structure, can be arranged on this host circuit board (not shown) via the tin ball of those other electron package structure or metal pins.
As shown in Figure 5, this first channel-splitting filter in addition in channel-splitting filter 55 and this first and the 3rd signal path between mixer in mixer 52 can omit the setting of band pass filter 54 (that is in the drawings this first and second band pass filter of the top), make this first channel-splitting filter not be coupled to this first mixer and the 3rd mixer via band pass filter 54.This second channel-splitting filter in channel-splitting filter 55 and this second and the 4th signal path between mixer in mixer 52 can omit the setting of band pass filter 54 the 3rd and the 4th band pass filter of below (that is in the drawings), make this second channel-splitting filter not be coupled to this second mixer and the 4th mixer via band pass filter 54.
The second configuration of the first application integrated circuit chip of the present invention
The schematic block diagram of the second configuration of the first integrated circuit (IC) chip 10 described in application of the open the present invention of Fig. 6, wherein in Fig. 1, Fig. 2, Fig. 5 and Fig. 6, the assembly of identical label has identical function, and can consult in Fig. 1, Fig. 2 and Fig. 5 about the relevant of this assembly describes.
The second configuration as shown in Figure 6, the signal that in the range of receiving that one signal receiver 60 can come from signal receiver 60 in order to process, a satellite transmits, wherein this signal can be perpendicular polarization and horizontal polarization signals or right-hand polarization and left-hand polarized signals, this signal and by be positioned at a dish-like reflector (reflector dish) a focus a feed horn antenna collected by, wherein this signal receiver 60 is such as a lnb (low-noise block, LNB).Signal receiver 60 more can comprise compared to the signal receiver 50 of Fig. 5 the signal downstream that four amplifiers 61 are set in parallel in four amplifiers 13 of integrated circuit (IC) chip 10 respectively.Respective input can be amplified as respective output by each amplifier 61, and there is an optimal 1dB compression point (P1dB), can prevent when an excessive electric current by four amplifiers 61 one of them time, the electronic equipment being located at its signal downstream is burnt.In addition, in Figure 5, on signal path between four amplifiers 11 of four mixers 52 and integrated circuit (IC) chip 1, the setting of amplifier 51 can be omitted, make the output of four mixers 52 can not be coupled to the input of four amplifiers 11 of integrated circuit (IC) chip 10 respectively via amplifier 51.
As shown in Figure 6, signal receiver 60 can produce four output signals respectively via box (set top box) on four groups of corresponding machines four cable transmission to indoor system from four corresponding amplifiers 61.
As shown in Figure 6, integrated circuit (IC) chip 10 can be encapsulated in Electronic Packaging module 40 as shown in Figure 4 above, and be arranged on a host circuit board (not shown) via metal pins 45, and each amplifier 51, each mixer 52, each local oscillator 53, each band pass filter 54, each channel-splitting filter 55, each group third stage amplifier 56 and each amplifier 61 such as can be arranged on other independently in integrated circuit (IC) chip, and be encapsulated in other electron package structure, be arranged on this host circuit board (not shown) via the tin ball of those other electron package structure or metal pins.
The third configuration of the first application integrated circuit chip of the present invention
Schematic block diagram of the third configuration of the first integrated circuit (IC) chip 10 described in application of the open the present invention of Fig. 7, wherein in Fig. 1, Fig. 2, Fig. 5, Fig. 6 and Fig. 7, the assembly of identical label has identical function, and can consult in Fig. 1, Fig. 2, Fig. 5 and Fig. 6 about the relevant of this assembly describes.
The third configuration as shown in Figure 7, the signal that in the range of receiving that one signal receiver 70 can come from signal receiver 70 in order to process, a satellite transmits, wherein this signal can be perpendicular polarization and horizontal polarization signals or right-hand polarization and left-hand polarized signals, and by be positioned at a dish-like reflector (reflector dish) a focus a feed horn antenna collected by, wherein this signal receiver 70 is such as a lnb (low-noise block, LNB).Signal receiver 70 more can comprise compared to the signal receiver 50 of Fig. 5 the signal downstream that four signal routers (channel routers) 71 are set in parallel in four amplifiers 13 of integrated circuit (IC) chip 10, and comprises the signal downstream that four amplifiers 72 are set in parallel in four signal routers 71 respectively.
As shown in Figure 7, each signal router 71 can control to use the signal selecting one of them frequency sub-band from the complex operator frequency range (frequency sub-bands) the operation frequency range (referred to here as the 4th frequency range (F4)) of its input signal, and the default frequency sub-band converted to by the signal of selected frequency sub-band in the 4th frequency range (F4) exports as it, wherein the frequency range of the 4th frequency range (F4) is such as between 10Hz to 4GHz, and optimum range is between 950MHz to 2150MHz, and the 4th frequency range has identical frequency range with this second frequency range and/or the 3rd frequency range, and the 4th frequency range has identical frequency range with this second frequency range and/or the 3rd frequency range.
As shown in Figure 7, each amplifier 72 can be inputted to amplify and be exported as it, and there is an optimal 1dB compression point (P1dB), can prevent when an excessive electric current by four amplifiers 72 one of them time, the electronic equipment being located at its signal downstream is burnt.
As shown in Figure 7, signal receiver 70 can produce four output signals respectively via box (set top box) on four groups of corresponding machines four cable transmission to indoor system from four corresponding amplifiers 72.
As shown in Figure 7, integrated circuit (IC) chip 10 can be encapsulated in electron package structure 40 as shown in Figure 4 above, and be arranged on a host circuit board (not shown) via metal pins 45, and each amplifier 51, each mixer 52, each local oscillator 53, each band pass filter 54, each channel-splitting filter 55, each organizes third stage amplifier 56, each amplifier 72 and each signal router 71 such as can be arranged on other independently in integrated circuit (IC) chip, and can be encapsulated in other electron package structure, and can be arranged on this host circuit board (not shown) via the tin ball of those other electron package structure or metal pins.
4th kind of configuration of the first application integrated circuit chip of the present invention
The schematic block diagram of the 4th kind of configuration of the first integrated circuit (IC) chip 10 described in application of the open the present invention of Fig. 8, wherein in Fig. 1, Fig. 2, Fig. 5 and Fig. 8, the assembly of identical label has identical function, and can consult in Fig. 1, Fig. 2 and Fig. 5 about the relevant of this assembly describes.
The 4th kind of configuration as shown in Figure 8, the signal that in the range of receiving that one signal receiver 90 can come from signal receiver 90 in order to process, a satellite transmits, wherein this signal can be perpendicular polarization and horizontal polarization signals or right-hand polarization and left-hand polarized signals, and by be positioned at a dish-like reflector (reflector dish) a focus a feed horn antenna collected by, wherein this signal receiver 90 is such as a lnb (low-noise block, LNB).Signal receiver 90 more can comprise compared to the signal receiver 50 of Fig. 5 the signal downstream that four channel-splitting filters 91 are set in parallel in four amplifiers 51, and comprise the signal downstream that two integrated circuit (IC) chip 10 are set in parallel in four channel-splitting filters 91, wherein integrated circuit (IC) chip 10 can consult the explanation shown in above-mentioned Fig. 1.
As shown in Figure 8, respective input can be divided into the output signal of two essence equal-wattages by each channel-splitting filter 91, is sent to the amplifier 11 of two integrated circuit (IC) chip 10 respectively.These four channel-splitting filters 91 have four outputs that four inputs are coupled to four amplifiers 51 respectively.
As shown in Figure 8, the amplifier 13 that signal receiver 90 can be corresponding from eight of being arranged in two integrated circuit (IC) chip 10 produces eight output signals respectively via box (set top box) in eight cable transmission to the corresponding machine of indoor system eight groups.
As shown in Figure 8, each integrated circuit (IC) chip 10 can be encapsulated in electron package structure 40 as shown in Figure 4 above, and be arranged on a host circuit board (not shown) via metal pins 45, and each amplifier 51, each mixer 52, each local oscillator 53, each band pass filter 54, each channel-splitting filter 55, each group third stage amplifier 56 and each channel-splitting filter 91 such as can be arranged on other independently in integrated circuit (IC) chip, and can be encapsulated in other electron package structure, and can be arranged on this host circuit board (not shown) via the tin ball of those other electron package structure or metal pins.
5th kind of configuration of the first application integrated circuit chip of the present invention
The schematic block diagram of the 5th kind of configuration of the first integrated circuit (IC) chip 10 described in application of the open the present invention of Fig. 9, wherein in Fig. 1, Fig. 2, Fig. 5, Fig. 6 and Fig. 9, the assembly of identical label has identical function, and can consult Fig. 1, Fig. 2, Fig. 5, Fig. 6 about the relevant of this assembly and describe.
The 4th kind of configuration as shown in Figure 9, two groups of perpendicular polarizations that in the range of receiving that one signal receiver 110 can come from signal receiver 110 in order to process, two satellites (that is being respectively one first satellite and one second satellite) transmit respectively and horizontal polarization signals or two groups of right-hand polarizations and left-hand polarized signals, and respectively by be positioned at a dish-like reflector (reflector dish) two focuses (that is being respectively one first focus and one second focus) two feed horn antennas (that is being respectively one first feed horn antenna and one second feed horn antenna) collected by, wherein this signal receiver 110 is such as a lnb (low-noise block, LNB).Signal receiver 110 can comprise (1) two integrated circuit (IC) chip 10 and be arranged in parallel, and this integrated circuit (IC) chip 10 please refer to the explanation shown in above-mentioned Fig. 1; (2) four switch matrix 111 are set in parallel in the signal downstream of two integrated circuit (IC) chip 10; (3) four amplifiers 112 are set in parallel in the signal downstream of four switch matrix 111 respectively.
As shown in Figure 9, each integrated circuit (IC) chip 10 signal upstream extremity electronic building brick can with reference to figure 6 in the explanation of electronic building brick of integrated circuit (IC) chip 10 signal upstream extremity.Can collect at this first feed horn antenna at this first focus place of this dish-like reflector and come from the input that this perpendicular polarization signal that this first satellite transmits to two groups of third stage amplifiers 56 of the signal upstream extremity being located at one first integrated circuit (IC) chip in this two integrated circuit (IC) chip 10 (that is in the drawings top) are wherein positioned at the third stage amplifier of top, this first feed horn antenna can be collected and come from the input that this horizontal polarization signals that this first satellite transmits to two groups of third stage amplifiers 56 of the signal upstream extremity being located at this first integrated circuit (IC) chip are wherein positioned at the third stage amplifier of below.Can collect at this second feed horn antenna at this second focus place of this dish-like reflector and come from the input that this perpendicular polarization signal that this second satellite transmits to two groups of third stage amplifiers 56 of the signal upstream extremity being located at one second integrated circuit (IC) chip in this two integrated circuit (IC) chip 10 (that is in the drawings below) are wherein positioned at the third stage amplifier of top, this second feed horn antenna can be collected and come from the input that this horizontal polarization signals that this second satellite transmits to two groups of third stage amplifiers 56 of the signal upstream extremity being located at this second integrated circuit (IC) chip are wherein positioned at the third stage amplifier of below.
Or, as shown in Figure 9, this the first feed horn antenna at this first focus place of this dish-like reflector can collect come from this right-hand polarized signals that this first satellite transmits to two groups of third stage amplifiers 56 of the signal upstream extremity being located at this first integrated circuit (IC) chip be wherein positioned at above the input of third stage amplifier, this the first feed horn antenna can be collected and come from the input that this left-hand polarized signals that this first satellite transmits to two groups of third stage amplifiers 56 of the signal upstream extremity being located at this first integrated circuit (IC) chip are wherein positioned at the third stage amplifier of below.This second feed horn antenna at this second focus place of this dish-like reflector can collect come from this right-hand polarized signals that this second satellite transmits to two groups of third stage amplifiers 56 of the signal upstream extremity being located at this second integrated circuit (IC) chip be wherein positioned at above the input of third stage amplifier, this second feed horn antenna can be collected and come from the input that this left-hand polarized signals that this second satellite transmits to two groups of third stage amplifiers 56 of the signal upstream extremity being located at this second integrated circuit (IC) chip are wherein positioned at the third stage amplifier of below.
As shown in Figure 9, each switch matrix 111 can have two inputs be arranged in parallel, one of them input is coupled to one of them corresponding amplifier 13 of two integrated circuit (IC) chip 10, another input is coupled to the corresponding amplifier 13 of another integrated circuit (IC) chip 10, one of them of each switch matrix 111 its two input changeable exports as it, and its output is coupled to one of them the corresponding input of four amplifiers 112.
As shown in Figure 9, each amplifier 112 can be inputted to amplify and be exported as it, and there is an optimal 1dB compression point (P1dB), with prevent when an excessive electric current by four amplifiers 112 one of them time, the electronic equipment of its signal downstream is burnt.
As shown in Figure 9, signal receiver 110 can produce four output signals respectively via box (set top box) on four groups of corresponding machines four cable transmission to indoor system from four corresponding amplifiers 112.
As shown in Figure 9, each integrated circuit (IC) chip 10 can be encapsulated in Electronic Packaging module 40 as shown in Figure 4 above, and be arranged on a host circuit board (not shown) via metal pins 45, and each mixer 52, each local oscillator 53, each band pass filter 54, each channel-splitting filter 55, each switch matrix 111, each amplifier 112 and each group third stage amplifier 56 such as can be arranged on other independently in integrated circuit (IC) chip, and can be encapsulated in other electron package structure, and can be arranged on this host circuit board (not shown) via the tin ball of those other electron package structure or metal pins.
More than illustrate just illustrative for the purpose of the present invention, and nonrestrictive, and those of ordinary skill in the art understand; when not departing from the spirit and scope that following claims limit, many amendments can be made, change; or equivalence, but all will fall within the scope of protection of the present invention.

Claims (20)

1. an integrated circuit (IC) chip, is characterized in that, comprising:
First is single-ended to differential amplifier, in order to produce and this first single-ended differential output relevant to the input of differential amplifier;
Second is single-ended to differential amplifier, in order to produce and this second single-ended differential output relevant to the input of differential amplifier;
First group of switching circuit, be positioned at this first single-ended signal downstream to differential amplifier, wherein this one of them first switching circuit of first group of switching circuit comprises a differential input relevant with this first single-ended this differential output to differential amplifier;
Second group of switching circuit, be positioned at this second single-ended signal downstream to differential amplifier, wherein this one of them second switch circuit of second group of switching circuit comprises a differential input relevant with this second single-ended this differential output to differential amplifier; And
First is differential to single-ended amplifier, be positioned at the signal downstream of this first switching circuit and be positioned at the signal downstream of this second switch circuit, wherein this first differentially comprises a differential input relevant with a differential output of this first switching circuit to single-ended amplifier.
2. integrated circuit (IC) chip as claimed in claim 1, it is characterized in that, more comprise the one second differential signal downstream being positioned at this one of them the 3rd switching circuit of first group of switching circuit to single-ended amplifier, and be positioned at the signal downstream of this one of them the 4th switching circuit of second group of switching circuit, wherein this second differentially comprises a differential input relevant with a differential output of the 3rd switching circuit to single-ended amplifier.
3. integrated circuit (IC) chip as claimed in claim 1, it is characterized in that, more comprise the one second differential signal downstream being positioned at this one of them the 3rd switching circuit of first group of switching amplifier to single-ended amplifier, and be positioned at the signal downstream of this one of them the 4th switching circuit of second group of switching circuit, wherein this second differentially comprises a differential input relevant with a differential output of the 4th switching circuit to single-ended amplifier.
4. integrated circuit (IC) chip as claimed in claim 1, it is characterized in that, more comprise one first group and be differentially positioned at this first single-ended signal downstream to differential amplifier to differential amplifier, and be positioned at the signal upstream extremity of this first group of switching circuit, wherein this first group differential to differential amplifier, one of them first differentially comprises a differential input relevant with this first single-ended this differential output to differential amplifier to differential amplifier, an and differential output relevant with this differential input of this first switching circuit.
5. integrated circuit (IC) chip as claimed in claim 4, it is characterized in that, more comprise one second group and be differentially positioned at this second single-ended signal downstream to differential amplifier to differential amplifier, and be positioned at the signal upstream extremity of this second group of switching circuit, wherein this second group differential to differential amplifier, one of them second differentially comprises a differential input relevant with this second single-ended this differential output to differential amplifier to differential amplifier, an and differential output relevant with this differential input of this second switch circuit.
6. integrated circuit (IC) chip as claimed in claim 4, it is characterized in that, when this first switching circuit switch to make this first differential to differential amplifier be coupled to this first differential to single-ended amplifier time, this first differentially switches to a power opening state to differential amplifier, when this first switching circuit switch to make this first differential to differential amplifier be not coupled to this first differential to single-ended amplifier time, this first differentially switches to a power down state to differential amplifier.
7. integrated circuit (IC) chip as claimed in claim 1, it is characterized in that, this first single-ended this differential output to differential amplifier has in fact the phase difference of 180 degree.
8. integrated circuit (IC) chip as claimed in claim 1, it is characterized in that, this differential output of this first switching circuit has in fact the phase difference of 180 degree.
9. integrated circuit (IC) chip as claimed in claim 1, it is characterized in that, this differential input of this first switching circuit has in fact the phase difference of 180 degree.
10. integrated circuit (IC) chip as claimed in claim 1, it is characterized in that, this first differential this differential input to single-ended amplifier has in fact the phase difference of 180 degree.
11. integrated circuit (IC) chip as claimed in claim 1, it is characterized in that, more comprise one the 3rd and single-endedly single-endedly with the 3rd input a relevant differential output to one of differential amplifier in order to produce to differential amplifier, this integrated circuit (IC) chip more comprises one the 4th and single-endedly single-endedly with the 4th inputs a relevant differential output to one of differential amplifier in order to produce to differential amplifier, this integrated circuit (IC) chip more comprises one the 3rd group of switching circuit and is positioned at the 3rd single-ended signal downstream to differential amplifier, wherein the 3rd group of one of them the 3rd switching circuit of switching circuit comprises the relevant differential input of this differential output to differential amplifier single-ended with the 3rd, this integrated circuit (IC) chip more comprises one the 4th group of switching circuit and is positioned at the 4th single-ended signal downstream to differential amplifier, wherein the 4th group of one of them the 4th switching circuit of switching circuit comprises the relevant differential input of this differential output to differential amplifier single-ended with the 4th, wherein this first differential signal downstream being positioned at the 3rd switching circuit to single-ended amplifier, and be positioned at the signal downstream of the 4th switching circuit.
12. integrated circuit (IC) chip as claimed in claim 1, it is characterized in that, described integrated circuit (IC) chip can be arranged in a signal receiver, in order to process the signal transmitted from one or more satellite.
13. 1 kinds of signal receivers, in order to process the signal transmitted from one or more satellite, it is characterized in that, this signal receiver comprises:
First is single-ended to differential amplifier, first single-endedly inputs a relevant differential output to one of differential amplifier in order to produce with this;
Second is single-ended to differential amplifier, second single-endedly inputs a relevant differential output to one of differential amplifier in order to produce with this;
First group of switching circuit, be positioned at this first single-ended signal downstream to differential amplifier, wherein this one of them first switching circuit of first group of switching circuit comprises a differential input relevant with this first single-ended this differential output to differential amplifier;
Second group of switching circuit, be positioned at this second single-ended signal downstream to differential amplifier, wherein this one of them second switch circuit of second group of switching circuit comprises a differential input relevant with this second single-ended this differential output to differential amplifier; And
First is differential to single-ended amplifier, be positioned at the signal downstream of this first switching circuit and be positioned at the signal downstream of this second switch circuit, wherein this first differentially comprises a differential input relevant with a differential output of this first switching circuit to single-ended amplifier.
14. signal receivers as claimed in claim 13, it is characterized in that, more comprise the one second differential signal downstream being positioned at this one of them the 3rd switching circuit of first group of switching circuit to single-ended amplifier, and be positioned at the signal downstream of this one of them the 4th switching circuit of second group of switching circuit, wherein this second differentially comprises a differential input relevant with a differential output of the 3rd switching circuit to single-ended amplifier.
15. these signal receivers as claimed in claim 13, it is characterized in that, more comprise the one second differential signal downstream being positioned at this one of them the 3rd switching circuit of first group of switching amplifier to single-ended amplifier, and be positioned at the signal downstream of this one of them the 4th switching circuit of second group of switching circuit, wherein this second differentially comprises a differential input relevant with a differential output of the 4th switching circuit to single-ended amplifier.
16. signal receivers as claimed in claim 13, it is characterized in that, more comprise one first group and be differentially positioned at this first single-ended signal downstream to differential amplifier to differential amplifier, and be positioned at the signal upstream extremity of this first group of switching circuit, wherein this first group differential to differential amplifier, one of them first differentially comprises a differential input relevant with this first single-ended this differential output to differential amplifier to differential amplifier, an and differential output relevant with this differential input of this first switching circuit.
17. signal receivers as claimed in claim 16, it is characterized in that, more comprise one second group and be differentially positioned at this second single-ended signal downstream to differential amplifier to differential amplifier, and be positioned at the signal upstream extremity of this second group of switching circuit, wherein this second group differential to differential amplifier, one of them second differentially comprises a differential input relevant with this second single-ended this differential output to differential amplifier to differential amplifier, an and differential output relevant with this differential input of this second switch circuit.
18. signal receivers as claimed in claim 16, it is characterized in that, when this first switching circuit switch to make this first differential to differential amplifier be coupled to this first differential to single-ended amplifier time, this first differentially switches to a power opening state to differential amplifier, when this first switching circuit switch to make this first differential to differential amplifier be not coupled to this first differential to single-ended amplifier time, this first differentially switches to a power down state to differential amplifier.
19. signal receivers as claimed in claim 13, is characterized in that, this first single-ended this differential output to differential amplifier has in fact the phase difference of 180 degree.
20. signal receivers as claimed in claim 13, it is characterized in that, more comprise one the 3rd and single-endedly single-endedly with the 3rd input a relevant differential output to one of differential amplifier in order to produce to differential amplifier, this signal receiver more comprises one the 4th and single-endedly single-endedly with the 4th inputs a relevant differential output to one of differential amplifier in order to produce to differential amplifier, this signal receiver more comprises one the 3rd group of switching circuit and is positioned at the 3rd single-ended signal downstream to differential amplifier, wherein the 3rd group of one of them the 3rd switching circuit of switching circuit comprises the relevant differential input of this differential output to differential amplifier single-ended with the 3rd, this signal receiver more comprises one the 4th group of switching circuit and is positioned at the 4th single-ended signal downstream to differential amplifier, wherein the 4th group of one of them the 4th switching circuit of switching circuit comprises the relevant differential input of this differential output to differential amplifier single-ended with the 4th, wherein this first differential signal downstream being positioned at the 3rd switching circuit to single-ended amplifier, and be positioned at the signal downstream of the 4th switching circuit.
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