CN104851938B - Method for manufacturing solar cells with a p-doped CdTe layer having a reduced thickness - Google Patents

Method for manufacturing solar cells with a p-doped CdTe layer having a reduced thickness Download PDF

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CN104851938B
CN104851938B CN201410215748.3A CN201410215748A CN104851938B CN 104851938 B CN104851938 B CN 104851938B CN 201410215748 A CN201410215748 A CN 201410215748A CN 104851938 B CN104851938 B CN 104851938B
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layer
cdte
substrate
doping
sacrificial
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CN104851938A (en
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克里什纳库马·维拉潘
彭寿
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China Building Materials International Engineering Group Co Ltd
CTF Solar GmbH
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China Building Materials International Engineering Group Co Ltd
CTF Solar GmbH
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1828—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe
    • H01L31/1836—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe comprising a growth substrate not being an AIIBVI compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/0296—Inorganic materials including, apart from doping material or other impurities, only AIIBVI compounds, e.g. CdS, ZnS, HgCdTe
    • H01L31/02963—Inorganic materials including, apart from doping material or other impurities, only AIIBVI compounds, e.g. CdS, ZnS, HgCdTe characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/0445—PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/073—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIBVI compound semiconductors, e.g. CdS/CdTe solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/543—Solar cells from Group II-VI materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention relates to a method for manufacturing a solar cell with a p-doped CdTe layer having a reduced thickness. In particular, the invention proposes a method for manufacturing a thin film CdTe solar cell having a pinhole-free and homogeneously doped CdTe layer with a reduced layer thickness. The method according to the invention is an efficient method to prevent shunting of the solar cell, to improve the reliability and long-term stability of the solar cell and to provide a uniform doping of the CdTe layer. This is achieved by applying a sacrificial doping layer between a first CdTe layer with large grains and a second CdTe layer with small grains, which together form a CdTe layer of the solar cell. In addition, if the sacrificial doping layer contains a halogen, the CdCl can be omitted2And (5) activating treatment.

Description

Method for manufacturing solar cells with a p-doped CdTe layer having a reduced thickness
Technical Field
The object of the present invention is a method for manufacturing CdTe solar cells with increased efficiency.
Background
The distribution of thin film solar cells can be further accelerated by increasing their electrical efficiency in light conversion. CdTe-based solar cells have proven to be particularly promising in this respect.
In the prior art, CdTe solar cells have the following structure: a transparent conductive oxide layer (TCO) is deposited on the glass substrate as a front contact. The TCO layer may include a high resistance buffer layer that helps minimize shunting in the solar cell. Over which a cadmium sulfide (CdS) layer is deposited and over which a cadmium telluride (CdTe) layer is deposited. Finally, a metal layer is applied to collect charge carriers. This method is called a superstructuring.
In the manufacture of solar cells, a substrate (preferably glass) forms a substrate on which subsequent layers are successively deposited.
In the preparation of CdTe solar modules, the thickness of the CdTe layer is generally maintained in the range from 4 to 5 μm. However, theoretical simulations of CdTe solar cells indicate that solar cells with a 1 μm CdTe layer can also yield reasonably high efficiencies. In principle, reducing the CdTe film thickness from 4 μm to 2 μm can help reduce CdTe material consumption by 30-40% in component manufacture. This CdTe film thickness reduction can also help to reduce layer deposition time and thereby speed device fabrication.
CdTe is typically deposited at substrate temperatures >500 ℃ to obtain high efficiency solar cells. The CdTe layer at this temperature has large grains, which can lead to the formation of pinholes. Therefore, simply reducing the layer thickness has several negative effects on the efficiency and long-term stability of the solar cell. While reducing the film thickness (< 3 μm), pinholes are formed in the CdTe layer, resulting in shunting of the solar cell. This problem is even more pronounced if an etching process is included in the solar cell fabrication, which would result in poor performance of the solar cell. In addition, lowering the shunt resistance value results in a low fill factor and ultimately in a reduced efficiency. Therefore, it is necessary to minimize the formation of pinholes in the CdTe layer in order to obtain a high efficiency solar cell.
In addition to this, increasing the p-doping of the CdTe layer is also important for obtaining high efficiency solar cells. A further increase in the efficiency of CdTe solar cells can be achieved by doping the CdTe layer. According to theoretical predictions, the high degree of p-doping of CdTe is limited due to the formation self-compensation effect. By using the appropriate doping element and the method of providing the doping element to the CdTe layer after deposition of the CdTe layer, only a certain level of p-doping can be achieved. During the production of CdTe solar cells, extrinsic p-doping of the CdTe layer is generally carried out after the activation process, which includes a post-annealing treatment to induce diffusion of the doping elements. A well-known and simple p-dopant for CdTe layers is Cu.
Disclosure of Invention
The aim of the invention is to obtain a solar cell comprising a doped CdTe layer with reduced thickness and without pinholes. In addition, the invention aims to simplify the manufacturing method of the CdTe solar cell.
According to the invention, the method for manufacturing a CdTe solar cell comprises a step of forming a first CdTe layer with large grains on a base layer, a step of forming a sacrificial doped layer containing a doping element on the first CdTe layer, and a step of forming a second CdTe layer with small grains on the sacrificial doped layer.
Preferred materials for the sacrificial doping layer are selected from materials comprising copper, phosphorus, antimony, bismuth, molybdenum or manganese as the doping element. According to one embodiment, the doping element is provided as an elemental layer. In another embodiment, the doping elements are provided as a combination of different elements, such as copper and antimony or antimony and bismuth, or as a complex, preferably a compound of any of the doping elements mentioned with a halogen, such as SbCl3. The preferred halogen for the complex of the sacrificial doping layer is fluorine (F), most preferably chlorine (Cl). Preferably the compound used is chloride.
The sacrificial doping layer may be applied using a method according to the prior art. Preferably, physical or dry chemical methods or wet chemical methods are used, such as, but not limited to:
-a sputtering step in which a metal layer is sputtered,
-an electro-deposition step of depositing,
-a spray of a halogen containing compound, wherein the compound is dissolved in water or another known solvent;
-spin-coating,
-dipping the substrate (or the surface of the first CdTe layer) into a solution containing the doping element or compound thereof;
sponge roll coating, etc.
The halogen containing compound is preferably applied by wet processing, more preferably by sponge roll coating.
The thickness of the sacrificial doped layer depends on the size of the CdTe layer resulting from fusing the first and second CdTe layers and the doping element used. With respect to the thickness of the CdTe layer, the thickness of the sacrificial doped layer is selected such that a predetermined doping level of the CdTe layer is achieved when the sacrificial doped layer is fully dissolved. In the case of elemental antimony as the sacrificial doped layer, the thickness of the sacrificial doped layer is preferably about one thousandth of the thickness of the CdTe layer. Some examples are given in table 1, wherein also the approximate thickness of each of the first and second CdTe layers is given.
TABLE 1
However, other doping elements or complexes containing the doping elements may also be used. Typically, the thickness of the sacrificial doped layer is preferably in the range of 2nm to 15 nm. If copper is used as the doping element, the thickness of the sacrificial doping layer should be reduced relative to when other doping elements are used, since a large amount of copper will cause the solar cell to degrade over time. Preferably, the thickness of the sacrificial doped layer comprising copper as doping element should be 30% less than the thickness of the sacrificial doped layer comprising another doping element, such as antimony.
The sacrificial doping layer is preferably applied on the first CdTe layer at a substrate temperature in the range of room temperature to 350 ℃. The substrate temperature should not exceed 350 deg.c, since higher substrate temperatures would make it difficult to apply the sacrificial doping layer with the small thickness described above due to re-evaporation problems. If a halogen-containing compound is used to apply the sacrificial doping layer, the substrate temperature is preferably in the range of room temperature to 100 ℃.
The first CdTe layer is applied over the base layer as a layer with large grains. The grains of the first CdTe layer have a size on the order of microns, e.g., in the range of 2 to 5 μm. This is achieved by depositing the first CdTe layer at a substrate temperature in the range 490 to 540 ℃, wherein the thickness of the first CdTe layer is between 0.5 and 6 μm, more preferably between 1 and 1.8 μm. If a solar cell is fabricated with the above layer configuration, the base layer is a layer stack comprising a transparent substrate, a transparent front contact layer and a CdS layer. If the solar cell is manufactured in a substrate configuration, the base layer is a layer stack comprising a substrate and a back contact layer. More details of these configurations are described later.
The thickness of the second CdTe layer is preferably between 1% and 100% of the total thickness of the first CdTe layer, depending on the requirements of the overall CdTe layer thickness. More preferably, the thickness of the second CdTe layer is between 20% and 30% of the total CdTe layer thickness. The overall CdTe layer thickness may be in the range of 0.5 to 8 μm. Only for very thin overall CdTe layers having a layer thickness of 0.5 to 1.5 μm, the thickness of the second CdTe layer can be about 40-50% of the overall CdTe layer thickness, in order to fill the pinholes and/or grain boundaries of the first CdTe layer. The thickness percentage of the thickness of the second layer is given by way of example only. According to the invention, the method can be carried out at a second layer thickness in any thickness range.
The second CdTe layer is applied as a layer with small grains and serves to fill or cover the pinholes and/or grain boundaries of the first CdTe layer. The grains of the second CdTe layer have a size on the nanometer scale, for example in the range of 100nm to 500 nm. Thus, the formation of shunts between the back and front contacts of the solar cell and the migration of impurities along grain boundaries within the CdTe layer can be reduced or avoided. The deposition of the small grain layer is achieved by depositing the second CdTe layer at a substrate temperature in the range of 200 ℃ to 350 ℃.
The first and the second CdTe layers may be deposited by any known method, including but not limited to, short distance (d) sublimation (CSS), Chemical Bath Deposition (CBD), sputtering, electrodeposition, or other physical or chemical methods.
According to one embodiment of said method for manufacturing a solar cell, said method also comprises a temperature treatment step carried out after the deposition of said second CdTe layer. That is, the temperature treatment step can be carried out directly after the step of applying the second CdTe layer, or can be carried out at a subsequent processing step, for example after applying a cover layer, which can be a sacrificial cover layer.
The temperature treatment step includes heating the substrate to a temperature in the range of 300 ℃ to 550 ℃. Most preferably, if the second CdTe layer is exposed, i.e. not covered by another layer, the substrate temperature should not exceed 450 ℃ during the temperature treatment process to prevent re-evaporation of CdTe.
Preferably, a halogen containing material is disposed on the surface of the second CdTe layer during the temperature treatment step. This process step corresponds to the so-called activation step known from the prior art in the manufacture of CdTe solar cells. Typically, for this temperature treatment step, CdCl is added2Used as the halogen-containing material, wherein the CdCl is annealed at a defined temperature (typically in the range of 380-440 ℃) in an air atmosphere by wet chemistry or by vacuum evaporation2Applied to the CdTe layer. The benefits of this activation step include a reduction in the lattice mismatch between the CdS layer/CdTe layer and the passivation of the CdTe layer grain boundaries. The CdCl2Activation induces interdiffusion between the CdS and CdTe layers, helping to achieve a smooth electron band transition at the CdS/CdTe junction. However, the method has a disadvantage in that CdCl2Are potentially hazardous materials and are therefore difficult to handle in a production line.
CdCl can be avoided if the sacrificial doped layer contains a halogen2Since the halogen component contained in the sacrificial doped layer helps to passivate the grain boundaries in the CdTe layer. The temperature treatment step of the invention is therefore preferably carried out without providing halogen-containing materials on the surface of said second CdTe layer, since the process of the invention simulates CdCl under these conditions2And (5) an activation process.
The thermal energy available during the temperature treatment step induces the decomposition of the sacrificial doped layer into its components and/or the diffusion of its components, in particular of the doping element, into and/or through the CdTe layer. Thus, the sacrificial doped layer dissociates, which represents a characteristic of the doped layer as a sacrificial layer. As a result, the first CdTe layer and the second CdTe layer are now proximate to each other and form a CdTe layer of the solar cell.
However, the solar cell manufacturing method may comprise different process steps involving higher temperatures, such as deposition of CdTe layers. Thus, during the deposition of the sacrificial doped layer, the deposition of the second CdTe layer and/or other process steps carried out after the application of the second CdTe layer, such as the process step of applying a contact layer, the dissolution of the sacrificial doped layer and the diffusion of its components can also take place at least partially. Thus, the temperature treatment step described above may be maintained if a sacrificial halogen-containing doped layer is used and if the process steps following the step of applying the sacrificial doped layer provide sufficient thermal budget to dissolve the sacrificial doped layer and diffuse the doping element.
Since the diffusion of the doping element takes place "inside" the CdTe layer, the CdTe layer is more uniformly doped than if a doped layer were provided over the complete CdTe layer deposited as in the prior art. At least, the application of a lower heat sink to the solar cell during the manufacturing process achieves an almost uniform doping of the CdTe layer compared to the processes according to the prior art. By "nearly uniform doping" is meant that no or only a small concentration gradient of the doping element is measured within the CdTe layer.
In another embodiment of the invention, depending on the choice of the material of the doping layer, an excess of doping element, i.e. atoms of doping element that cannot be incorporated into the CdTe crystals, can accumulate on the surface of the second CdTe layer. This occurs due to the preferential impurity diffusion assisted by the grain boundaries, in particular due to the second CdTe layer with smaller grains. Excess doping elements may be washed or rinsed away by use of a suitable solvent, or may be removed by a subsequent nitric-phosphoric acid etching process.
The method of manufacturing a solar cell of the present invention can be used to manufacture a solar cell in the above layer configuration or in the substrate configuration.
The method for manufacturing the solar cell with the above layer structure further comprisesProviding a transparent substrate, preferably glass, applying a transparent front contact layer or layer stack, such as TCO, and applying a CdS layer on said transparent front contact layer or layer stack. After applying the CdS layer, the inventive method described above is carried out, wherein the layer stack comprising the transparent substrate, the transparent front contact layer and the CdS layer serves as a base layer for applying the first CdTe layer. That is, the first CdTe layer, the sacrificial doped layer, and the second CdTe layer are applied in this order over the CdS layer. In addition, the temperature treatment process can be carried out before the application of the back contact layer or layer stack, for example CdCl2An activation process and a nitric-phosphoric acid etching process. The CdTe surface is washed with a suitable solution, such as water or methanol. The back contact layer may comprise a metal, any other suitable conductive material or a suitable semiconducting layer (e.g. Sb), according to the prior art3Te2）。
In the method for manufacturing a solar cell of substrate construction, the steps are essentially carried out in the reverse order, except for the steps of applying the first CdTe layer with large grains, applying the sacrificial doped layer and applying the second CdTe layer with small grains. The substrate may be a flexible metal foil, such as molybdenum, which may act as a back contact to collect light induced charges, or any other suitable substrate according to the prior art. Thus, first a substrate is provided, on which the back contact layer or layer stack is applied, and then the first CdTe layer, the sacrificial doped layer and the second CdTe layer are applied. That is, the layer stack comprising the substrate and the back contact layer serves as a base layer to which the first CdTe layer is applied. Then, the CdS layer and the transparent front contact layer, e.g. TCO, are applied, wherein a temperature treatment process as described above may be carried out after the second CdTe layer is applied or even after the CdS layer and/or the transparent front contact layer is applied. Optionally, depending on the CdS and TCO deposition process, the diffusion of the doping element may also have occurred during the CdS and/or TCO deposition process. If CdCl is included2An activation process, the doping element may also diffuse during the activation process. Under such conditions, canAn additional post-annealing process to diffuse the doping element can be unnecessary.
The process steps of applying the (transparent) substrate, applying the pre-contact layer, applying the CdS layer and applying the back contact layer are carried out according to methods known from the prior art and are therefore not described in detail here. It should be noted that in the manufacturing process of solar cells of substrate construction, the step of applying the CdS layer should be carried out at a relatively low substrate temperature in the range of 200 to 350 ℃ in order to prevent re-evaporation of the CdTe layer. This can be achieved by using a well known sputtering method for depositing the CdS layer.
Drawings
Fig. 1 schematically shows the layer structure of a solar cell according to the prior art. The solar cell comprises a layer sequence on a substrate (1) consisting of a front contact (21), a CdS layer (3), a CdTe layer (4) and a back contact (22).
Fig. 2a to 2d schematically show layer sequences as can be observed during the course of the method of the invention.
Detailed Description
The method according to the invention is explained below in a first exemplary embodiment showing the production of a solar cell with the above layer construction, without the embodiment being meant to be limited.
As shown in fig. 2a, the front contact (21) and the CdS layer (3) have been applied on a transparent substrate (1) by means of a method according to the prior art. As front contact (21), a 450nm thick transparent bilayer [ fluorine doped tin oxide (350 nm) as conductive layer and tin oxide (100 nm) as high resistance buffer layer ] (as TCO) was applied. The CdS layer (3) reaches a thickness of 90nm and is deposited using CSS technique. Thereon, a first CdTe layer (41) according to the invention having a thickness of 1.6 μm is deposited. The deposition process was carried out as a CSS process at a substrate temperature of 530 ℃, resulting in large grains of the deposited layer.
Fig. 2b schematically shows a sacrificial doped layer (5) applied over the first CdTe layer (41). The sacrificial doping layer (5) consists of elemental antimony (Sb) and is deposited with a thickness of 2nm using a sputtering method at a substrate temperature of 280 ℃.
Fig. 2c schematically shows the layer stack of the solar cell after deposition of a second CdTe layer (42) on the sacrificial doped layer (5). A second CdTe layer (42) is deposited using the CSS process at a substrate temperature of 300 ℃ and a thickness of 400 nm. The second CdTe layer (42) has small grains covering the grain boundaries of the first CdTe layer (41). Due to the very small layer thickness of the sacrificial doped layer (5), the sacrificial doped layer (5) does not completely cover the grain boundaries of the first CdTe layer (41). However, it is uniformly distributed on the first CdTe layer surface. This ensures a uniform doping of the resulting CdTe layer. In addition, the sacrificial doped layer (5) starts to split during the deposition of the second CdTe layer (42), wherein antimony moves into the first CdTe layer (41) and into the partially deposited second CdTe layer (42). However, the already diffused antimony atoms and the reduction of the thickness of the sacrificial doped layer (5) are not illustrated in fig. 2c, since antimony does not diffuse to a considerable extent into the first CdTe layer (41) and the second CdTe layer (42) in this process step.
Then, the known CdCl is mixed at 385 deg.C2The activation step was carried out for 20 minutes.
Fig. 2d schematically shows the solar cell after completion of the back contact step. A back contact (22) has been produced which has a layer sequence corresponding to the layer sequences known from the prior art and comprises a metal, in this case molybdenum (Mo). As shown, the sacrificial doped layer (5) is fully dissociated and diffused into the CdTe layer (40) resulting from the fusing of the first and second CdTe layers (41, 42), wherein the resulting CdTe layer (40) is doped with antimony (indicated by the dots within the CdTe layer (40)). The diffusion of the doping element into the first and second CdTe layers (41, 42), and the global dissociation of the sacrificial doping layer (5), may be in CdCl2During the activation step and/or at any time during the creation of the back contact (22), resulting in the illustrated layer arrangement.
The CdTe layer (40) is almost uniformly doped, which means that no or only a small concentration gradient of antimony is visible in the CdTe layer (40).
Reference numerals
1 substrate (glass)
21 front contact (transparent, TCO)
22 Back contact (Metal)
3 CdS layer
4 CdTe layer (prior art)
40 CdTe layer
41 first CdTe layer
42 second CdTe layer
5 sacrificial doping layer

Claims (16)

1. A method of fabricating a solar cell, comprising the steps of:
a) a first CdTe layer with large grains is applied over the base layer,
b) applying a sacrificial doping layer comprising a doping element on said first CdTe layer, and
c) applying a second CdTe layer with small grains on the sacrificial doped layer;
wherein the sacrificial doped layer dissolves and decomposes in step c) and/or in other steps after step c).
2. The method of claim 1, characterized in that the sacrificial doping layer comprises one of copper, phosphorus, antimony, bismuth, molybdenum or manganese as the doping element.
3. A method according to claim 1 or 2, characterized in that the doping element is provided as an elemental layer.
4. Method according to claim 1 or 2, characterized in that the doping elements are provided as a combination of different doping elements or as a composite.
5. The method according to claim 4, characterized in that the complex comprises a halogen.
6. Method according to claim 1 or 2, characterized in that the sacrificial doping layer is applied by a sputtering method or by a method using a liquid solution containing the doping element.
7. Method according to claim 1 or 2, characterized in that the sacrificial doping layer is applied at a thickness in the range of 2nm to 15 nm.
8. The method according to claim 1 or 2, characterized in that the sacrificial doping layer is applied at a substrate temperature in the range of room temperature to 350 ℃.
9. The method according to claim 1 or 2, characterized in that said first CdTe layer is deposited at a thickness ranging from 0.5 μ ι η to 6 μ ι η, at a substrate temperature ranging from 490 ℃ to 540 ℃.
10. The process according to claim 1 or 2, characterized in that the second CdTe layer is deposited at a thickness of 20% to 40% of the overall layer thickness of the CdTe layer consisting of the first and second CdTe layers, at a substrate temperature ranging from 200 ℃ to 350 ℃.
11. The method according to claim 1 or 2, characterized in that the method further comprises a temperature treatment step carried out at a temperature in the range of 300 ℃ to 550 ℃ after step c).
12. The method according to claim 11, characterized in that during the temperature treatment step, a halogen containing material is disposed on the surface of the second CdTe layer.
13. Method according to claim 1 or 2, characterized in that the method further comprises the steps of:
d) a transparent substrate is provided and is provided,
e) a transparent front contact layer is applied to the substrate,
f) applying a CdS layer, and
g) a back contact layer is applied to the substrate,
wherein said steps d), e) and f) are performed in this order before performing said steps a), b) and c), and said step g) is performed after performing said steps a), b) and c), and wherein a layer stack comprising said transparent substrate, said transparent front contact layer and said CdS layer is said base layer.
14. Method according to claim 1 or 2, characterized in that the method further comprises the steps of:
h) a substrate is provided, and the substrate,
i) a back contact layer is applied to the substrate,
j) applying a CdS layer, and
k) a transparent front contact layer is applied to the substrate,
wherein the steps h) and i) are performed in this order before performing the steps a), b) and c), and the steps j) and k) are performed after performing the steps a), b) and c), and wherein the layer stack comprising the substrate and the back contact is the base layer.
15. The method according to claim 9, characterized in that the first CdTe layer is deposited at a thickness ranging from 1 μ ι η to 1.8 μ ι η at a substrate temperature ranging from 490 ℃ to 540 ℃.
16. The method according to claim 11, characterized in that it further comprises a temperature treatment step carried out at a temperature in the range of 300 ℃ to 450 ℃ after step c).
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