CN104851790A - Method for manufacturing gate insulation layer - Google Patents
Method for manufacturing gate insulation layer Download PDFInfo
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- CN104851790A CN104851790A CN201410050579.2A CN201410050579A CN104851790A CN 104851790 A CN104851790 A CN 104851790A CN 201410050579 A CN201410050579 A CN 201410050579A CN 104851790 A CN104851790 A CN 104851790A
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- silicon nitride
- layer
- nitride layer
- silicon oxide
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 238000009413 insulation Methods 0.000 title abstract 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 50
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 50
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 40
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 35
- 238000000151 deposition Methods 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 11
- 239000001257 hydrogen Substances 0.000 claims abstract description 11
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 11
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000012212 insulator Substances 0.000 claims description 23
- 230000008021 deposition Effects 0.000 claims description 16
- 239000007789 gas Substances 0.000 claims description 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- 238000006356 dehydrogenation reaction Methods 0.000 claims description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims description 10
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 8
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 8
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 8
- 229910021529 ammonia Inorganic materials 0.000 claims description 4
- 239000001272 nitrous oxide Substances 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 6
- 239000001301 oxygen Substances 0.000 abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 abstract description 6
- 229910001413 alkali metal ion Inorganic materials 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- 239000011521 glass Substances 0.000 abstract description 3
- 230000000903 blocking effect Effects 0.000 abstract description 2
- 238000007599 discharging Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 239000003595 mist Substances 0.000 description 14
- 238000005137 deposition process Methods 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 229910016344 CuSi Inorganic materials 0.000 description 2
- 229910003902 SiCl 4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Formation Of Insulating Films (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a method for manufacturing a gate insulation layer. The method comprises successively depositing a silicon nitride layer and a silicon oxide layer on a gate according to a chemical vapor deposition method, thereby obtaining the silicon nitride layer and the gate insulation layer which is successively stacked on the gate insulation layer, wherein the gate is a Cu gate. The method for manufacturing the gate insulation layer has functions of effectively protecting the Cu gate and an active semiconductor layer, effectively isolating oxygen by the deposited silicon nitride layer for preventing oxidation of Cu, and effectively isolating hydrogen by the deposited silicon oxide layer for preventing reduction of the active semiconductor layer. Furthermore the gate insulation layer with the silicon nitride/silicon oxide stacked structure has functions of effectively blocking alkali metal ions in a glass substrate, improving antistatic discharging capability, reducing leakage current, and improving an equivalent capacitance.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to a kind of method manufacturing gate insulator.
Background technology
At present, flat-panel monitor, such as liquid crystal indicator, organic electroluminescence display device and method of manufacturing same etc., main adopt driven with active matrix pattern, by the thin-film transistor (TFT) of driving circuit section as switch element, is pixel electrode output signal.The performance of thin-film transistor is the key factor determining display unit quality, requires that it possesses height and punctures withstand voltage, low-leakage current, to strengthen reliability, effectively reduces the fraction defective of display unit.
Common thin-film transistor generally comprises: insulated substrate, grid, gate insulator, active semiconductor layer and source/drain electrode layer, wherein gate insulator is between grid and active semiconductor layer, for the stability of TFT and antistatic all extremely important.Large scale, high-resolution, high-frequency drive are the main development directions of flat-panel monitor, therefore also can increase the demand that TFT mobility improves and metal wire impedance reduces.Current most method adopts indium gallium zinc oxide (IGZO) to substitute the active semiconductor layer of amorphous silicon (A-Si) as TFT, and mobility can by about 1cm
2/ (VS) is increased to about 10cm
2/ (VS), adopts Cu substitute for Al as grid simultaneously, and the resistance that wherein resistance of Cu is about 2 μ Ω and Al is about 3 ~ 3.5 μ Ω.But adopt during said method and there are some problems equally, IGZO layer is very responsive to hydrogen, and hydrogen can make the electrical property of IGZO layer change, and active layer even can be caused to be conductor from semiconductor variable; Grid Cu is very responsive to oxygen, and Cu can be oxidized by oxygen, thus loses the due effect of grid.
Current most of thin-film transistor adopts silicon oxide layer as gate insulator, but Cu meeting is direct and silica forms CuSi
xo
yand increase impedance, simultaneously compared with silicon nitride, the dielectric constant of silica is less, and anti-static electrictity release ability is poor, and leakage current is higher, poor for the alkali metal ion blocking effect in substrate, easily affects the performance of TFT.
Therefore, need at present a kind of method manufacturing gate insulator to overcome the problems referred to above and to take into account stability and the antistatic effect of TFT.
Summary of the invention
For solving the problem, the present invention, by forming the gate insulator of silicon nitride layer and silicon oxide layer stacked above one another, protects grid and active semiconductor layer effectively, improves the performance of thin-film transistor.
Additional aspect of the present invention and advantage will partly be set forth in the following description, and partly will become obvious from description, or can the acquistion by practice of the present invention.
The invention provides a kind of method manufacturing gate insulator, comprise: adopt chemical vapour deposition technique, deposited silicon nitride layer and silicon oxide layer successively on grid, obtain the gate insulator of described silicon nitride layer and described silicon oxide layer stacked above one another, wherein said grid is Cu grid.
In an execution mode of the inventive method, the temperature depositing described silicon nitride layer is 420 ~ 450 DEG C, and the temperature depositing described silicon oxide layer is 420 ~ 450 DEG C.
In another execution mode of the inventive method, the unstrpped gas depositing described silicon nitride layer is monosilane and ammonia, and the unstrpped gas depositing described silicon oxide layer is monosilane and nitrous oxide.
In another execution mode of the inventive method, the flow-rate ratio of described monosilane and described ammonia is 1:1 to 1:3.
In another execution mode of the inventive method, the flow-rate ratio of described monosilane and described nitrous oxide is 1:1 to 1:3.
In another execution mode of the inventive method, described method passes into nitrogen before being also included in the described silicon nitride layer of deposition.
In another execution mode of the inventive method, described method passes into hydrogen before being also included in and passing into described nitrogen.
In another execution mode of the inventive method, the flow of described hydrogen is 5000 ~ 8000sccm, and the time of passing into is 5 ~ 10 seconds, and the flow of wherein said nitrogen is 5000 ~ 8000sccm, and the time of passing into is 5 ~ 10 seconds.
In another execution mode of the inventive method, described method carries out dehydrogenation after being also included in deposited silicon nitride layer, and wherein said dehydrogenation is heated 30 ~ 50 minutes at 450 ~ 550 DEG C by described silicon nitride layer.
In another execution mode of the inventive method, described method is also included on described silicon oxide layer and deposits active semiconductor layer.
Method of the present invention is adopted to manufacture gate insulator; can available protecting Cu grid and active semiconductor layer; the silicon nitride layer that deposition is formed can effective isolation from oxygen; prevent Cu oxidized; and the silicon oxide layer that deposition is formed effectively can isolate hydrogen, prevent active semiconductor layer to be reduced, the gate insulator of this silicon nitride layer and silicon oxide layer stacked above one another effectively can stop the alkali metal ion in glass substrate in addition; strengthen anti-static electrictity release (ESD) ability and reduce leakage current, improving equivalent capacity.
Embodiment
According to specific embodiment, technical scheme of the present invention is described further below.Protection scope of the present invention is not limited to following examples, enumerates these examples and does not only limit the present invention in any way for exemplary purpose.
The invention provides a kind of method manufacturing gate insulator, comprise: adopt chemical vapour deposition technique, deposited silicon nitride layer and silicon oxide layer successively on grid, obtain the gate insulator of described silicon nitride layer and described silicon oxide layer stacked above one another, wherein said grid is Cu grid.
Silicon nitride layer of the present invention and silicon oxide layer are formed by chemical gaseous phase depositing process (CVD), can adopt Low Pressure Chemical Vapor Deposition, thermal vapor deposition method, plasma reinforced chemical vapour deposition method etc.
The present invention adopts high temperature CVD to carry out the deposition of silicon nitride layer and silicon oxide layer, and depositing temperature all preferably 420 ~ 450 DEG C, can remove hydrogen at this temperature effectively and the film quality of the silicon nitride layer deposited and silicon oxide layer is finer and close, and dielectric constant is higher.
With regard to forming the unstrpped gas of silicon nitride layer, as nitrogen source gas, NH can be used
3, NH
2h
2n, N
2deng, preferred NH
3; As silicon source gas, SiH can be used
4, Si
2h
6, SiCl
4, SiHCl
3, SiH
2cl
2, SiH
3cl
3, SiF
4deng, preferred SiH
4.SiH
4with NH
3flow-rate ratio be not less than 1:1, to compensate the loss of thermal effect deficiency, reduce the content of N-H key in the silicon nitride layer that deposits simultaneously, to promote dielectric constant, SiH
4with NH
3flow-rate ratio be preferably 1:1 to 1:3.SiH is adopted in practical operation
4mass fraction is the SiH of 5%
4with N
2mist.
With regard to forming the unstrpped gas of silicon oxide layer, as oxygen source gas, N can be used
2o, O
2, O
3deng, preferred N
2o; As silicon source gas, SiH can be used
4, Si
2h
6, SiCl
4, SiHCl
3, SiH
2cl
2, SiH
3cl
3, SiF
4deng, preferred SiH
4.SiH
4with N
2the flow-rate ratio of O is not less than 1:1, to compensate the loss of thermal effect deficiency, reduces the content of N-H key in the silicon nitride layer deposited simultaneously, to promote dielectric constant, and SiH
4with N
2the flow-rate ratio of O is preferably 1:1 to 1:3.SiH is adopted in practical operation
4mass fraction is the SiH of 5%
4with N
2mist.
The thickness of whole gate insulator should control within the specific limits, and blocked up gate insulator can increase the threshold voltage of thin-film transistor, and wherein the thickness of silicon nitride film is not less than 500
, to ensure enough dielectric property and to stop the ability of alkali metal ion, preferably 500 ~ 700
, the thickness of silicon oxide film is not higher than 1500
, preferably 1300 ~ 1500
.
In addition, before deposited silicon nitride layer, N can be passed into when power is 0 in vacuum chamber
2, the N passed into
2flow be 5000 ~ 8000sccm, the time of passing into is 5 ~ 10 seconds, passes into N
2cu grid thermally equivalent can be made and reduce the temperature in chamber, preventing from generating CuSi simultaneously
x.
Passing into N
2before, H can be passed into when power is 0 in vacuum chamber
2, the H passed into
2flow be 5000 ~ 8000sccm, the time of passing into is 5 ~ 10 seconds, passes into H
2oxidized Cu can be reduced, Cu grid thermally equivalent can be made and reduce the temperature in chamber simultaneously.
Passing into H
2and N
2afterwards, process need be vacuumized to vacuum chamber, and then carry out the deposition of silicon nitride layer.
In addition, after deposited silicon nitride layer, first can carry out to silicon nitride layer the deposition that dehydrogenation carries out silicon oxide layer again, the destruction of the diffusion couple silicon oxide layer of hydrogen during to reduce subsequent annealing process.Dehydrogenation is preferably silicon nitride layer heating 30 ~ 50 minutes at the temperature of 450 ~ 550 DEG C.Dehydrogenation is lower to vacuum level requirements, but needs at high temperature to keep the long period, therefore preferably carries out in the chamber different from deposition chambers, can reduce taking vacuum chamber.
Method of the present invention is also included on silicon oxide layer and deposits active semiconductor layer, and active semiconductor layer is the metal oxide or semiconductor that mobility is higher, such as IGZO and polysilicon, preferred IGZO.
Unless otherwise defined, term used herein is the implication that those skilled in the art understand usually.
By the following examples the present invention is described in further detail.
Embodiment
Embodiment 1
Cu grid is put into vacuum chamber, successively passes into H wherein when power is 0
2with N
2, wherein H
2flow be 5000sccm, the time of passing into is 10 seconds, N
2flow be 5000sccm, the time of passing into is 10 seconds, carries out afterwards vacuumizing process.
In vacuum chamber, using plasma strengthens chemical vapour deposition technique, utilizes OxfordInstrument Plasma80Plus system to be 500 at Cu gate surface deposit thickness
silicon nitride layer, unstrpped gas is SiH
4with N
2mist and NH
3, SiH
4with N
2the flow of mist is 400sccm, wherein SiH
4mass fraction be 5%, NH
3flow be 20sccm, concrete deposition process parameters is in table 1.
Table 1
Afterwards in another chamber, the silicon nitride layer that deposition is formed is heated 40 minutes, to carry out dehydrogenation at 500 DEG C.
In vacuum chamber, using plasma strengthens chemical vapour deposition technique, utilizes OxfordInstrument Plasma80Plus system deposit thickness on the silicon nitride layer of deposition formation to be 1500
silicon oxide layer, unstrpped gas is SiH
4with N
2mist and N
2o, SiH
4with N
2the flow of mist is 400sccm, wherein SiH
4mass fraction be 5%, N
2the flow of O is 20sccm, and concrete deposition process parameters is in table 2.
Table 2
The gate insulator of formed silicon nitride layer and silicon oxide layer stacked above one another deposits IGZO active semiconductor layer.
Embodiment 2
Cu grid is put into vacuum chamber, successively passes into H wherein when power is 0
2with N
2, wherein H
2flow be 6000sccm, the time of passing into is 8 seconds, N
2flow be 6000sccm, the time of passing into is 8 seconds, carries out afterwards vacuumizing process.
In vacuum chamber, using plasma strengthens chemical vapour deposition technique, utilizes OxfordInstrument Plasma80Plus system to be 600 at Cu gate surface deposit thickness
silicon nitride layer, unstrpped gas is SiH
4with N
2mist and NH
3, SiH
4with N
2the flow of mist is 400sccm, wherein SiH
4mass fraction be 5%, NH
3flow be 10sccm, concrete deposition process parameters is in table 3.
Table 3
Afterwards in another chamber, the silicon nitride layer that deposition is formed is heated 50 minutes, to carry out dehydrogenation at 450 DEG C.
In vacuum chamber, using plasma strengthens chemical vapour deposition technique, utilizes OxfordInstrument Plasma80Plus system deposit thickness on the silicon nitride layer of deposition formation to be 1400
silicon oxide layer, unstrpped gas is SiH
4with N
2mist and N
2o, SiH
4with N
2the flow of mist is 400sccm, wherein SiH
4mass fraction be 5%, N
2the flow of O is 10sccm, and concrete deposition process parameters is in table 4.
Table 4
The gate insulator of formed silicon nitride layer and silicon oxide layer stacked above one another deposits IGZO active semiconductor layer.
Embodiment 3
Cu grid is put into vacuum chamber, successively passes into H wherein when power is 0
2with N
2, wherein H
2flow be 8000sccm, the time of passing into is 5 seconds, N
2flow be 8000sccm, the time of passing into is 5 seconds, carries out afterwards vacuumizing process.
In vacuum chamber, using plasma strengthens chemical vapour deposition technique, utilizes OxfordInstrument Plasma80Plus system to be 700 at Cu gate surface deposit thickness
silicon nitride layer, unstrpped gas is SiH
4with N
2mist and NH
3, SiH
4with N
2the flow of mist is 600sccm, wherein SiH
4mass fraction be 5%, NH
3flow be 10sccm, concrete deposition process parameters is in table 5.
Table 5
Afterwards in another chamber, the silicon nitride layer that deposition is formed is heated 30 minutes, to carry out dehydrogenation at 550 DEG C.
In vacuum chamber, using plasma strengthens chemical vapour deposition technique, utilizes OxfordInstrument Plasma80Plus system deposit thickness on the silicon nitride layer of deposition formation to be 1300
silicon oxide layer, unstrpped gas is SiH
4with N
2mist and N
2o, SiH
4with N
2the flow of mist is 600sccm, wherein SiH
4mass fraction be 5%, N
2the flow of O is 10sccm, and concrete deposition process parameters is in table 6.
Table 6
The gate insulator of formed silicon nitride layer and silicon oxide layer stacked above one another deposits IGZO active semiconductor layer.
In sum; method of the present invention is adopted to manufacture gate insulator; can available protecting Cu grid and IGZO active semiconductor layer; the silicon nitride layer that deposition is formed can effective isolation from oxygen; prevent Cu oxidized; and the silicon oxide layer that deposition is formed effectively can isolate hydrogen; IGZO is prevented to be reduced; in addition the gate insulator of this silicon nitride layer and silicon oxide layer stacked above one another effectively can stop the alkali metal ion in glass substrate; strengthen anti-static electrictity release (ESD) ability and reduce leakage current, its equivalent capacity compares the silica gate insulator of same thickness by 1.77 × 10
-6(F/m
2) bring up to 2.02 × 10
- 6(F/m
2), increase about 15%.
Those skilled in the art it should be noted that execution mode described in the invention is only exemplary, can make other replacements various, changes and improvements within the scope of the invention.Thus, the invention is not restricted to above-mentioned execution mode, and be only defined by the claims.
Claims (10)
1. one kind manufactures the method for gate insulator, comprise: adopt chemical vapour deposition technique, deposited silicon nitride layer and silicon oxide layer successively on grid, obtain the gate insulator of described silicon nitride layer and described silicon oxide layer stacked above one another, wherein said grid is Cu grid.
2. method according to claim 1, the temperature wherein depositing described silicon nitride layer is 420 ~ 450 ° of C, and the temperature depositing described silicon oxide layer is 420 ~ 450 ° of C.
3. method according to claim 2, the unstrpped gas wherein depositing described silicon nitride layer is monosilane and ammonia, and the unstrpped gas depositing described silicon oxide layer is monosilane and nitrous oxide.
4. method according to claim 3, the flow-rate ratio of wherein said monosilane and described ammonia is 1:1 to 1:3.
5., according to the method for claim 3 or 4, the flow-rate ratio of wherein said monosilane and described nitrous oxide is 1:1 to 1:3.
6. method according to claim 5, passes into nitrogen before being also included in the described silicon nitride layer of deposition.
7. method according to claim 6, is also included in before passing into described nitrogen and passes into hydrogen.
8. method according to claim 7, the flow of wherein said hydrogen is 5000 ~ 8000sccm, and the time of passing into is 5 ~ 10 seconds, and the flow of wherein said nitrogen is 5000 ~ 8000sccm, and the time of passing into is 5 ~ 10 seconds.
9. method according to claim 7, carries out dehydrogenation after being also included in deposited silicon nitride layer, and wherein said dehydrogenation is heated 30 ~ 50 minutes at 450 ~ 550 DEG C by described silicon nitride layer.
10. method according to claim 9, is also included on described silicon oxide layer and deposits active semiconductor layer.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410050579.2A CN104851790A (en) | 2014-02-13 | 2014-02-13 | Method for manufacturing gate insulation layer |
| TW103115387A TWI567828B (en) | 2014-02-13 | 2014-04-29 | Method for manufacturing gate insulating layer |
| KR1020150010558A KR20150095563A (en) | 2014-02-13 | 2015-01-22 | A method for manufacturing gate insulation layer |
| JP2015010201A JP2015154078A (en) | 2014-02-13 | 2015-01-22 | Method of manufacturing gate insulation layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410050579.2A CN104851790A (en) | 2014-02-13 | 2014-02-13 | Method for manufacturing gate insulation layer |
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| Publication Number | Publication Date |
|---|---|
| CN104851790A true CN104851790A (en) | 2015-08-19 |
Family
ID=53851347
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| CN201410050579.2A Pending CN104851790A (en) | 2014-02-13 | 2014-02-13 | Method for manufacturing gate insulation layer |
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|---|---|
| JP (1) | JP2015154078A (en) |
| KR (1) | KR20150095563A (en) |
| CN (1) | CN104851790A (en) |
| TW (1) | TWI567828B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110797255A (en) * | 2019-10-14 | 2020-02-14 | 长江存储科技有限责任公司 | Thin film stack structure, three-dimensional memory and preparation method thereof |
| CN113299667A (en) * | 2021-05-10 | 2021-08-24 | Tcl华星光电技术有限公司 | MLED display panel and preparation method thereof |
| CN113451412A (en) * | 2020-04-01 | 2021-09-28 | 重庆康佳光电技术研究院有限公司 | TFT and manufacturing method thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101928463B1 (en) * | 2016-01-19 | 2018-12-12 | 에이피시스템 주식회사 | Apparatus for depositing passivation film and method for depositing passivation film |
| US10468491B1 (en) | 2018-07-03 | 2019-11-05 | International Business Machines Corporation | Low resistance contact for transistors |
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| US20110127524A1 (en) * | 2009-11-27 | 2011-06-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
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| JP5888501B2 (en) * | 2012-02-16 | 2016-03-22 | 三菱マテリアル株式会社 | Thin film wiring formation method |
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- 2014-02-13 CN CN201410050579.2A patent/CN104851790A/en active Pending
- 2014-04-29 TW TW103115387A patent/TWI567828B/en not_active IP Right Cessation
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- 2015-01-22 JP JP2015010201A patent/JP2015154078A/en active Pending
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| US20120262433A1 (en) * | 2008-06-04 | 2012-10-18 | Samsung Electronics Co., Ltd. | Organic light emitting diode display and method for manufacturing the same |
| WO2010098101A1 (en) * | 2009-02-27 | 2010-09-02 | 株式会社アルバック | Transistor, transistor manufacturing method, and manufacturing device thereof |
| US20110127524A1 (en) * | 2009-11-27 | 2011-06-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110797255A (en) * | 2019-10-14 | 2020-02-14 | 长江存储科技有限责任公司 | Thin film stack structure, three-dimensional memory and preparation method thereof |
| CN113451412A (en) * | 2020-04-01 | 2021-09-28 | 重庆康佳光电技术研究院有限公司 | TFT and manufacturing method thereof |
| CN113451412B (en) * | 2020-04-01 | 2023-08-29 | 重庆康佳光电科技有限公司 | TFT and manufacturing method thereof |
| CN113299667A (en) * | 2021-05-10 | 2021-08-24 | Tcl华星光电技术有限公司 | MLED display panel and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20150095563A (en) | 2015-08-21 |
| TWI567828B (en) | 2017-01-21 |
| TW201532149A (en) | 2015-08-16 |
| JP2015154078A (en) | 2015-08-24 |
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