CN104851451B - The memory cell for the static random-access memory reinforced based on resistance - Google Patents
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Abstract
The present invention proposes a kind of memory cell for the static random-access memory reinforced based on resistance, including latch cicuit and position selection circuit, latch cicuit is made up of two PMOSs P1 and P2, two NMOS tubes N1 and N2, the first resistance-capacitance network and the second resistance-capacitance network；Position selection circuit is made up of NMOS tube N5 and N6；Latch cicuit forms 4 storage points X1, X1B, X2, X2B；Relative to traditional 6T structure Storage Units, resistance-capacitance network is with the addition of, is not changing former read operation path, in the case of obvious complexity is not increased, to increase a small amount of area as cost, ensures that single-particle inversion does not occur for memory cell, ensures that data are correct.
Description
Technical field
The invention belongs to IC design and manufacturing technology, is related to static random-access memory, more particularly to one
The memory cell for the static random-access memory that kind is reinforced based on resistance, can be applied to military field, civil area and business
With space field, be particularly suitable for use in high-performance, high-density radioresistance application.
Background technology
Single-particle inversion is the important parameter of radiation hardened.Single-particle inversion or soft error, refer to data storage
Once nondestructive data transformation on position.Charged particle (such as cosmic ray or trap proton) injects semiconductor devices, leads to
Cross and interacted with semi-conducting material, soon lose energy.The energy of loss makes electronics jump to conduction band up from valence band.In
It is to have electronics in conduction band, hole is left in valence band, form electron hole pair, introduces nonequilibrium carrier.Without electric field
When, generation is spread, is compound by nonequilibrium carrier, is finally disappeared.When having electric field, nonequilibrium carrier (electron hole pair) will divide
Collected from by electrode, form transient current.Transient current can make node potential change, cause device logic state to overturn；Or
Propagated along signal transmission path, so as to disturb circuit normal function.For CMOS SRAM memory cell, the leakage of blanking tube
The space-charge region of area's reverse biased pn junction forms device single-particle inversion sensitive volume, and its electric field is enough to separate electron hole pair, and
Collected by electrode.
Typical memory cell has 6T structures now.Intersect as shown in figure 1,6T sram cells include two identicals
The phase inverter of connection, forms latch cicuit, i.e., the output of one phase inverter is connected to the input of another phase inverter.Latch cicuit
It is connected between power supply and ground potential.Each phase inverter respectively includes crystal pulling on NMOS pull-down transistor N1 or N2 and PMOS
Pipe P1 or P2.The output of phase inverter is two memory nodes Q and QB.It is another when one of memory node is pulled down to low-voltage
Individual memory node is pulled to high voltage, forms complementary pair.Paratope line is to BL and BLB respectively via a pair of transmission gate transistor N3
Memory node Q and QB are connected to N4.Transmission gate transistor N3 and N4 grid are connected to wordline WL.
Assuming that the state of the memory cell is " 1 ", i.e. Q is high voltage, and QB is low-voltage, the conducting of P1 and N2 pipes, N1 and P2
Pipe cut-off, the reverse biased pn junction space-charge region in N1 and P2 pipes drain region is exactly the single-particle inversion sensitive volume of device.Managed for N1, wink
State electric current reduces drain electrode (i.e. Q stores point) voltage, is coupled to P2 and N2 grid, makes the cut-off of N2 pipes, the conducting of P2 pipes, the leakage of N2 pipes
Pole (i.e. QB stores point) voltage rise, feeds back to the grid of P1, N1 pipe, ends P1 pipes, the conducting of N1 pipes, and state of memory cells is thorough
Bottom is changed into " 0 " from " 1 ".That is under radiation environment, single-particle inversion easily occurs for 6T structure Storage Units.Make storage content
It is interfered, the wrong value will remain to the memory cell and be written over next time.
In order to solve the list for after high energy particle (high energy proton, heavy ion) hits memory node, causing memory cell to occur
Particle flop phenomenon, generally use technique is reinforced and circuit design reinforces two kinds of means.Circuit design, which is reinforced, generally has three kinds of solutions
Certainly method.Method one is the memory node power-up perhaps resistance delay cell in memory cell, as shown in Figures 2 and 3.Powered
Particle is incident, N1 pipe drain potentials is dropped to low-voltage, but when P1 pipes still turn on, unstable during state of memory cells, deposits
In the competition of two processes.On the one hand, power supply is charged by P1 to the gate capacitance of N2 pipes, N1 pipes drain voltage is increased, is recovered
To original state；On the other hand, N1 pipes drain voltage reduces, and is coupled to another inverter gate, then feed back so that N1
Pipe turns on, the cut-off of P1 pipes, state of memory cells upset.By increasing RC delays, transient current makes the time that logic circuit is overturn
It is delayed by, and then causes having time to make this spike transient current cause node voltage change to return to initial value.This method
The shortcomings that be on chip needed for resistance capacitance value it is larger, resistance capacitance area is excessive, and the write time greatly increases.Method two
It is to add coupled capacitor between two memory nodes, as shown in Figure 4.The principle of this method is when one of node is by high energy
After particle is hit, produce transient current and cause the voltage of one of node that saltus step occurs, the voltage of another node is coupled
Unidirectional saltus step also occurs for the influence of electric capacity, so that memory cell can not be overturn.This method is similarly subjected to make
Make difficulty and the area limitation of electric capacity, and the limitation of write time.Method three is that storage information is carried out using more pipe units
Redundancy preserves, 12T DICE structures as shown in Figure 5.By the way that 4 phase inverters are end to end, wherein memory node respectively with it is preceding
One-level NMOS is connected with the PMOS of rear stage so that and positive and negative data storage is all preserved by redundancy, once some memory node is sent out
Raw single-particle inversion, its node voltage connected can only influence the memory node of previous stage or rear stage, be not affected that
One-level is recovered to the information of the memory node of saltus step.The shortcomings that this method is that transistor number is too many, and area is excessive.
The content of the invention
The purpose of the present invention is to propose to a kind of memory cell for the static random-access memory reinforced based on resistance, do not increase
Add complexity, only increasing a small amount of area can ensure that memory cell by not generating state upset during particle bombardment, ensures number
According to correct.
It is proposed by the present invention based on resistance reinforce static random-access memory memory cell, including latch cicuit and
Position selection circuit, latch cicuit is by two PMOSs P1 and P2, two NMOS tubes N1 and N2, the first resistance-capacitance network and the second capacitance-resistance
Network is formed；Position selection circuit is made up of NMOS tube N5 and N6；Latch cicuit forms 4 storage points X1, X1B, X2, X2B；
P1 drain electrode connection X1, its source electrode connection power supply, its grid connection X1B；The input of first resistance-capacitance network and defeated
Go out end to be connected with X1 and X2 respectively；N1 drain electrode connection X2, its source ground, its grid connection X2B；
P2 drain electrode connection X1B, its source electrode connection power supply, its grid connection X1；The input of second resistance-capacitance network and defeated
Go out end to be connected with X1B and X2B respectively；N2 drain electrode connection X2B, its source ground, its grid meet X2；
N5 drain electrode meets X2 or X1, N6 drain electrode correspond to and meets X2B or X1B；N5 source electrode meets bit line BL；N6 source electrode connects complementation
Bit line BLB；N5 and N6 grid links together, and is connected on wordline WL.
First resistance-capacitance network is made up of R1 and C1, and second resistance-capacitance network is made up of R2 and C2；
R1 both ends are connected with X1, X2 respectively；C1 one end is connected with X1, other end ground connection；
R2 both ends are connected with X1B, X2B respectively；C2 one end is connected with X1B, other end ground connection.
The composition of resistance-capacitance network can also use following scheme：First resistance-capacitance network serves as capacitance-resistance by being always on
PMOS P3 and NMOS tube the composition N3 compositions of isolating points, second resistance-capacitance network serve as capacitance-resistance isolating points by being always on
PMOS P4 and NMOS tube composition N4 composition；
Storage point X3 is formed between P3 and N3；Storage point X3B is formed between P4 and N4；
P3 source electrode connection X1, its connection X3 that drains, its grounded-grid, its substrate connects power supply, to keep being always on；N3
Drain electrode connection X3, its source electrode connection X2, its grid connects power supply, its Substrate ground, to keep being always on；
P4 source electrode connection X1B, its connection X3B that drains, its grounded-grid, its substrate connects power supply, to keep being always on；
N3 drain electrode connection X3B, its source electrode connection X2B, its grid connect power supply, its Substrate ground, to keep being always on.
The present invention with the addition of resistance-capacitance network in 6T structure Storage Units, and circuit area overhead is small, anti-single particle upset property
Can be excellent, and compatible common processes.
Brief description of the drawings
Fig. 1 is traditional 6TSRAM memory cell；
Fig. 2 is the memory cell that memory node adds resistance capacitance；
Fig. 3 is the memory cell that resistance capacitance is replaced with mos electric capacity；
Fig. 4 is the memory cell that memory node adds coupled capacitor；
Fig. 5 is DICE structure Storage Units；
Fig. 6 is the circuit diagram of first embodiment of the invention；
Fig. 7 is the circuit diagram of second embodiment of the invention；
Fig. 8 is the circuit diagram of third embodiment of the invention.
Embodiment
For the object, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in more detail.
Embodiment one
As shown in fig. 6, the memory cell of the static random-access memory reinforced based on resistance of the present invention, including latch
Circuit and position selection circuit, latch cicuit is by two PMOSs P1 and P2, two NMOS tubes N1 and N2, the first resistance-capacitance network and
Two resistance-capacitance networks are formed, and first resistance-capacitance network is made up of R1 and C1, and second resistance-capacitance network is made up of R2 and C2；Position choosing
Circuit is selected to be made up of NMOS tube N5 and N6；Latch cicuit forms 4 storage points X1, X1B, X2, X2B.
P1 drain electrode connection X1, its source electrode connection power supply, its grid connection X1B；R1 both ends are connected with X1, X2 respectively；
C1 one end is connected with X1, other end ground connection；N1 drain electrode connection X2, its source ground, its grid connection X2B.
P2 drain electrode connection X1B, its source electrode connection power supply, its grid connection X1；R2 both ends connect with X1B, X2B respectively
Connect；C2 one end is connected with X1B, other end ground connection；N2 drain electrode connection X2B, its source ground, its grid meet X2.
N5 drain electrode meets X2, and N6 drain electrodes are corresponding to meet X2B；N5 source electrode meets bit line BL；N6 source electrode meets paratope line BLB；
N5 and N6 grid links together, and is connected on wordline WL.
If high energy particle collects electric charge by the memory cell, metal-oxide-semiconductor sensitive nodes, form transient current and cause voltage to become
Change, then on the one hand the change causes the corresponding metal-oxide-semiconductor shut-off in complementary inverter, on the other hand, the change is delayed by RC
Afterwards, being coupled to the grid of complementary inverter just can overturn phase inverter state.Assuming that memory storage high level in Fig. 6, i.e. X1
=" 1 ", X2=" 1 ", and X1B=" 0 ", X2B=" 0 ", then the sensitive nodes of the unit are the drain electrode of N1 pipes, i.e., at X2, and P1
Pipe drains, i.e., at X1B.Particle can produce the change that transient current causes voltage when only bombarding at X2 or at X1B.If particle
At X2, then X2 is changed into " 0 " from " 1 ", the N2 pipes that shut-off is opened originally so that X2B " 0 " floating；On the other hand, at X2
Voltage change, RC need to be passed through and be delayed, open the P2 pipes closed originally so that X1B complete switches off P1 pipes by " 0 " change " 1 " so that
Memory cell is overturn.If RC delays are enough long, before P2 pipes are opened, it is " 1 " that P1 pipes having time, which maintains X1, prevents unit from turning over
Turn.Simultaneously because position selection signal is connected to X2 and X2B, the read operation delay of unit is unaffected.
Embodiment two
The embodiment is that the circuit design of the first resistance-capacitance network and the second resistance-capacitance network is different from the difference of embodiment one,
Other parts are identical with embodiment one.
As shown in fig. 7, first resistance-capacitance network serves as the PMOS P3 and NMOS of capacitance-resistance isolating points by being always on
Pipe composition N3 compositions, second resistance-capacitance network are formed by being always on serving as the PMOS P4 of capacitance-resistance isolating points and NMOS tube
N4 is formed；P3, P4, N3, the N4 being always on preserve to memory node information redundancy, form X1, X1B, X2, X2B, X3, X3B six
Individual storage point.
P3 source electrode connection X1, its connection X3 that drains, its grounded-grid, its substrate connects power supply, to keep being always on；N3
Drain electrode connection X3, its source electrode connection X2, its grid connects power supply, its Substrate ground, to keep being always on.
P4 source electrode connection X1B, its connection X3B that drains, its grounded-grid, its substrate connects power supply, to keep being always on；
N3 drain electrode connection X3B, its source electrode connection X2B, its grid connect power supply, its Substrate ground, to keep being always on.
Position selection circuit N5 and N6 connect X2 and X2B storage points respectively.
If saltus step occurs for the voltage of a memory node, two transfer tubes being always on act as resistance and electric capacity is made
With to skip signal progress RC delays so that pull-up PMOS or pull-down NMOS having time make this skip signal recover initial
Value.
Charge-trapping sensitizing range is the reverse-biased region for causing to have highfield of PN junction in metal-oxide-semiconductor, when these regions of particle bombardment
When, the electron hole pair ionized out is separated under electric field action, is collected by electrode, forms transient current.Such as Fig. 7 structures, if
Memory cell stores low level, i.e. X1=" 0 ", X3=" 0 ", X2=" 0 ", X1B=" 1 ", X3B=" 1 ", X2B=" 1 ".P3's
Source body PN junction is reverse-biased, and leakage body PN junction is reverse-biased, and P1 leakage body PN junction is reverse-biased.Therefore during particle bombardment device, only beat in P3 source
Transient current can be produced when pole X1, P3 drain electrode X3 or P1 drain electrode X1.Similarly, transient state can be produced in X3 and X2B by only beating
Electric current.That is the sensitive nodes of the structure are X1 (being " 1 " by " 0 " upset), X3 (being " 1 " by " 0 " upset), X3B (by " 1 " upset
For " 0 "), X2B points (by " 1 " upset be " 0 ").
In above-mentioned analysis, sensitive spot has 4, X1 (be " 1 " by " 0 " upset), X3 (it is " 1 " to be overturn by " 0 "), X3B (by
" 1 " upset be " 0 "), X2B points (by " 1 " overturn be " 0 ").Wherein X1 points are needed by two by " 0 " upset for the change of " 1 "
The RC delays of resistance could cause N2 to open, and X3 is only needed to be switched on by a RC delay by " 0 " upset for the change of " 1 "
N1；Wherein X2B points need the RC delays by two resistance that P1 could be caused to open by " 1 " upset for the change of " 0 ", and X3B
Only need to be delayed by a RC for the change of " 0 " by " 1 " upset and be switched on P1；Therefore X3 by " 0 " upset for " 1 " change or
Changes more " danger " of the X3B by " 1 " upset for " 0 ".It is " 1 " when X3 is overturn by " 0 ", due to the RC delays that N3 is brought, the unit
This time can be utilized initial value will to be reverted to by the skip signal of " 0 " to " 1 " at X3 by always on N1；Or work as
X3B is " 0 " by " 1 " upset, and due to the RC delays that P4 is brought, the unit can utilize this time will by always on P2
Initial value is reverted to by the skip signal of " 1 " to " 0 " at X3B.
Resistance-capacitance network is served as using metal-oxide-semiconductor in unit, compatible universal MOS techniques, is simple to manufacture and is easily achieved.
Embodiment three
The embodiment is that the storage point that a selection circuit is connected is different from the difference of embodiment two, other parts with
Embodiment two is identical.
As shown in figure 8, N5 drain electrode meets X1, N6 drain electrodes are corresponding to meet X1B；N5 source electrode meets bit line BL；N6 source electrode connects mutually
Cover line BLB；N5 and N6 grid links together, and is connected on wordline WL.
Three embodiments of the present invention can make quiet in the case where not increasing obvious complexity, a small amount of area of increase
Single-particle inversion does not occur under radiation environment for the memory cell of state random access memory, compatible universal CMOS technology, easily realizes.
Particular embodiments described above, the purpose of the present invention, technical scheme and beneficial effect are carried out further in detail
Describe in detail it is bright, should be understood that the foregoing is only the present invention specific embodiment, be not intended to limit the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements done etc., it should be included in the guarantor of the present invention
Within the scope of shield.
Claims (2)
1. the memory cell for the static random-access memory reinforced based on resistance, including latch cicuit and position selection circuit, its
It is characterised by, latch cicuit is by two PMOSs P1 and P2, two NMOS tubes N1 and N2, the first resistance-capacitance network and the second capacitance-resistance net
Network is formed；Position selection circuit is made up of NMOS tube N5 and N6；Latch cicuit forms 4 storage points X1, X1B, X2, X2B；
P1 drain electrode connection X1, its source electrode connection power supply, its grid connection X1B；The input and output end of first resistance-capacitance network
It is connected respectively with X1 and X2；N1 drain electrode connection X2, its source ground, its grid connection X2B；
P2 drain electrode connection X1B, its source electrode connection power supply, its grid connection X1；The input and output end of second resistance-capacitance network
It is connected respectively with X1B and X2B；N2 drain electrode connection X2B, its source ground, its grid meet X2；
N5 drain electrode meets X2 or X1, N6 drain electrode correspond to and meets X2B or X1B；N5 source electrode meets bit line BL；N6 source electrode connects paratope line
BLB；N5 and N6 grid links together, and is connected on wordline WL；
First resistance-capacitance network is made up of R1 and C1, and second resistance-capacitance network is made up of R2 and C2；
R1 both ends are connected with X1, X2 respectively；C1 one end is connected with X1, other end ground connection；
R2 both ends are connected with X1B, X2B respectively；C2 one end is connected with X1B, other end ground connection.
2. the memory cell for the static random-access memory reinforced as claimed in claim 1 based on resistance, it is characterised in that
First resistance-capacitance network is formed N3 and formed by being always on to be served as the PMOS P3 of capacitance-resistance isolating points and NMOS tube, and described
Two resistance-capacitance networks are formed N4 and formed by being always on to be served as the PMOS P4 of capacitance-resistance isolating points and NMOS tube；
Storage point X3 is formed between P3 and N3；Storage point X3B is formed between P4 and N4；
P3 source electrode connection X1, its connection X3 that drains, its grounded-grid, its substrate connects power supply, to keep being always on；N3 leakage
Pole connects X3, its source electrode connection X2, and its grid connects power supply, its Substrate ground, to keep being always on；
P4 source electrode connection X1B, its connection X3B that drains, its grounded-grid, its substrate connects power supply, to keep being always on；N3's
Drain electrode connection X3B, its source electrode connection X2B, its grid connect power supply, its Substrate ground, to keep being always on.
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