CN104835785A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN104835785A CN104835785A CN201410045886.1A CN201410045886A CN104835785A CN 104835785 A CN104835785 A CN 104835785A CN 201410045886 A CN201410045886 A CN 201410045886A CN 104835785 A CN104835785 A CN 104835785A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
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- 239000010410 layer Substances 0.000 claims description 100
- 238000000034 method Methods 0.000 claims description 67
- 238000005468 ion implantation Methods 0.000 claims description 22
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 21
- 230000008569 process Effects 0.000 claims description 19
- 238000002347 injection Methods 0.000 claims description 18
- 239000007924 injection Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 9
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 6
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
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- 229910052799 carbon Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
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- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 2
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
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- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- JIMUOUDLWPNFAY-UHFFFAOYSA-N [Si]=O.[Hf].[N] Chemical compound [Si]=O.[Hf].[N] JIMUOUDLWPNFAY-UHFFFAOYSA-N 0.000 description 1
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- 238000002513 implantation Methods 0.000 description 1
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- 238000002955 isolation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
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- 229910052757 nitrogen Inorganic materials 0.000 description 1
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- 238000007254 oxidation reaction Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
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- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention provides a semiconductor device and a manufacturing method thereof, relating to the semiconductor technical field. The manufacturing method comprises the step of forming first stack fault dislocation located in a light dope source/ drain region, second stack fault dislocation located in a source electrode and a drain electrode, and a lifting stress layer located above the source electrode and the drain electrode, and higher than a semiconductor substrate. The first stack fault dislocation, the second stack fault dislocation and the lifting stress layer can apply tensile stress on channels of an NMOS device and improve performances of the semiconductor device; in addition, the formed stress layer is higher than the semiconductor substrate, which can avoid damaging the source electrode and the drain electrode, and increasing the yield per unit time. The semiconductor device according to the invention possesses better performance.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor device and manufacture method thereof.
Background technology
In technical field of semiconductors, because the size of cmos device constantly reduces along with the reduction of process node, the performance improvement of device becomes necessary.The method much improving carrier mobility is there is in prior art, but strained silicon technology has attracted increasing concern and has been used gradually, such as: by the performance of germanium silicon (SiGe) process improving PMOS, the performance of NMOS is improved by carbon silicon (SiC) technique.
It is reported, carbon silicon (SiC) stressor layers of the U-shaped lifting of depression can improve the performance of nmos device, and performance is risen to 32% from 6%.
In addition, dislocation (Stack fault dislocation) technology can produce tensile stress, and can improve the performance of NMOS.
There is a kind of manufacture method of semiconductor device in prior art, improving the performance of nmos device by adopting dislocation technology with the carbon silicon stressor layers of the lifting being positioned at source electrode and drain electrode.In the method, form the carbon silicon stressor layers of lifting by epitaxy technique, concrete grammar is: the depression first forming the carbon silicon stressor layers being used for accommodating lifting in source electrode and drain electrode, then at the epitaxial growth carbon silicon that caves in form the stressor layers of lifting.Owing to needing first to form depression again in the stressor layers of epitaxial growth carbon silicon thus formation lifting that caves in, at least there is following problem in the method: the process that (1) forms depression can damage the dislocation formed, and causes the stress of dislocation to be released; (2) process forming depression can cause certain destruction to source electrode and drain electrode; (3) first form the epitaxial growth carbon silicon again that caves in and can cause the overlong time of epitaxial growth technology needs, cause the output of the semiconductor device in the unit interval to reduce.
Visible, in order to solve the aforementioned problems in the prior, need to propose a kind of new semiconductor device structure and manufacture method thereof.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of semiconductor device and manufacture method thereof, the adverse effect that the technique can improving the carbon silicon stressor layers forming lifting is brought, improve the carrier mobility of semiconductor device and then improve the performance of device.
The embodiment of the present invention one provides a kind of manufacture method of semiconductor device, and described method comprises:
Step S101: provide Semiconductor substrate, forms dummy gate structure and the skew sidewall being positioned at described dummy gate structure both sides on the semiconductor substrate;
Step S102: form light dope source/drain region by light dope ion implantation in described Semiconductor substrate and be positioned at the first dislocation of described light dope source/drain region;
Step S103: form major side wall in the both sides of described skew sidewall, is infused in described Semiconductor substrate the second dislocation forming source electrode and drain electrode and be positioned at described source electrode and described drain electrode by heavy doping ion;
Step S104: remove described major side wall, is formed and to be positioned at above described source electrode and described drain electrode and the stressor layers of lifting higher than described Semiconductor substrate.
Wherein, the degree of depth of described first dislocation in described Semiconductor substrate is less than described second dislocation, and described first dislocation is than the channel region of described second dislocation closer to device.
Wherein, described stressor layers comprises carbon silicon layer.
Wherein, described stressor layers comprises phosphorus or the in-situ doped carbon silicon layer of arsenic.
Alternatively, in described step S104, the step forming described stressor layers comprises:
Form one deck stress material layer on the semiconductor substrate;
The part outside described source electrode and described drain electrode region is positioned at, to form described stressor layers by the described stress material layer of etching removal.
Alternatively, in described step S102, before the step of carrying out light dope ion implantation, also comprise the step implementing pre-amorphous injection; And/or, after the step of carrying out light dope ion implantation, also comprise the step of carrying out annealing process.
Alternatively, in described step S103, before the step of carrying out heavy doping ion injection, also comprise the step implementing pre-amorphous injection; And/or, after the step of carrying out heavy doping ion injection, also comprise the step of carrying out annealing process.
Wherein, also comprise the steps: after described step S104
Step S105: the interlayer dielectric layer forming contact hole etching barrier layer and be positioned on described contact hole etching barrier layer;
Step S106: remove described dummy gate structure, and form metal gate structure in the position that described dummy gate structure is original;
Step S107: form the contact hole be positioned at above described source electrode and described drain electrode.
The invention process two provides a kind of semiconductor device, comprise: Semiconductor substrate, be positioned at the grid structure in described Semiconductor substrate and be positioned at source electrode and the drain electrode of described Semiconductor substrate, also comprise the first dislocation and the second dislocation that are positioned at described source electrode and described drain electrode, and to be positioned at above described source electrode and described drain electrode and the stressor layers of lifting higher than described Semiconductor substrate.
Alternatively, the degree of depth of described first dislocation in described Semiconductor substrate is less than described second dislocation, and described first dislocation is than the channel region of described second dislocation closer to device.
Wherein, described stressor layers comprises carbon silicon layer.
Wherein, described stressor layers comprises phosphorus or the in-situ doped carbon silicon layer of arsenic.
The manufacture method of semiconductor device of the present invention, by forming the first dislocation being positioned at light dope source/drain region, the second dislocation being positioned at source electrode and drain electrode and being positioned at source electrode and the stressor layers of lifting above drain and higher than Semiconductor substrate, tensile stress can be applied to the raceway groove of nmos device, improve the performance of semiconductor device.Further, the technique forming stressor layers is more reasonable relative to prior art, not only can avoid damaging source electrode and drain electrode, and can improve the output of the semiconductor device in the unit interval.Semiconductor device of the present invention, can adopt said method to obtain, have better performance.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A to 1F is the schematic cross sectional views of the figure that the correlation step of the manufacture method of a kind of semiconductor device of the embodiment of the present invention one is formed;
Fig. 2 is a kind of indicative flowchart of the manufacture method of a kind of semiconductor device of the embodiment of the present invention one;
Fig. 3 is the schematic cross sectional views of the structure of a kind of semiconductor device of the embodiment of the present invention two.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should be understood that, the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.Although it should be understood that and term first, second, third, etc. can be used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms be only used for differentiation element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., here can be used thus the relation of the element of shown in description figure or feature and other element or feature for convenience of description.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprises the different orientation of the device in using and operating.Such as, if the device upset in accompanying drawing, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be comprised.Device can additionally orientation (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to comprise plural form, unless context is known point out other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.
Here with reference to the cross-sectional view as the schematic diagram of desirable embodiment of the present invention (and intermediate structure), inventive embodiment is described.Like this, it is expected to the change from shown shape because such as manufacturing technology and/or tolerance cause.Therefore, embodiments of the invention should not be confined to the given shape in district shown here, but comprise owing to such as manufacturing the form variations caused.Such as, the injection region being shown as rectangle has round or bending features and/or implantation concentration gradient usually at its edge, instead of the binary from injection region to non-injection regions changes.Equally, by inject formed disposal area this disposal area and injection can be caused to carry out time process surface between district some inject.Therefore, the district shown in figure is in fact schematic, and their shape is not intended the true form in the district of display device and is not intended to limit scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, to explain the technical scheme of the present invention's proposition.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Embodiment one
Below, the detailed step of a manufacture method illustrative methods of the semiconductor device that the embodiment of the present invention proposes is described with reference to Figure 1A-Fig. 1 F and Fig. 2.Wherein, Figure 1A to 1F is the schematic cross sectional views of the figure of the correlation step formation of the manufacture method of a kind of semiconductor device of the embodiment of the present invention; Fig. 2 is a kind of indicative flowchart of the manufacture method of a kind of semiconductor device of the embodiment of the present invention.
The manufacture method of the semiconductor device of the embodiment of the present invention, mainly for the manufacture of nmos device or the semiconductor device comprising nmos device, generally comprises following steps:
Steps A 1: provide Semiconductor substrate 100, forms dummy gate structure 101 and the skew sidewall 102 being positioned at these dummy gate structure 101 both sides, as shown in Figure 1A on a semiconductor substrate 100.
Wherein, dummy gate structure 101 generally includes dummy grid dielectric layer and the dummy grid (in order to briefly, the two not illustrated respectively in Fig. 1) be located thereon.Exemplarily, the material of dummy grid dielectric layer is oxide, the material polysilicon of dummy grid.Skew sidewall 102 can be single layer structure or sandwich construction.
In the present embodiment, shallow trench isolation can also be comprised from (STI) in Semiconductor substrate 100.
Steps A 2: form light dope source/drain region 103 by light dope ion implantation in Semiconductor substrate 100 and be positioned at the first dislocation 104 of light dope source/drain region 103, as shown in Figure 1B.
For NMOS, the Doped ions of light dope ion implantation can be phosphonium ion or arsenic ion etc.
Exemplarily, when the Doped ions of light dope ion implantation is phosphonium ion, the energy range of ion implantation is 1-20keV, and the dosage of ion implantation is 1.0 × e
14-1.0 × e
15cm
-2; When the Doped ions of light dope ion implantation is arsenic ion, the energy range of ion implantation is 2-35keV, and the dosage of ion implantation is 1.0 × e
14-1.0 × e
15cm
-2.
In the present embodiment, before carrying out light dope ion implantation or simultaneously, alternatively, pre-amorphous injection (PAI) is implemented, to reduce short-channel effect.The injection ion of pre-amorphous injection comprises III race and V race's ion such as germanium, carbon.
Alternatively, after the step implementing light dope ion implantation, bag-like region ion implantation can also be performed, to form the bag-like region wrapped light dope source/drain region 103 in Semiconductor substrate 100, for adjusting threshold voltage and the break-through of source/drain region preventing follow-up formation, in order to simplify, not shown bag-like region in diagram.
In the present embodiment, the step of carrying out annealing process can also be comprised after the step of light dope ion implantation and/or the step of execution bag-like region ion implantation.Performing the object of annealing process is activate the Doped ions in light dope source/drain region and bag-like region, and eliminates the defect that above-mentioned ion implantation produces.This annealing process, can be rapid thermal annealing or other annealing way, not limit at this.
Steps A 3: form major side wall 105 in the both sides of skew sidewall 102; Be infused in Semiconductor substrate 100 by heavy doping ion and form source electrode 1061 and drain electrode 1062 and the second dislocation 107 being positioned at source electrode 1061 and drain electrode 1062, as shown in Figure 1 C,
Wherein, the processing step forming major side wall 105 comprises: form the major side wall material layer covering dummy gate structure 101 and skew sidewall 102 on a semiconductor substrate 100, its constituent material preferred nitrogen SiClx; Sidewall etch (blanket etch) technique is adopted to etch this major side wall material layer to form major side wall 105.
Then, source electrode 1061 and drain electrode 1062 and the second dislocation 107 being positioned at source electrode 1061 and drain electrode 1062 is formed by heavy doping.
Before enforcement heavy doping ion is injected or simultaneously, alternatively, pre-amorphous injection (PAI) is implemented to reduce short-channel effect.The injection ion of pre-amorphous injection comprises III race and V race's ion such as germanium, carbon.
In the present embodiment, after the step that heavy doping ion is injected, the step of carrying out annealing process can also be comprised.
In the present embodiment, the first dislocation 104 and the second dislocation 107 all can apply tensile stress to raceway groove, improve carrier mobility.Wherein, the location comparison of the first dislocation 104 compared with the second dislocation 107 in Semiconductor substrate is shallow, and closer to the channel region of device; But the second dislocation 107 is positioned at source electrode and drains and be in darker position, larger stress can be produced to raceway groove.Wherein, in the process of ion implantation, form dislocation is that this area is easy to realize, and generally needs the appearance avoiding dislocation in prior art, and the present embodiment can improve device performance to raceway groove stress application by suitably arranging dislocation.
Steps A 4: remove major side wall 105, is formed and to be positioned at above source electrode 1061 and drain electrode 1062 and higher than the stressor layers 108 of the lifting of Semiconductor substrate 100, as shown in figure ip.
Wherein, in the present embodiment, stressor layers 108, higher than Semiconductor substrate 100, refers to stressor layers 108 on the whole all higher than the upper surface of Semiconductor substrate 100.That is, in the present embodiment when forming stressor layers 108, in Semiconductor substrate 100, do not form groove.
Exemplarily, the method forming stressor layers 108 comprises: directly form one deck stress material layer on a semiconductor substrate 100; This stress material layer of etching removal is positioned at the part outside source electrode 1061 and drain electrode 1062 regions, to form stressor layers 108.
The size of the stress that stressor layers 108 has is relevant with the process conditions of the material that formation stressor layers 108 adopts and depositing operation, is not specifically limited at this.
Exemplarily, stressor layers 108 is carbon silicon (SiC) layer.The method forming stressor layers 108 is epitaxial growth method.Further, this stressor layers 108 is in-situ doped carbon silicon (SiC) layer of phosphorus or arsenic, to improve the tensile stress to raceway groove further.
In the present embodiment, the process forming stressor layers 108 does not need first in source electrode and drain electrode, to form groove as prior art, therefore hinge structure, there is following advantage: (1) can be avoided damaging dislocation (such as the first dislocation 104 and the second dislocation 107), and then avoids causing dislocation to be released the stress that raceway groove applies; (2) destruction to source electrode and drain electrode can be reduced, improve device performance; (3) process time of the step forming stressor layers 108 can be shortened, and then improve the output of the semiconductor device in the unit interval.
Steps A 5: the interlayer dielectric layer (ILD) 109 forming contact hole etching barrier layer (not shown) and be positioned on contact hole etching barrier layer; Then, remove dummy gate structure 101, the position original in described dummy gate structure forms metal gate structure 110.The figure formed, as referring to figure 1e.
Wherein, the method for contact hole etching barrier layer (CESL) and interlayer dielectric layer 109 is formed, the various suitable technique that those skilled in the art can be adopted to have the knack of, such as chemical vapor deposition method.The material preferential oxidation silicon of interlayer dielectric layer 109.
Wherein, metal gate structure 110 generally comprises high k dielectric layer and the metal gates be located thereon.The material of high k dielectric layer comprises hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc., particularly preferably is hafnium oxide, zirconia or aluminium oxide.It should be noted that, can also form boundary layer in the below of high k dielectric layer, its constituent material comprises Si oxide (SiO
x), the effect forming boundary layer improves the interfacial characteristics between high k dielectric layer and Semiconductor substrate; Cover layer can also be formed between high k dielectric layer and metal gates, its constituent material comprises titanium nitride or tantalum nitride, forming tectal effect is prevent the metal material in metal gate structure to the diffusion of high k dielectric layer, in order to simplify, is omitted in diagram.The technology forming above-mentioned each layer is had the knack of by those skilled in the art, does not repeat them here.
Steps A 6: form the contact hole 111 being positioned at source electrode and drain electrode top, as shown in fig. 1f.
Wherein, the technique forming contact hole 111 is conventionally known to one of skill in the art, is no longer repeated at this.
So far, complete the processing step that method is according to an exemplary embodiment of the present invention implemented, next, the making of whole semiconductor device can be completed by subsequent technique, comprise: the step etc. of the step of filling metal (being generally tungsten) in contact hole 111, the step forming multiple interconnecting metal layer, formation metal pad, does not repeat them here.
The manufacture method of the semiconductor device of the present embodiment, by forming the first dislocation 104 being positioned at light dope source/drain region 103, the second dislocation being positioned at source electrode 1061 and drain electrode 1062 and being positioned at source electrode 1061 and draining above 1062 and higher than the stressor layers 108 of the lifting of Semiconductor substrate 100, tensile stress can be applied to the raceway groove of nmos device, improve the performance of semiconductor device.Further, the technique forming stressor layers 108 is more reasonable relative to prior art, not only can avoid damaging source electrode and drain electrode and the first dislocation and the second dislocation, and can improve the output of the semiconductor device in the unit interval.
Fig. 2 shows a kind of indicative flowchart of the manufacture method of a kind of semiconductor device that the embodiment of the present invention proposes, for schematically illustrating the typical process of this manufacture method.Specifically comprise:
Step S101: provide Semiconductor substrate, forms dummy gate structure and the skew sidewall being positioned at described dummy gate structure both sides on the semiconductor substrate;
Step S102: form light dope source/drain region by light dope ion implantation in described Semiconductor substrate;
Step S103: form major side wall in the both sides of described skew sidewall, be infused in described Semiconductor substrate by heavy doping ion and form source electrode and drain electrode;
Step S104: remove described major side wall, is formed and to be positioned at above described source electrode and described drain electrode and the stressor layers of lifting higher than described Semiconductor substrate.
Embodiment two
Below, the structure of the semiconductor device that the embodiment of the present invention proposes is described with reference to Fig. 3.Wherein, Fig. 3 is the schematic cross sectional views of the structure of a kind of semiconductor device of the embodiment of the present invention.
As shown in Figure 3, the semiconductor device of the embodiment of the present invention comprises: Semiconductor substrate 100, be positioned at the grid structure 110 in Semiconductor substrate 100 and be positioned at source electrode 1061 and the drain electrode 1062 of Semiconductor substrate 100, also comprise to be positioned at above source electrode 1061 and drain electrode 1062 and higher than the lifting of Semiconductor substrate 100 stressor layers 108, be positioned at the first dislocation 104 of light dope source/drain region 103 and be positioned at the second dislocation 107 of described source electrode and described drain electrode.
Wherein, the degree of depth of described first dislocation 104 in described Semiconductor substrate 100 is less than described second dislocation 107, and, described first dislocation 104 than the channel region of described second dislocation 107 closer to device, as shown in Figure 3.
In the present embodiment, stressor layers 108 and the first dislocation 104 and the second dislocation 107 can apply tensile stress to raceway groove, improve the mobility of charge carrier.
Wherein, described stressor layers 108 is generally carbon silicon layer.Further, stressor layers 108 is the in-situ doped carbon silicon layer of phosphorus or arsenic, to improve the tensile stress applied raceway groove.
The semiconductor device of the present embodiment, can also comprise the assemblies such as interlayer dielectric layer 109, contact hole 111 and skew sidewall 102, not limit at this.
The semiconductor device of the present embodiment can be nmos device, also can be the semiconductor device comprising nmos device.
The semiconductor device of the present embodiment, can adopt the method described in embodiment one to obtain, and about the concrete structure of the semiconductor device of the present embodiment, with reference to embodiment one, can repeat no more herein.
The semiconductor device of the present embodiment, comprise the first dislocation 104 being positioned at light dope source/drain region 103, the second dislocation 107 being positioned at source electrode and drain electrode and to be positioned at above source electrode 1061 and drain electrode 1062 and higher than the stressor layers 108 of the lifting of Semiconductor substrate 100, tensile stress can be applied to the raceway groove of nmos device, improve the performance of semiconductor device.Further, the technique forming stressor layers 108 can not damage source electrode and drain electrode.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (12)
1. a manufacture method for semiconductor device, is characterized in that, described method comprises:
Step S101: provide Semiconductor substrate, forms dummy gate structure and the skew sidewall being positioned at described dummy gate structure both sides on the semiconductor substrate;
Step S102: form light dope source/drain region by light dope ion implantation in described Semiconductor substrate and be positioned at the first dislocation of described light dope source/drain region;
Step S103: form major side wall in the both sides of described skew sidewall, is infused in described Semiconductor substrate the second dislocation forming source electrode and drain electrode and be positioned at described source electrode and described drain electrode by heavy doping ion;
Step S104: remove described major side wall, is formed and to be positioned at above described source electrode and described drain electrode and the stressor layers of lifting higher than described Semiconductor substrate.
2. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, the degree of depth of described first dislocation in described Semiconductor substrate is less than described second dislocation, and described first dislocation is than the channel region of described second dislocation closer to device.
3. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that,
In described step S102, before the step of carrying out light dope ion implantation, also comprise the step implementing pre-amorphous injection; And/or, after the step of carrying out light dope ion implantation, also comprise the step of carrying out annealing process.
4. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that,
In described step S103, before the step of carrying out heavy doping ion injection, also comprise the step implementing pre-amorphous injection; And/or, after the step of carrying out heavy doping ion injection, also comprise the step of carrying out annealing process.
5. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, described stressor layers comprises carbon silicon layer.
6. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, described stressor layers comprises phosphorus or the in-situ doped carbon silicon layer of arsenic.
7. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, in described step S104, the step forming described stressor layers comprises:
Directly form one deck stress material layer on the semiconductor substrate;
The part outside described source electrode and described drain electrode region is positioned at, to form described stressor layers by the described stress material layer of etching removal.
8. the manufacture method of the semiconductor device as described in any one of claim 1 to 7, is characterized in that, also comprises the steps: after described step S104
Step S105: the interlayer dielectric layer forming contact hole etching barrier layer and be positioned on described contact hole etching barrier layer;
Step S106: remove described dummy gate structure, and form metal gate structure in the position that described dummy gate structure is original;
Step S107: form the contact hole be positioned at above described source electrode and described drain electrode.
9. a semiconductor device, it is characterized in that, comprise: Semiconductor substrate, the grid structure be positioned in described Semiconductor substrate, the light dope source/drain region being positioned at described Semiconductor substrate and source electrode and drain electrode, also comprise the first dislocation being positioned at described light dope source/drain region, the second dislocation being positioned at described source electrode and described drain electrode and be positioned at the stressor layers of described source electrode and described drain top and lifting higher than described Semiconductor substrate.
10. semiconductor device as claimed in claim 9, it is characterized in that, the degree of depth of described first dislocation in described Semiconductor substrate is less than described second dislocation, and described first dislocation is than the channel region of described second dislocation closer to device.
11. semiconductor device as claimed in claim 9, it is characterized in that, described stressor layers comprises carbon silicon layer.
12. semiconductor device as claimed in claim 9, is characterized in that, described stressor layers comprises phosphorus or the in-situ doped carbon silicon layer of arsenic.
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| CN102931222A (en) * | 2011-08-08 | 2013-02-13 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN103066124A (en) * | 2011-10-20 | 2013-04-24 | 台湾积体电路制造股份有限公司 | Semiconductor device with multiple stress structures and method of forming the same |
| US20130099294A1 (en) * | 2011-10-24 | 2013-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOSFETs with Multiple Dislocation Planes |
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| CN103066124A (en) * | 2011-10-20 | 2013-04-24 | 台湾积体电路制造股份有限公司 | Semiconductor device with multiple stress structures and method of forming the same |
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Application publication date: 20150812 |