CN104821180B - A kind of 8 pipe SRAM bit cell gate array of suitable low voltage operating - Google Patents
A kind of 8 pipe SRAM bit cell gate array of suitable low voltage operating Download PDFInfo
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- CN104821180B CN104821180B CN201510269641.1A CN201510269641A CN104821180B CN 104821180 B CN104821180 B CN 104821180B CN 201510269641 A CN201510269641 A CN 201510269641A CN 104821180 B CN104821180 B CN 104821180B
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Abstract
The invention discloses a kind of 8 pipe SRAM bit cell gate array of suitable low voltage operating, the 8 pipe SRAM bit cell is to increase by two NMOS tubes in traditional 6 pipe SRAM bit cells, respectively by two signal line traffic controls；In the array be made up of the 8 pipe SRAM bit cell, each column increases by two PMOSs, also respectively by above-mentioned two signal line traffic controls.In write operation, by controlling two PMOSs that each column is newly-increased in array to turn off the power supply of bit location (bit cell), competitive relation is eliminated, realization does not have competitive operation；Add two control NMOS tubes by new in each SRAM bit cell, eliminate in array with the interference of the SRAM bit cell on the non-selected row of a line.Novel circuit configuration proposed by the present invention can solve SRAM write operation hour simultaneously and be disturbed problem according to race problem, and non-selected cell data, so that SRAM can be operated at lower voltages.
Description
Technical field
The invention belongs to semiconductor circuit technology field, for memory and chip circuit design, and in particular to Yi Zhongshi
Close 8 pipe SRAM bit cell gate array of low voltage operating.
Background technology
As shown in figure 1, Fig. 1 is traditional 6 pipe (6T) SRAM bit cell array schematic diagrames, this traditional SRAM array have with
Lower two major defects：
1. traditional SRAM write operation is closed due to the competition between the presence data value to be write and the data value preserved
System, write operation easily fail in low-voltage.
Assuming that before write operation：Node NVB1 save values are " 1 ", and NV1 is " 0 ".
When write operation, BLB1 0, BL1 1, node NVB1 is reduced to " 0 " by the drop-down of BLB1 " 0 ", so as to lead
Node NV1 upsets are caused to be changed into " 1 ".But during NVB1 is " 0 " by BLB1 drop-downs, because NV1 is also " 0 ", so MPU1
Open, influenceed so NVB1 is also pulled up " 1 " by MPU1, result in competition conflict.In normal working voltage, this competition is closed
System is usually BLB1 stronger, so work(can be write as.But in low voltage operating, BLB1 drop-downs " 0 " can die down, on MPU1
Competition can cause NVB1 to be written to work(.
2. in traditional SRAM, the sram cell that belongs to the bit location that wordline is chosen on the non-selected row of same a line, its
The data value of preservation is vulnerable to interference.
When operation is written and read to SRAM bit cell 1, wordline WL1 can be " 1 ".Now with WL1 but not
The bit location 2 for wanting to be operated is also turned on, because BL2 and BLB2 is " 1 ", it is assumed that NVB2 is " 0 ", and now NVB2 can be by BLB2
The influence voltage of charging can be raised, if raised to a certain extent, NV2 node voltage can be caused to overturn and become " 0 ", and then handle
NVB2 is changed into " 1 ", so as to cause the data of bit location 2 to be interfered, is destroyed.This disturbed condition at lower voltages, more
Easily occur.
The content of the invention
In order to solve the above-mentioned problems of the prior art, the present invention provides a kind of 8 pipe SRAM of suitable low voltage operating
Bit cell circuit array, it is intended to solve SRAM write operation hour and be disturbed problem according to race problem and non-selected cell data.
To realize above-mentioned technical purpose and the technique effect, the present invention is achieved through the following technical solutions：
A kind of 8 pipe SRAM bit cell circuits of suitable low voltage operating, including the first PMOS, the second PMOS, first
NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube and the 6th NMOS tube；
Wherein, first PMOS forms the first phase inverter, second PMOS and institute with first NMOS tube
State the second NMOS tube and form the second phase inverter；The output end of first phase inverter is directly connected to the defeated of second phase inverter
Enter end, the output end of second phase inverter is directly connected to the input of first phase inverter；
The source electrode of first PMOS and second PMOS is connected with power supply, first NMOS tube and described
The source ground of two NMOS tubes；
The source electrode of 3rd NMOS tube is connected with the first bit line, base stage and the first signal wire phase of the 3rd NMOS tube
Even, the drain electrode of the 3rd NMOS tube is connected with the source electrode of the 5th NMOS tube, the base stage and wordline of the 5th NMOS tube
It is connected, the drain electrode of the 5th NMOS tube is connected with the output end of first phase inverter；
The source electrode of 4th NMOS tube is connected with the second bit line, base stage and the secondary signal line phase of the 4th NMOS tube
Even, the drain electrode of the 4th NMOS tube is connected with the source electrode of the 6th NMOS tube, the base stage of the 6th NMOS tube with it is described
Wordline is connected, and the drain electrode of the 6th NMOS tube is connected with the output end of second phase inverter.
The array of 8 pipe SRAM bit cell circuits of a kind of suitable low voltage operating, by above-mentioned 8 pipe of some row several columns
SRAM bit cell circuit is formed, and the 8 pipe SRAM bit cell circuit per a line is connected by the wordline of the row, the institute of each row
State 8 pipe SRAM bit cell circuits to connect by two bit lines of the row, the 3rd PMOS is set up in each row of the array
With the 4th PMOS；
The source electrode of first PMOS of the 8 pipe SRAM bit cell circuit in each row is respectively with the described 3rd
The drain electrode connection of PMOS, the source electrode of the 3rd PMOS is connected with power supply, the base stage of the 3rd PMOS and described the
One signal wire is connected；
The source electrode of second PMOS of the 8 pipe SRAM bit cell circuit in each row is respectively with the described 4th
The drain electrode connection of PMOS, the source electrode of the 4th PMOS is connected with power supply, the base stage of the 4th PMOS and described the
Binary signal line is connected.
Compared with prior art, the beneficial effects of the invention are as follows：
Novel circuit configuration proposed by the present invention solves following two problems, so that SRAM can be in lower electricity
Pressure is operated.
1. in write operation, by controlling the 3rd PMOS P3 and the 4th PMOS P4 of each column to turn off bit location
(bitcell) power supply, eliminates competitive relation, and realization does not have competitive operation.
Assuming that before write operation：The section point NVB1 of first bit location is " 1 ", and the first node NV1 of the first bit location is
“0”。
When write operation, the second bit line BLB1 of first row is 0, and the first bit line BL1 of first row is 1, though now
The first node NV1 of right first bit location is " 0 ", causes the 4th PMOS P4 to open, but due to the secondary signal line of first row
WWLA1 is " 1 ", so the 4th PMOS P4 is turned off, has blocked the path for the section point NVB1 of the first bit location being drawn " 1 ",
I.e. no and first row the second bit line BLB1 draws the competitor of " 0 ", so the section point NVB1 of the first bit location is easy to
Drawn " 0 ".Data contention during due to eliminating write operation, so as to be easier successfully to realize write operation under low pressure.
2. by newly adding the 3rd NMOS tube N3 and the 4th NMOS tube N4 in bit location, the non-choosing to same a line is eliminated
The interference of unit on middle row.
When operation is written and read to the first bit location, the wordline WL1 of the first row can be " 1 ".Now with the first row
Bit line WL1 colleague's but be not desired to the second bit location operated, due to the secondary signal line WWLA2 and secondary series of secondary series
First signal wire WWLB2 is " 0 ", so be not opened, so having cut off the first bit line BL2 and secondary series of secondary series
Second bit line BLB2 to the interference path of second cell data, the data of the second bit location so as to being not easy because being interfered and
It is destroyed.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention,
And can be practiced according to the content of specification, with presently preferred embodiments of the present invention and coordinate accompanying drawing to describe in detail below.This hair
Bright embodiment is shown in detail by following examples and its accompanying drawing.
Brief description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, forms the part of the application, this hair
Bright schematic description and description is used to explain the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is 6 pipe (6T) SRAM bit cell array structure schematic diagrames of prior art；
Fig. 2 is the 8 pipe SRAM bit cell electrical block diagrams of the present invention；
Fig. 3 is the 8 pipe SRAM bit cell gate array structural representations of the present invention.
Embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments, the present invention is described in detail.
It is shown in Figure 2, a kind of 8 pipe SRAM bit cell circuits of suitable low voltage operating, including the first PMOS P1,
Two PMOS P2, the first NMOS tube N1, the second NMOS tube N2, the 3rd NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube N5 and
6th NMOS tube N6；
Wherein, the first PMOS P1 and the first NMOS tube N1 forms the first phase inverter, second PMOS
P2 and the second NMOS tube N2 forms the second phase inverter；It is anti-that the output end of first phase inverter is directly connected to described second
The input of phase device, the output end of second phase inverter are directly connected to the input of first phase inverter；
The first PMOS P1 and the second PMOS P2 source electrode are connected with power supply, the first NMOS tube N1 and
The source ground of the second NMOS tube N2；
The source electrode of the 3rd NMOS tube N3 is connected with the first bit line BL, the base stage of the 3rd NMOS tube N3 and the first letter
Number line WWLB is connected, and the drain electrode of the 3rd NMOS tube N3 is connected with the source electrode of the 5th NMOS tube N5, the 5th NMOS
Pipe N5 base stage is connected with wordline WL, and the drain electrode of the 5th NMOS tube N5 is connected with the output end of first phase inverter；
The source electrode of the 4th NMOS tube N4 is connected with the second bit line BLB, the base stage and second of the 4th NMOS tube N4
Signal wire WWLA is connected, and the drain electrode of the 4th NMOS tube N4 is connected with the source electrode of the 6th NMOS tube N6, and the described 6th
NMOS tube N6 base stage is connected with the wordline WL, the drain electrode of the 6th NMOS tube N6 and the output end of second phase inverter
Connection.
When writing " 0 " operation, each control signal value：
When one writing operates, each control signal value：
| By r/w cell | Go together other units | Other units of same column | |
| WL | 1 | 1 | 0 |
| WWLA | 1 | 0 | 1 |
| WWLB | 0 | 0 | 0 |
| BL | 0 | 1 | 0 |
| BLB | 1 | 1 | 1 |
Participate in shown in Fig. 3, a kind of array of 8 pipe SRAM bit cell circuits of suitable low voltage operating is some by some rows
The 8 pipe SRAM bit cell circuits composition of row, the 8 pipe SRAM bit cell circuit per a line are connected by the wordline of the row, often
The 8 pipe SRAM bit cell circuit of one row is connected by two bit lines of the row, and the is set up in each row of the array
Three PMOS P3 and the 4th PMOS P4；
The first PMOS P1 of the 8 pipe SRAM bit cell circuit in each row source electrode is respectively with the described 3rd
PMOS P3 drain electrode connection, the source electrode of the 3rd PMOS P3 is connected with power supply, the base stage of the 3rd PMOS P3 and
The first signal wire WWLB is connected；
The second PMOS P2 of the 8 pipe SRAM bit cell circuit in each row source electrode is respectively with the described 4th
PMOS P4 drain electrode connection, the source electrode of the 4th PMOS P4 is connected with power supply, the base stage of the 4th PMOS P4 and
The secondary signal line WWLA is connected.
1. in write operation, by controlling the 3rd PMOS P3 and the 4th PMOS P4 of each column to turn off bit location
(bitcell) power supply, eliminates competitive relation, and realization does not have competitive operation.
Assuming that before write operation：The section point NVB1 of first bit location is " 1 ", and the first node NV1 of the first bit location is
“0”。
When write operation, the second bit line BLB1 of first row is 0, and the first bit line BL1 of first row is 1, though now
The first node NV1 of right first bit location is " 0 ", causes the 4th PMOS P4 to open, but due to the secondary signal line of first row
WWLA1 is " 1 ", so the 4th PMOS P4 is turned off, has blocked the path for the section point NVB1 of the first bit location being drawn " 1 ",
I.e. no and first row the second bit line BLB1 draws the competitor of " 0 ", so the section point NVB1 of the first bit location is easy to
Drawn " 0 ".Data contention during due to eliminating write operation, so as to be easier successfully to realize write operation under low pressure.
2. by newly adding the 3rd NMOS tube N3 and the 4th NMOS tube N4 in bit location, the non-choosing to same a line is eliminated
The interference of unit on middle row.
When operation is written and read to the first bit location, the wordline WL1 of the first row can be " 1 ".Now with the first row
Bit line WL1 colleague's but be not desired to the second bit location operated, due to the secondary signal line WWLA2 and secondary series of secondary series
First signal wire WWLB2 is " 0 ", so be not opened, so having cut off the first bit line BL2 and secondary series of secondary series
Second bit line BLB2 to the interference path of second cell data, the data of the second bit location so as to being not easy because being interfered and
It is destroyed.
Above-described embodiment is in the art the purpose is to be to allow simply to illustrate that the technical concepts and features of the present invention
Those of ordinary skill can understand present disclosure and implement according to this, and it is not intended to limit the scope of the present invention.It is all
It is the equivalent change or modification according to made by the essence of present invention, should all covers within the scope of the present invention.
Claims (1)
- A kind of 1. 8 pipe SRAM bit cell gate array of suitable low voltage operating, it is characterised in that：By the 8 of some row several columns Pipe SRAM bit cell circuit form, the 8 pipe SRAM bit cell circuit include the first PMOS (P1), the second PMOS (P2), First NMOS tube (N1), the second NMOS tube (N2), the 3rd NMOS tube (N3), the 4th NMOS tube (N4), the 5th NMOS tube (N5) and 6th NMOS tube (N6)；Wherein, first PMOS (P1) forms the first phase inverter, second PMOS with first NMOS tube (N1) (P2) the second phase inverter is formed with second NMOS tube (N2)；The output end of first phase inverter is directly connected to described The input of two phase inverters, the output end of second phase inverter are directly connected to the input of first phase inverter；The source electrode of first PMOS (P1) and second PMOS (P2) is connected with power supply, first NMOS tube (N1) With the source ground of second NMOS tube (N2)；The source electrode of 3rd NMOS tube (N3) is connected with the first bit line (BL), the base stage and first of the 3rd NMOS tube (N3) Signal wire (WWLB) is connected, and the drain electrode of the 3rd NMOS tube (N3) is connected with the source electrode of the 5th NMOS tube (N5), described The base stage of 5th NMOS tube (N5) is connected with wordline (WL), drain electrode and first phase inverter of the 5th NMOS tube (N5) Output end connects；The source electrode of 4th NMOS tube (N4) is connected with the second bit line (BLB), the base stage of the 4th NMOS tube (N4) and the Binary signal line (WWLA) is connected, and the drain electrode of the 4th NMOS tube (N4) is connected with the source electrode of the 6th NMOS tube (N6), institute The base stage for stating the 6th NMOS tube (N6) is connected with the wordline (WL), the drain electrode of the 6th NMOS tube (N6) and described second anti- The output end connection of phase device；The 8 pipe SRAM bit cell circuit per a line is connected by the wordline of the row, the 8 pipe SRAM bit cell of each row Circuit is connected by two bit lines of the row, it is characterised in that：The 3rd PMOS (P3) is set up in each row of the array With the 4th PMOS (P4)；The source electrode of first PMOS (P1) of the 8 pipe SRAM bit cell circuit in each row is respectively with the described 3rd The drain electrode connection of PMOS (P3), the source electrode of the 3rd PMOS (P3) are connected with power supply, the 3rd PMOS (P3) Base stage is connected with first signal wire (WWLB)；The source electrode of second PMOS (P2) of the 8 pipe SRAM bit cell circuit in each row is respectively with the described 4th The drain electrode connection of PMOS (P4), the source electrode of the 4th PMOS (P4) are connected with power supply, the 4th PMOS (P4) Base stage is connected with the secondary signal line (WWLA).
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| CN106782377B (en) | 2016-12-27 | 2018-01-23 | 惠科股份有限公司 | Liquid crystal display device and driving method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1753102A (en) * | 2004-08-23 | 2006-03-29 | 台湾积体电路制造股份有限公司 | Memory cell structure of sram |
| CN101740116A (en) * | 2008-11-19 | 2010-06-16 | 台湾积体电路制造股份有限公司 | 8 transistor type low leakage sram cell |
| CN103077741A (en) * | 2012-12-31 | 2013-05-01 | 东南大学 | Low-voltage operation storage unit circuit of SRAM (Static Random Access Memory) |
| CN103295624A (en) * | 2012-02-22 | 2013-09-11 | 德克萨斯仪器股份有限公司 | High performance two-port sram architecture using 8T high performance single-port bit cell |
-
2015
- 2015-05-25 CN CN201510269641.1A patent/CN104821180B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1753102A (en) * | 2004-08-23 | 2006-03-29 | 台湾积体电路制造股份有限公司 | Memory cell structure of sram |
| CN101740116A (en) * | 2008-11-19 | 2010-06-16 | 台湾积体电路制造股份有限公司 | 8 transistor type low leakage sram cell |
| CN103295624A (en) * | 2012-02-22 | 2013-09-11 | 德克萨斯仪器股份有限公司 | High performance two-port sram architecture using 8T high performance single-port bit cell |
| CN103077741A (en) * | 2012-12-31 | 2013-05-01 | 东南大学 | Low-voltage operation storage unit circuit of SRAM (Static Random Access Memory) |
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