CN104820466A - SVG (Static Var Generator) system based on real-time clock chip - Google Patents
SVG (Static Var Generator) system based on real-time clock chip Download PDFInfo
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- CN104820466A CN104820466A CN201510254023.XA CN201510254023A CN104820466A CN 104820466 A CN104820466 A CN 104820466A CN 201510254023 A CN201510254023 A CN 201510254023A CN 104820466 A CN104820466 A CN 104820466A
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Abstract
The invention discloses an SVG (Static Var Generator) system based on a real-time clock chip. The system comprises a central control unit and a filter circuit, wherein the central control unit is connected with the clock chip by an I2C bus; an SCL (Serial Clock) pin and an SDA (Serial Data) pin of the clock chip are in open-drain structures; a connecting line of an SCL pin of the central control unit and the SCL pin of the clock chip is connected with a pull-up resistor R1; a connecting line of an SDA pin of the central control unit and the SDA pin of the clock chip is connected with a pull-up resistor R2; the pull-up resistor R1 and the pull-up resistor R2 are connected with a VDD (Voltage Drain Drain) network; a TEST pin of the clock chip is connected with a second pin of a bidirectional diode; a first pin and a third pin of the bidirectional diode are connected with a reserve power supply and the VDD network respectively; and the filter circuit is connected with the clock chip, and comprises a capacitor C1 and a capacitor C2 which are connected in parallel. The structure operability of the system has a very considerable market prospect.
Description
Technical field
The present invention relates to the field of outside RTC (Real-Time Clock) efficient application, specifically, the design relates to a kind of SVG based on real-time timepiece chip (Static Var Generator) system.
Background technology
In productive life, there is the requirement detected in real time the time in many fields.Controller polygamy has real-time clock, for calculating current time; Also has the interrupting input as other chips.Present most of clock chip all needs external crystal oscillator normally to work for RTC, and increase pcb board cabling, precision is not high, affects clock stability.Meet the manually adjustment of leap year needs, not intelligent.
Summary of the invention
For correlative technology field document and above the deficiencies in the prior art, in a large amount of existing literature research with for a long time on the basis of association area Development Practice, the present invention proposes " a kind of SVG system based on real-time timepiece chip ", to overcome in prior art technical barriers such as " external crystal oscillator normally work for RTC; increase pcb board cabling; precision is not high, affects clock stability ".
In order to solve the problems of the technologies described above, the technical solution used in the present invention is: a kind of SVG system based on real-time timepiece chip, comprises central control unit, and described central control unit is connected with clock chip by I2C bus.The SCL pin of described clock chip and SDA pin adopt Floating drain, central control unit SCL pin is connected pull-up resistor R1 with the connecting line of clock chip SCL pin, central control unit SDA pin is connected pull-up resistor R2 with the connecting line of clock chip SDA pin, pull-up resistor R1 and pull-up resistor R2 is connected to VDD network, clock chip TEST pin is connected to the 2nd pin of bilateral diode, and the 1st pin and the 3rd pin of bilateral diode are connected respectively on standby power supply and VDD network.This system also comprises and is connected to clock chip filtering circuit, comprises electric capacity C1 in parallel and electric capacity C2.When the FOE pin of described clock chip is high level, FOUT pin exports the frequency signal of 32.768kHz.
The present invention adopts technique scheme, compared with prior art, set high the DTCXO (digital temperature compensation crystal oscillistor) of the 32.768kHz of stability in the present invention in clock chip used, exported the frequency signal of a 32.768kHz by FOUT pin; There is leap year automatic regulating function (2000 to 2099); Fixed cycle Interruption function.Fixed cycle scope 244.14us ~ 4096min random time setting; Timing upgrades interrupt function.Can according to the timing setting of internal clocking, generation per second or per minute interrupt event; In view of the ease for operation of above advantage and this system architecture, this is designed with very considerable market outlook.
Accompanying drawing explanation
Fig. 1 is that RX-8025T and the K60 of the specific embodiment of the invention is connected by I2C bus interface;
Fig. 2 is the clock chip workflow of the specific embodiment of the invention;
Fig. 3 is the data communication flow process between the MCU (Micro Control Unit) of the specific embodiment of the invention and the real-time chip of external dedicated;
Fig. 4 is the register writes flow process of the specific embodiment of the invention;
Fig. 5 is the register read flow process of the specific embodiment of the invention;
Embodiment
Contrast accompanying drawing below, by the description to case study on implementation, to effect and principle of work, manufacturing process and the operation using method etc. of the mutual alignment between the shape of each component involved by the specific embodiment of the present invention, structure, each several part and annexation, each several part, be described in further detail, have more complete, accurate and deep understanding to help those skilled in the art to inventive concept of the present invention, technical scheme.
A kind of SVG system based on real-time timepiece chip, comprise central control unit, described central control unit is connected with clock chip circuit by I2C bus, central control unit SCL pin is connected pull-up resistor R1 with the connecting line of clock chip SCL pin, central control unit SDA pin is connected pull-up resistor R2 with the connecting line of clock chip SDA pin, pull-up resistor R1 and pull-up resistor R2 is connected to VDD network, clock chip TEST pin is connected to the 2nd pin of bilateral diode, 1st pin and the 3rd pin of bilateral diode are connected respectively on standby power supply and VDD network.The SCL pin of described clock chip and SDA pin adopt Floating drain.This system also comprises and is connected to clock chip filtering circuit, comprises electric capacity C1 in parallel and electric capacity C2.When the FOE pin of described clock chip is high level, FOUT pin exports the frequency signal of 32.768kHz.
In figure, R1, R2 are the SDA of pull-up resistor, clock chip, SCL pin is as shown in Figure 1 Floating drain, is high level time idle.BAT45C bilateral diode, when VDD network has electricity, because unilateral conduction electric current pipe on D1 of diode is exported by 2 pin, diode cut-off below, ensures that battery BT1 is not charged.
When the power-off of VDD network battery BT1 to D1 under pipe power, because unilateral conduction electric current pipe under D1 of diode is exported by 2 pin, the cut-off of upper pipe, ensures that battery is only powered to clock, ensures low-loss and energy-saving.Battery BT1 is back-up source, when preventing system power failure, and loss of data.
C1, C2 are connected between the power supply of clock chip and ground, strobe.
FOUT pin exports the frequency signal of 32.768kHz, and this function needs FOE pin state enable.When FOE is high level, FOUT pin just has frequency signal output.Do not use FOUT in upper graph structure, therefore FOE is connected to the ground, R3 is pull down resistor.
K60 and RX-8025T clock chip is connected by I2C bus, K60 is as primary controller, the beginning of the clock of control I2C bus and data transmission, stop, restarting signal, clock chip produces answer signal as controlled device, there is provided clock data to K60, provide real time clock information in time when primary controller needs clock data.The backstage timing real-time clock when primary controller does not need clock data.
By reference to the accompanying drawings the design is exemplarily described above; obvious the design's specific implementation is not subject to the restrictions described above; as long as have employed the improvement of the various unsubstantialities that method is conceived and technical scheme is carried out of the design; or the design of the design and technical scheme directly applied to other occasion, all within the protection domain of the design without to improve.
Claims (6)
1. the SVG system based on real-time timepiece chip, comprise central control unit, it is characterized in that: described central control unit is connected with clock chip circuit by bus, central control unit SCL pin is connected pull-up resistor R1 with the connecting line of clock chip SCL pin, central control unit SDA pin is connected pull-up resistor R2 with the connecting line of clock chip SDA pin, pull-up resistor R1 and pull-up resistor R2 is connected to VDD network, clock chip TEST pin is connected to the 2nd pin of bilateral diode, 1st pin and the 3rd pin of bilateral diode are connected respectively on standby power supply and VDD network.
2. the SVG system based on real-time timepiece chip according to claim 1, is characterized in that: the SCL pin of described clock chip and SDA pin adopt Floating drain.
3. the SVG system based on real-time timepiece chip according to claim 1, is characterized in that: this system also comprises the filtering circuit being connected to clock chip, comprises electric capacity C1 in parallel and electric capacity C2.
4. the SVG system based on real-time timepiece chip according to claim 1, is characterized in that: when the FOE pin of described clock chip is high level, and FOUT pin exports the frequency signal of 32.768kHz.
5. the SVG system based on real-time timepiece chip according to claim 1, is characterized in that: described clock chip adopts RX-8025T chip, and described central control unit adopts K60 chip.
6. the SVG system based on real-time timepiece chip according to claim 1, is characterized in that: the software clock of described clock chip initialization system when the initialization of SVG system electrification.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510254023.XA CN104820466A (en) | 2015-05-18 | 2015-05-18 | SVG (Static Var Generator) system based on real-time clock chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510254023.XA CN104820466A (en) | 2015-05-18 | 2015-05-18 | SVG (Static Var Generator) system based on real-time clock chip |
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| CN104820466A true CN104820466A (en) | 2015-08-05 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101216699A (en) * | 2007-12-28 | 2008-07-09 | 厦门元谷信息科技有限公司 | Split type energy-saving controller of air-conditioner |
| CN101727732A (en) * | 2008-10-24 | 2010-06-09 | 淄博智洋电气有限公司 | High-voltage electrified body temperature monitoring system based on wireless transmission mode |
| CN103311932A (en) * | 2013-05-29 | 2013-09-18 | 国电南京自动化股份有限公司 | Double-DSP (digital signal processor) control system based on chained SVG (scalable vector graphics) |
| CN104062916A (en) * | 2014-06-05 | 2014-09-24 | 中国航天科技集团公司第五研究院第五一三研究所 | Main control circuit of centralized meter reading system |
| CN204883472U (en) * | 2015-05-18 | 2015-12-16 | 安徽鑫龙电器股份有限公司 | SVG system based on real -time clock chip |
-
2015
- 2015-05-18 CN CN201510254023.XA patent/CN104820466A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101216699A (en) * | 2007-12-28 | 2008-07-09 | 厦门元谷信息科技有限公司 | Split type energy-saving controller of air-conditioner |
| CN101727732A (en) * | 2008-10-24 | 2010-06-09 | 淄博智洋电气有限公司 | High-voltage electrified body temperature monitoring system based on wireless transmission mode |
| CN103311932A (en) * | 2013-05-29 | 2013-09-18 | 国电南京自动化股份有限公司 | Double-DSP (digital signal processor) control system based on chained SVG (scalable vector graphics) |
| CN104062916A (en) * | 2014-06-05 | 2014-09-24 | 中国航天科技集团公司第五研究院第五一三研究所 | Main control circuit of centralized meter reading system |
| CN204883472U (en) * | 2015-05-18 | 2015-12-16 | 安徽鑫龙电器股份有限公司 | SVG system based on real -time clock chip |
Non-Patent Citations (1)
| Title |
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| 夏喜龙: ""基于AT89S52的多时段载波表设计"", 《中国优秀博硕士学位论文全文数据库（硕士）工程科技II辑》 * |
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Application publication date: 20150805 |