CN104811194A - Intensified type clock device and mobile terminal equipment - Google Patents
Intensified type clock device and mobile terminal equipment Download PDFInfo
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Abstract
The invention discloses an intensified type clock device and mobile terminal equipment. The intensified type clock device comprises a clock chip and at least one logic gate unit, wherein each logic gate unit comprises at least one logic gate; the clock chip is connected with each logic gate unit; different logic gate units are correspondingly connected with different function modules of the mobile terminal equipment; each logic gate unit is used for carrying out logic processing on a clock signal output by the clock chip and outputting the clock signal to the function module connected with the logic gate unit. According to the intensified type clock device, the same clock chip is used for providing the clock signal to at least one function module of the mobile terminal equipment; by the aid of the design structure, the different function modules commonly use one set of clock system so that the quantity of the clock chips in the mobile terminal equipment is reduced; the production cost is reduced and the occupation on the area of a PCB (Printed Circuit Board) of the terminal equipment is also reduced.
Description
The application submits the divisional application that Patent Office of the People's Republic of China, application number are 201210004630.7, denomination of invention is the Chinese patent application of " a kind of centralized clock apparatus and mobile terminal device " on 01 09th, 2012 to.
Technical field
The present invention relates to mobile communication terminal technical field, particularly relate to a kind of centralized clock apparatus and mobile terminal device.
Background technology
Along with developing rapidly of mobile communication technology, increasing function can be gathered in mobile phone, as WIFI (Wireless Fidelity, Wireless Fidelity), bluetooth, GPS (Global Positioning System, global positioning system), FM (Frequency Modulation, frequency modulation(FM)) etc., meanwhile, also integrated multiple communication module is wanted in mobile phone, as CDMA (Code Division Multiple Access, code division multiple access accesses), GSM (Global System for Mobile communication, global system for mobile communications), TD-SCDMA (Time Division-Synchronous Code Division Multiple Access, TD SDMA) etc.
Clock frequency, clock work level and startup/closing timing that generally in mobile phone, each module needs are different.Such as, CDMA requires 19.2MHz clock frequency usually, WIFI requires 26MHz clock frequency usually, bluetooth requires 32MHz clock frequency usually, start time clock feature when WIFI and bluetooth are high level, and when CDMA is low level, start time clock feature, for another example, when WIFI is starting state, bluetooth may be closed condition.Given this, be equipped with the onboard clock of an exclusive use often in prior art each module.But, because this mode of being equipped with an exclusive onboard clock to each module needs to be equipped with clock crystal in each inside modules, both manufacturing cost is increased like this, take again PCB (PrintedCircuit Board, printed circuit board (PCB)) area, current mobile phone can not be met to trend that is miniaturized and cost degradation development, therefore, be necessary to develop a kind of novel centralized clock apparatus that time clock feature is provided for multiple module unification.
Summary of the invention
The invention provides a kind of centralized clock apparatus and mobile terminal device, be equipped with to overcome each mobile terminal module in prior art the problem that the production cost that exclusive onboard clock causes is high, take panel area.
The inventive method comprises:
A kind of centralized clock apparatus, comprise clock chip and at least one logic gate, each logic gate comprises at least one gate; Wherein,
Described clock chip is connected respectively with each logic gate, Different Logic gate cell correspondence connects the difference in functionality module of mobile terminal device, each logic gate comprises the gate realizing switch, when the described gate realizing switch is for being in opening in the functional module connected, open and provide clock signal to described functional module, output to the functional module that this logic gate connects;
The gate realizing switch in described logic gate controls to open or close by described functional module; Or described logic gate also connects the central processing unit of described mobile terminal device, then the gate realizing switch in described logic gate controls to open or close by described central processing unit;
The frequency accuracy of the clock signal that described clock chip exports, consistent with the maximum clock frequency precision needed for described each functional module;
Wherein, for the functional module that the frequency of required clock signal frequency and described clock chip clock signal is inconsistent, be connected with frequency regulating circuit between its with corresponding logic gate, the clock signal frequency division that described clock chip exports by described frequency regulating circuit or process of frequency multiplication become the clock signal consistent with described required clock signal frequency; The functional module that the clock signal level exported for required clock signal level and clock chip is inconsistent, be connected with level shifting circuit between its with corresponding logic gate, the clock signal that described logic gate exports is converted to the clock signal consistent with described required clock signal level by described level shifting circuit.
A kind of mobile terminal device, comprising:
Centralized clock apparatus as above, and at least one functional module;
Described functional module is corresponding with each logic gate of described centralized clock apparatus to be connected.
The centralized clock apparatus of one provided by the invention and mobile terminal device, this centralized clock apparatus comprises a clock chip and at least one logic gate, at least one functional module that it is mobile terminal device that this device adopts with clock chip provides clock signal, this project organization can make difference in functionality module share a set of clock system, decrease the quantity of clock chip in mobile terminal device, both reduced production cost, additionally reduced long-pending the taking of terminal equipment PCB surface.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of centralized clock apparatus provided by the invention;
Fig. 2 is the structural representation of the centralized clock apparatus of the embodiment of the present invention one;
Fig. 3 is the structural representation of the centralized clock apparatus of the embodiment of the present invention two;
Fig. 4 is the structural representation of the centralized clock apparatus of the embodiment of the present invention three;
Fig. 5 is the structural representation of a kind of mobile terminal device provided by the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the embodiment of a kind of centralized clock apparatus of the present invention and mobile terminal device is described in further detail.
The invention provides a kind of centralized clock apparatus, as shown in Figure 1, comprise a clock chip and at least one logic gate (in Fig. 1, N is positive integer, and N >=1); Each logic gate comprises at least one gate, wherein, described clock chip is connected respectively with each logic gate, Different Logic gate cell correspondence connects the difference in functionality module of mobile terminal device, each logic gate outputs to the functional module that this logic gate connects after being used for carrying out logical process to the clock signal that described clock chip exports.
At least one functional module that it is mobile terminal device that centralized clock apparatus provided by the invention adopts with clock chip provides clock signal, this project organization can make difference in functionality module share a set of clock system, decrease the quantity of clock chip in mobile terminal device, both reduced production cost, additionally reduced long-pending the taking of terminal equipment PCB surface.
Concrete, in the present invention, logic gate at least comprises a gate, and this gate provides clock signal for controlling clock chip for functional module, and this structure can ensure that each functional module is shared and be independent of each other with clock chip.
Because the present invention's employing provides clock signal with at least one functional module that clock chip is mobile terminal device, and different functional modules often has different requirements to the frequency of clock signal and level, therefore centralized clock apparatus of the present invention must meet the different demands of difference in functionality module to clock signal.
In order to meet the different demands of each functional module to clock signal frequency precision, preferably, the frequency accuracy of the clock signal that described clock chip exports, consistent with the maximum clock frequency precision needed for described each functional module.Like this, the frequency accuracy provided due to this clock chip can meet the full accuracy demand of each functional module, therefore can meet each functional module other leveled demands to Clock Frequency Accuracy equally.
For meeting the different demands of each functional module to clock signal frequency, preferably, for the functional module that the frequency of required clock signal frequency and described clock chip clock signal is inconsistent, be connected with frequency regulating circuit between its with corresponding logic gate, the clock signal frequency division that described clock chip exports by described frequency regulating circuit or process of frequency multiplication become the clock signal consistent with described required clock signal frequency.This mode achieve original clock signal frequency can not the demand of content with funtion module time, by original clock signal frequency division or process of frequency multiplication for functional module provides satisfactory clock signal.
Preferably, described frequency regulating circuit is the circuit that frequency division device/phase-locked loop/frequency division device is connected with phase-locked loop.
Concrete, frequency division device can realize being fixed frequency division to the frequency of original clock signal, as 1/2 frequency division, 1/3 frequency division, but any frequency division can not be realized, as 3/5 frequency division, and phase-locked loop is a kind of feedback control circuit, can realize any frequency division, in concrete enforcement, the circuit that frequency division device can also be adopted to be connected with phase-locked loop obtains the clock signal consistent with clock signal frequency needed for functional module by after original clock signal process.
Preferably, described phase-locked loop is integrated in described functional module inside or arranges independent of described functional module.
In mobile terminal device, some functional module inside itself is configured with phase-locked loop, therefore, when the fixing frequency division of frequency division device can not reach the frequency requirement of functional module and functional module internal configurations phase-locked loop time, the phase-locked loop by described functional module internal configurations reaches any frequency division object.This mode had both taken full advantage of the internal resource of existing capability module, and owing to not needing to arrange phase-locked loop in clock apparatus inside, also would not take PCB surface plate area.
For meeting the different demands of each functional module to clock signal level, preferably, the functional module that the clock signal level exported for required clock signal level and clock chip is inconsistent, be connected with level shifting circuit between its with corresponding logic gate, the clock signal that described logic gate exports is converted to the clock signal consistent with described required clock signal level by described level shifting circuit.The original clock signal that this mode makes clock chip provide is being converted level by during level shifting circuit, with realize original clock signal level can not the demand of content with funtion module time, by original clock signal switching levels for functional module provides satisfactory clock signal.
Preferably, each logic gate comprises the gate realizing switch, when the described gate realizing switch is for being in opening in the functional module connected, opens and providing clock signal to described functional module.
In mobile terminal device, the state of each functional module residing for synchronization may be different, the functional module such as had is starting state, some functional modules are then closed condition, the functional module being in starting state like this needs clock signal, and the functional module being in closed condition does not need clock signal, in order to avoid the system power dissipation waste situation that same clock chip provides clock signal to cause to all functions module simultaneously, utilize the gate realizing switch in described logic gate, when the functional module connected is in opening, open and provide clock signal to described functional module.This mode ensure that and uses the clock signal provided for multiple functional module with clock chip to be independent of each other, and avoids the waste of system power dissipation.
Preferably, described logic gate also connects the central processing unit of described mobile terminal device, then the gate realizing switch in described logic gate controls to open or close by described central processing unit and/or described functional module.
In order to can in time for it provides clock signal when each functional module is in opening, and can in time for it cuts off clock signal when each functional module is in closed condition, mobile terminal device need control the described gate realizing switch and open in time and cut out.Concrete, can according to the actual needs of mobile terminal device, determine the described gate realizing switch open or close be by central processing unit independently control/each functional module independently controls/central processing unit and each functional module co-controlling.Such as, when the ability of the central processing unit processing load of mobile terminal device is lower, can determine that independently controlling described gate by each functional module opens or close; Or, when functional module self does not possess the function that the control logic gate opens, determine that independently controlling described gate by central processing unit opens or close; Or by the needs of described functional module according to self, notice central processing unit goes to trigger described gate and opens or cut out, namely by functional module and central processing unit co-controlling.
According to the concrete needs of mobile terminal device, after determining that the described concrete controlled object of gate realizing switch is described central processing unit and/or described functional module, the described concrete logical process relation realizing the gate of switch can be determined.Centralized clock apparatus provided by the invention is not construed as limiting the described concrete logical process relation realizing the gate of switch, can determine according to actual needs, such as, can determine that described gate is and door or door, XOR gate, NAND gate etc. according to actual needs.
It is to be noted, in order to ensure when the functional module of multiple mobile terminal device shares a clock chip, described clock chip can provide stable clock signal, in actual applications, should avoid occurring that too much functional module shares the phenomenon of a set of centralized clock apparatus of the present invention.Concrete, can determine that a set of centralized clock apparatus can provide the functional module quantity of clock service according to practical situations, avoid driving phenomenon.
Embodiment one
As shown in Figure 2, the invention provides a kind of specific embodiment of centralized clock apparatus, open or close by the gate realizing switch in each functional module separate control logic gate cell (open hereinafter referred to as logic gate or close) in this embodiment.This device specifically comprises: clock chip 201, logic gate 205, logic gate 206, logic gate 207, frequency division device 208, level shifting circuit 209, level shifting circuit 210, wherein frequency division device 208 and level shifting circuit 209 are connected between logic gate 205 and Bluetooth chip 202, logic gate 206 is connected with WIFI chip 203, and level shifting circuit 210 is connected between logic gate 207 and CDMA chip 204.
In this mobile terminal device, Bluetooth chip 202, WIFI chip 203 and CDMA chip 204 common clock chip 201, and, Bluetooth chip 202 requires the clock signal that frequency is 32MHz, level is 1.8V, frequency accuracy is 20ppm (part per million), WIFI chip 203 requires that frequency is 26MHz, level is 1.2V, frequency accuracy is the clock signal of 20ppm, and CDMA chip 204 requires that frequency is 19.2MHz, level is 1.0V, frequency accuracy is the clock signal of 10ppm.The requirement of visible CDMA chip 204 pairs of Clock Frequency Accuracy is the highest, and in the present embodiment, clock chip 201 provides that frequency is 19.2MHz, level is 1.2V, frequency accuracy is the clock signal of 10ppm.
In the present embodiment, logic gate 205 is opened when receiving the high trigger signal from Bluetooth chip 202; Logic gate 206 is opened when receiving the triggering signal from WIFI chip 203, and WIFI chip internal is configured with phase-locked loop; Logic gate 207 is opened when receiving the low level triggering signal from CDMA chip 204.
The centralized clock apparatus of the present embodiment specifically provides the process of clock signal as follows:
Bluetooth chip 202 when needed clock signal time, high level is transferred to by low level by sending to the triggering signal of logic gate 205, now logic gate 205 is opened, clock chip 201 provides frequency to be 19.2MHz, level is the original clock signal of 1.2V, this original clock signal is by after logic gate 205 and frequency division device 208, under the effect of frequency division device 208, be converted to frequency is 32MHz, level is still the clock signal of 1.2V, then level shifting circuit 209 is arrived, and to be converted to frequency under the effect of level shifting circuit 209 be 32MHz, level is the clock signal of 1.8V, reoffer and use to Bluetooth chip 202.
WIFI chip 203 when needed clock signal time, high level is transferred to by low level by sending to the triggering signal of logic gate 206, now logic gate 206 is opened, clock chip 201 provides that frequency is 19.2MHz, level is the original clock signal of 1.2V, this original clock signal is by after logic gate 206, arrive WIFI chip 203, and in WIFI chip 203 phase-locked loop effect under to be converted to frequency be 26MHz, level is still the clock signal of 1.2V, just used by WIFI chip 203 afterwards.
CDMA chip 204 when needed clock signal time, low level is transferred to by high level by sending to the triggering signal of logic gate 207, now logic gate 207 is opened, clock chip 201 provides that frequency is 19.2MHz, level is the original clock signal of 1.2V, this original clock signal is by after logic gate 207, arrive level shifting circuit 210, and to be converted to level under the effect of level shifting circuit 210 be 1.0V, frequency is still the clock signal of 19.2MHz, just used by CDMA chip 204 afterwards.
Embodiment two
As shown in Figure 3, the invention provides the specific embodiment of another kind of centralized clock apparatus, open or close by the gate realizing switch in central processing unit separate control logic gate cell (open hereinafter referred to as logic gate or close) in this embodiment.This device specifically comprises: clock chip 301, logic gate 305, logic gate 306, logic gate 307, level shifting circuit 309, phase-locked loop 310, level shifting circuit 311, wherein, level shifting circuit 309 and phase-locked loop 310 are connected between logic gate 305 and Bluetooth chip 302, logic gate 306 is connected with WIFI chip 303, level shifting circuit 311 is connected between logic gate 307 and CDMA chip 304, and logic gate 305, logic gate 306 are all connected with central processing unit 308 with logic gate 307.
In this mobile terminal device, Bluetooth chip 302, WIFI chip 303 and CDMA chip 304 common clock chip 301, and, Bluetooth chip 302 requires that frequency is 32MHz, level is 1.8V, frequency accuracy is the clock signal of 20ppm, WIFI chip 303 requires that frequency is 26MHz, level is 1.2V, frequency accuracy is the clock signal of 20ppm, and CDMA chip 304 requires that frequency is 19.2MHz, level is 1.0V, frequency accuracy is the clock signal of 10ppm.The requirement of visible CDMA chip 304 pairs of Clock Frequency Accuracy is the highest, and in the present embodiment, clock chip 301 provides that frequency is 19.2MHz, level is 1.2V, frequency accuracy is the clock signal of 10ppm.
In the present embodiment, logic gate 305 is opened when receiving the high trigger signal from central processing unit 308; Logic gate 306 is opened when receiving the high trigger signal from central processing unit 308, and WIFI chip 303 internal configurations has phase-locked loop; Logic gate 307 is opened when receiving the low level triggering signal from central processing unit 308.
The centralized clock apparatus of the present embodiment specifically provides the process of clock signal as follows:
When central processing unit 308 determines that Bluetooth chip 302 is in starting state, high level is transferred to by low level by sending to the triggering signal of logic gate 305, now logic gate 305 is opened, clock chip 301 provides frequency to be 19.2MHz, level is the original clock signal of 1.2V, this original clock signal is by after logic gate 305 and level shifting circuit 309, under the effect of level shifting circuit 309, be converted to level is 1.8V, frequency is still the clock signal of 19.2MHz, then this clock signal arrives phase-locked loop 310, and under phase-locked loop 310 acts on, to be converted to level be 1.8V, frequency is the clock signal of 32MHz, finally be supplied to Bluetooth chip 302 to use.
When central processing unit 308 determines that WIFI chip 303 is in starting state, high level is transferred to by low level by sending to the triggering signal of logic gate 306, now logic gate 306 is opened, clock chip 301 provides that frequency is 19.2MHz, level is the original clock signal of 1.2V, this original clock signal is by after logic gate 306, arrive WIFI chip 303, and in WIFI chip 303 phase-locked loop effect under to be converted to frequency be 26MHz, level is still the clock signal of 1.2V, just used by WIFI chip 303 afterwards.
When central processing unit 308 determines that CDMA chip 304 is in starting state, low level is transferred to by high level by sending to the triggering signal of logic gate 307, now logic gate 307 is opened, clock chip 301 provides that frequency is 19.2MHz, level is the original clock signal of 1.2V, this original clock signal is by after logic gate 307, arrive level shifting circuit 311, and to be converted to level under level shifting circuit 311 acts on be 1.0V, frequency is still the clock signal of 19.2MHz, reoffer and use to CDMA chip 304.
Embodiment three
As shown in Figure 4, the present invention also provides the specific embodiment of another centralized clock apparatus, opens or closes (open hereinafter referred to as logic gate or close) in this embodiment by the gate realizing switch in central processing unit and each functional module co-controlling logic gate.This device specifically comprises: clock chip 401, logic gate 405, logic gate 406, logic gate 407, level shifting circuit 409, phase-locked loop 410, frequency division device 411, level shifting circuit 412, wherein, level shifting circuit 409 and phase-locked loop 410 are connected between logic gate 405 and Bluetooth chip 402, frequency division device 411 is connected between logic gate 406 and WIFI chip 403, level shifting circuit 412 is connected between logic gate 407 and CDMA chip 404, and logic gate 405, logic gate 406 is all connected with central processing unit 408 with logic gate 407.
In this mobile terminal device, Bluetooth chip 402, WIFI chip 403 and CDMA chip 404 common clock chip 401, and, Bluetooth chip 402 requires that frequency is 32MHz, level is 1.8V, frequency accuracy is the clock signal of 20ppm, WIFI chip 403 requires that frequency is 26MHz, level is 1.2V, frequency accuracy is the clock signal of 20ppm, and CDMA chip 404 requires that frequency is 19.2MHz, level is 1.0V, frequency accuracy is the clock signal of 10ppm.The requirement of visible CDMA chip 404 pairs of Clock Frequency Accuracy is the highest, and in the present embodiment, clock chip 401 provides that frequency is 19.2MHz, level is 1.2V, frequency accuracy is the clock signal of 10ppm.
In the present embodiment, logic gate 405 is closed when receiving the low level triggering signal from central processing unit 408; Logic gate 406 is closed when receiving the low level triggering signal from central processing unit 408; Logic gate 407 is closed when receiving the high trigger signal from central processing unit 408.
The centralized clock apparatus of the present embodiment stops providing the detailed process of clock signal as follows:
Bluetooth chip 402 is when determining no longer to need clock signal, request message is stopped to central processing unit 408 tranmitting data register, then central processing unit 408 transfers low level by sending to the triggering signal of logic gate 405 to by high level, now logic gate 405 is closed, and clock chip 401 provides clock signal no longer to Bluetooth chip 402.
WIFI chip 403 is when determining no longer to need clock signal, request message is stopped to central processing unit 408 tranmitting data register, then central processing unit 408 transfers low level by sending to the triggering signal of logic gate 406 to by high level, now logic gate 406 is closed, and clock chip 401 provides clock signal no longer to WIFI chip 403.
CDMA chip 404 is when determining no longer to need clock signal, request message is stopped to central processing unit 408 tranmitting data register, then central processing unit 408 transfers high level by sending to the triggering signal of logic gate 406 to by low level, now logic gate 407 is closed, and clock chip 401 provides clock signal no longer to CDMA chip 404.
Centralized clock apparatus provided by the invention, at least one functional module that employing is mobile terminal device with clock chip provides clock signal, this project organization can make difference in functionality module share a set of clock system, decrease the quantity of clock chip in mobile terminal device, both reduced production cost, additionally reduced long-pending the taking of terminal equipment PCB surface.
The present invention also provides a kind of mobile terminal device, as shown in Figure 5, comprising:
Centralized clock apparatus as above, and at least one functional module (in Fig. 5, N is positive integer, and N >=1); Described functional module is corresponding with each logic gate of described centralized clock apparatus to be connected.
Preferably, described mobile terminal device, also comprises: the central processing unit be connected with each logic gate of described centralized clock apparatus.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (5)
1. a centralized clock apparatus, is characterized in that, comprise clock chip and at least one logic gate, each logic gate comprises at least one gate; Wherein,
Described clock chip is connected respectively with each logic gate, Different Logic gate cell correspondence connects the difference in functionality module of mobile terminal device, each logic gate comprises the gate realizing switch, when the described gate realizing switch is for being in opening in the functional module connected, open and provide clock signal to described functional module, output to the functional module that this logic gate connects;
The gate realizing switch in described logic gate controls to open or close by described functional module; Or described logic gate also connects the central processing unit of described mobile terminal device, then the gate realizing switch in described logic gate controls to open or close by described central processing unit;
The frequency accuracy of the clock signal that described clock chip exports, consistent with the maximum clock frequency precision needed for described each functional module;
Wherein, for the functional module that the frequency of required clock signal frequency and described clock chip clock signal is inconsistent, be connected with frequency regulating circuit between its with corresponding logic gate, the clock signal frequency division that described clock chip exports by described frequency regulating circuit or process of frequency multiplication become the clock signal consistent with described required clock signal frequency; The functional module that the clock signal level exported for required clock signal level and clock chip is inconsistent, be connected with level shifting circuit between its with corresponding logic gate, the clock signal that described logic gate exports is converted to the clock signal consistent with described required clock signal level by described level shifting circuit.
2. device as claimed in claim 1, it is characterized in that, described frequency regulating circuit is the circuit that frequency division device/phase-locked loop/frequency division device is connected with phase-locked loop.
3. device as claimed in claim 2, is characterized in that, described phase-locked loop is integrated in described functional module inside or arranges independent of described functional module.
4. a mobile terminal device, is characterized in that, comprising:
Centralized clock apparatus as claimed in claim 1, and at least one functional module;
Described functional module is corresponding with each logic gate of described centralized clock apparatus to be connected.
5. mobile terminal device as claimed in claim 4, is characterized in that, also comprise:
The central processing unit be connected with each logic gate of described centralized clock apparatus.
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| CN201510182538.3A CN104811194B (en) | 2012-01-09 | 2012-01-09 | A kind of centralized clock device and mobile terminal device |
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| CN201510182538.3A CN104811194B (en) | 2012-01-09 | 2012-01-09 | A kind of centralized clock device and mobile terminal device |
| CN201210004630.7A CN102594344B (en) | 2012-01-09 | 2012-01-09 | Centralized clock device and mobile terminal device |
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| CN102594344A (en) | 2012-07-18 |
| CN102594344B (en) | 2015-03-18 |
| CN104811194B (en) | 2018-05-01 |
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