CN104810057A - Flash memory apparatus and flash memory erasing method - Google Patents
Flash memory apparatus and flash memory erasing method Download PDFInfo
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- CN104810057A CN104810057A CN201410041171.9A CN201410041171A CN104810057A CN 104810057 A CN104810057 A CN 104810057A CN 201410041171 A CN201410041171 A CN 201410041171A CN 104810057 A CN104810057 A CN 104810057A
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Abstract
The invention relates to a flash memory apparatus and a flash memory erasing method. The flash memory apparatus comprises a plurality of memory cells arranged in at least one lease. The flash memory erasing method comprises the following steps: executing erasing motion on the memory cells in the at least one lease in the above flash memory according to a first electrical signal, dividing the at least lease to obtain a plurality of subleases, and carrying out erasing motion on the memory cells in the subleases according to a second electrical signal, wherein the current absolute value supplied by the first electrical signal is smaller than the current absolute value supplied by the second electrical signal.
Description
Technical field
The invention relates to a kind of flash memory devices, and relate to a kind of erasing method of storage unit of flash memory devices especially.
Background technology
Along with the evolution of electronics technology, electronic installation becomes instrument necessary in people's life.And in order to provide the function of long-acting and a large amount of data storing, nonvolatile memory becomes important data storing medium.Further, in electronic product now, flash memories is in comparatively welcome nonvolatile memory.
Please refer to Fig. 1, Fig. 1 illustrates in prior art, the number of memory cells of flash memories and the graph of a relation of critical voltage.Wherein, curve C 1 represents that the storage unit of flash memories is being under the state of being programmed, the magnitude of voltage of critical voltage and the relation curve of corresponding number of memory cells.Curve C 2 then represents that the storage unit of flash memories is being in by under erased status, the magnitude of voltage of critical voltage and the relation curve of corresponding number of memory cells.Wherein, the signal of erasing that the many utilizations of prior art are fixed carries out disposable action of erasing to provide enough large electric current to the multiple storage unit in same wellblock.
Under the erase mode of prior art, because each storage unit is being carried out in the process of erasing, the difference in the change speed of its critical voltage, and the phenomenon that the voltage regime Δ V causing curve C 2 to distribute is excessively wide.This is due in order to make all storage unit all complete the action of erasing, and must wait for the phenomenon that the slow storage unit of change of critical voltage causes the long period.In this phenomenon, the storage unit of the change speed of critical voltage often can occur to erase the phenomenon of (over erase), and even produces the situation of bit line electric leakage.Further, existing erase mode often needs the action of adjoint rear sequencing (post-program) to reduce its voltage regime Δ V, increases the complexity in action, and increases the utilization rate of storage unit, reduce the serviceable life of storage unit.
Summary of the invention
The invention provides the erasing method of a kind of flash memories and storage unit thereof, effectively reduce storage unit and to occur to erase the possibility of (over erase) phenomenon.
In the erasing method of flash memories of the present invention, flash memories has the majority storage unit be configured at least one wellblock, and the step of erasing method comprises: first, perform according to the first electric signal action of erasing for the storage unit at least one wellblock in flash memories, and, subregion is carried out at least one wellblock, and obtain most sub-wellblocks, perform with foundation the second electric signal action of erasing respectively again for the storage unit in sub-wellblock, wherein, the current absolute value of the first electric signal supply is less than the current absolute value of the second electric signal supply.
Flash memory devices of the present invention comprises at least one wellblock and Memory Controller.Wellblock comprises most storage unit, and Memory Controller couples the storage unit of at least one wellblock.When Memory Controller performs and erases action, first perform according to the first electric signal action of erasing for the storage unit at least one wellblock in flash memories, and carry out subregion to obtain most sub-wellblocks at least one wellblock, then perform with foundation the second electric signal action of erasing for the storage unit in sub-wellblock respectively.Wherein, the current absolute value of the first electric signal supply is less than the current absolute value of the second electric signal supply.
Based on above-mentioned, the present invention carries out the action of erasing of the storage unit in flash memory memory storage by the action of erasing of two benches formula.Wherein, the first electric signal that first stage utilizes current absolute value less carries out disposable action of erasing for all storage unit in identical wellblock, and in subordinate phase, the second electric signal utilizing current absolute value larger carries out the action of erasing of subregion for the storage unit of the multiple sub-wellblock in wellblock.Thus, the uniformity coefficient of the change that the storage unit of normal storage unit and low conductance produces for action of erasing can be controlled, and unlikely generation is because need to erase for a long time action and caused the generation of phenomenon of erasing for the storage unit with low conductance.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawings to be described in detail below.
Accompanying drawing explanation
Fig. 1 illustrates in prior art, the number of memory cells of flash memories and the graph of a relation of critical voltage.
Fig. 2 illustrates the process flow diagram of the erasing method of the flash memories of one embodiment of the invention.
Fig. 3 illustrates the schematic diagram of the flash memory devices of one embodiment of the invention.
Fig. 4 illustrates the schematic diagram carrying out the embodiment of subregion for wellblock of the embodiment of the present invention.
Fig. 5 illustrates storage unit threshold voltage variations curve map when this case embodiment flash memories is erased.
Wherein, description of reference numerals is as follows:
C1, C2, CV1, CV2, CV3: curve
Δ V: voltage regime
S210 ~ S230: the step of erasing method
300: flash memory devices
310: Memory Controller
320: flash memories
321 ~ 32N: wellblock
MC11 ~ MCPM: storage unit
BL1, BLP: bit line
WL1, WLA1, WLA2, WL3, WLM: wordline
SA1 ~ SA3: sub-wellblock
EV1: the first electric signal
EV2: the second electric signal
Embodiment
Please refer to Fig. 2, Fig. 2 illustrates the process flow diagram of the erasing method of the flash memories of one embodiment of the invention.Wherein, there is in flash memories one or more wellblock (well), and in each wellblock, include most storage unit.When carry out storage unit erase action time, in step S210, can for all storage unit at least one wellblock in flash memories according to the first electric signal, and the relatively low voltage utilizing it to have performs action of erasing, wherein the voltage of the first electric signal is such as between+6.0V ~+8.8V.The first electric signal that this action of erasing in advance provides is the movement that the critical voltage of all storage unit that can make in same wellblock produces at a slow speed.It should be noted that carry out in step S210 erase in action, have the storage unit of different critical voltage translational speed under the impact of the first electric signal, the difference of the change of the critical voltage produced can not be very large.
In addition, in step S220, then carry out the action of subregion for the storage unit will carried out in the wellblock of erasing, and the storage unit in the wellblock of carrying out erasing is divided into most sub-wellblocks.Then, in step S230, then respectively for the storage unit of the multiple sub-wellblock obtained in step S220, come to erase action to the storage unit of each sub-wellblock respectively by the second electric signal converting normal voltage to, wherein, the voltage of the second electric signal is such as between+8.8V ~ 9.8V.Wherein, the current absolute value that the second electric signal can provide is greater than the current absolute value that the first electric signal can provide.Further, under the impact of the second electric signal, the translational speed of the critical voltage of storage unit will be greater than in step S210, the translational speed of the critical voltage that storage unit produces because of the impact of the first electric signal.
Please pay special attention at this, in step S230, carry out erasing action respectively for multiple sub-wellblock, advantage is wherein, in single sub-wellblock, the slower Number of Storage Units of critical voltage translational speed is few compared to the storage unit that the critical voltage translational speed in whole wellblock is slower, in other words, when carrying out erasing action for the storage unit in single sub-wellblock, the storage unit that too much critical voltage translational speed is slower can be waited for, and produce the long problem of erase time.In other words, carry out erasing action for the storage unit in single sub-wellblock, effectively can reduce storage unit and to occur to erase the possibility of phenomenon.
Subsidiary one carries, and the first electric signal can be first to erase the voltage signal of voltage or the current signal of the first erasing current, and the second electric signal can be then second to erase the voltage signal of voltage or the current signal of the second erasing current.Focus on, the current absolute value that the first electric signal provides is less than the current absolute value that the second electric signal provides.
Please refer to Fig. 3, Fig. 3 illustrates the schematic diagram of the flash memory devices 300 of one embodiment of the invention.Flash memory devices 300 comprises Memory Controller 310 and flash memories 320.Flash memories 320 comprises one or more wellblock 321 ~ 32N, and has most storage unit in each wellblock 321 ~ 32N.
When the storage unit in flash memories 320 will carry out erasing action, Memory Controller 310 can carry out erasing action according to the step of Fig. 2 for the storage unit of each wellblock 321 ~ 32N in flash memories 320.Relatively it should be noted that the action about carrying out subregion in step S220 for wellblock, referring to Fig. 3 and Fig. 4, wherein Fig. 4 illustrates the schematic diagram carrying out the embodiment of subregion for wellblock of the embodiment of the present invention.In the diagram, with the wellblock 321 of Fig. 3 for example, wellblock 321 comprises most storage unit MC11 ~ MCPM.Wherein, storage unit MC11 ~ MC1M is coupled to bit line BL1 jointly, and storage unit MCP1 ~ MCPM is coupled to bit line BLP jointly.In addition, storage unit MC11 ~ MC1M is coupled to wordline WL1 ~ WLM respectively, and storage unit MCP1 ~ MCPM is also coupled to wordline WL1 ~ WLM respectively.
The subregion action of the wellblock 321 that Memory Controller 310 carries out is that the wordline WL1 ~ WLM coupled according to storage unit MC11 ~ MCPM carries out.Wherein, take Fig. 4 as example, the storage unit being coupled to wordline WL1 ~ WLA1 can be divided into the first sub-wellblock SA1, the storage unit being coupled to wordline WLA2 ~ WLA3 can be divided into the second sub-wellblock SA2, and the storage unit being coupled to wordline WLA3 ~ WLM can be divided into the 3rd sub-wellblock SA3.
In addition, when Memory Controller 310 carries out erasing action for each sub-wellblock SA1 ~ SA3 in wellblock 321 respectively, Memory Controller 310 can one of them of chooser wellblock SA1 ~ SA3 using as choosing sub-wellblock, not selected sub-wellblock is not then for choose sub-wellblock.In the diagram, with sub-wellblock SA1 for choosing sub-wellblock for example, sub-wellblock SA2 and SA3 be not then for choose sub-wellblock.Further, Memory Controller 310 can provide chooses the wordline WL of sub-wellblock SA1 ~ WLA1 to choose word-line signal of erasing, and provides and do not choose the wordline WLA2 of sub-wellblock SA2 and SA3 ~ WLM not choose word-line signal of erasing.Wherein, the above-mentioned absolute value of voltage of word-line signal of erasing of choosing is greater than the absolute value of voltage not choosing word-line signal of erasing.
Illustrate with the example of reality, what Memory Controller 310 provided chooses the voltage of word-line signal of erasing about can equal-8.8 volts, and do not choose the pact of the voltage of word-line signal of erasing can equal-1 volt, further, Memory Controller 310 reoffers the second electric signal with action of erasing to the storage unit chosen in sub-wellblock SA1.And it should be noted that, when Memory Controller 310 provide the second electric signal with the storage unit chosen in sub-wellblock SA1 is erased action time, choose the critical voltage of the storage unit in sub-wellblock SA1 can change fast according to the second electric signal, meanwhile, do not choose the storage unit in sub-wellblock SA1 can along with the action and changing slowly of erasing of the storage unit chosen in sub-wellblock SA1 yet.
Certainly, above-mentioned about Fig. 4, the sub-wellblock quantity in wellblock 321 is only an example, and wherein, sub-wellblock quantity can decide according to the height state of the conductance of storage unit in flash memories.Further, above-mentioned about choosing the magnitude of voltage also only just example of erasing word-line signal and do not choose word-line signal of erasing, and be not used to limit scope of the present invention.In fact, choose the word-line signal and do not choose the magnitude of voltage of word-line signal of erasing can decide according to the process parameter of processing procedure selected by flash memories and drift state thereof of erasing, there is no the value limited.
In addition, even more noteworthy, in the embodiment of this case, after the action of erasing of storage unit completing subordinate phase (as step S230), rear sequencing action (Post-program) can also be carried out for storage unit.Above-mentioned rear sequencing action can compensate for the storage unit that critical voltage drift is excessive, to reduce the voltage regime Δ V of the critical voltage distribution of the storage unit after erasing.And the storage unit erase step of two benches formula based on this case embodiment, needing to carry out rear sequencing action with the storage unit reaching compensation effect will significantly reduce relative to prior art, and the time of then sequencing action also can effectively shorten.
Below please refer to Fig. 5, Fig. 5 illustrates storage unit threshold voltage variations curve map when this case embodiment flash memories is erased.Wherein, curve C V1 represents that storage unit is in critical voltage distribution curve when being programmed state.And storage unit receive the first electric signal EV1 with the action of erasing performing the first stage after, the critical voltage distribution curve of storage unit changes to curve C V2.And storage unit receive the second electric signal EV2 with the action of erasing performing subordinate phase after, the critical voltage distribution curve of storage unit then changes to curve C V3.Can be found by Fig. 5, storage unit is after the action of erasing completing the two-stage, do not have the storage unit that phenomenon occurred to erase to occur, and, the voltage regime Δ V of the critical voltage distribution of the storage unit after erasing also can have being limited of degree, is unlikely and produces the excessively wide situation of voltage regime Δ V.
In sum, the present invention to be erased action to the storage unit in wellblock by two stage mode, and, erase in action in the storage unit of subordinate phase, also carry out subregion for wellblock, to carry out the action of erasing of storage unit respectively to the sub-wellblock in wellblock.Thus, storage unit is crossed the situation of erasing and can be significantly lowered, and effectively maintains the quality of storage unit.
Claims (10)
1. an erasing method for flash memories, this flash memories has the majority storage unit be configured at least one wellblock, comprising:
Perform according to one first electric signal action of erasing for the plurality of storage unit at least one wellblock of this in this flash memories;
Carry out subregion for this at least one wellblock, and obtain most sub-wellblocks; And
Perform with foundation one second electric signal action of erasing respectively for the storage unit in the plurality of sub-wellblock,
Wherein, the current absolute value of this first electric signal supply is less than the current absolute value of this second electric signal supply.
2. the erasing method of flash memories as claimed in claim 1, wherein this first electric signal is first to erase voltage or the first erasing current, and this second electric signal is then second to erase voltage or the second erasing current.
3. the erasing method of flash memories as claimed in claim 1, wherein carries out subregion for this at least one wellblock and the step obtaining the plurality of sub-wellblock comprises:
The wordline coupled for the plurality of storage unit in this at least one wellblock is to carry out subregion.
4. the erasing method of flash memories as claimed in claim 1, wherein comprises with the step performing action of erasing according to this second electric signal for the storage unit in the plurality of sub-wellblock respectively:
Respectively this sub-wellblock is selected to choose sub-wellblock as one;
There is provided this to choose at least one wordline one in sub-wellblock to choose word-line signal of erasing, and provide this to choose at least one at least one wordline one of wellblock of not choosing outside sub-wellblock not choose word-line signal of erasing; And
There is provided this second electric signal to choose the storage unit in sub-wellblock to erase action to this.
5. the erasing method of flash memories as claimed in claim 4, wherein, this choose the absolute value of voltage of word-line signal of erasing to be greater than absolute value of voltage that this does not choose word-line signal of erasing.
6. a flash memory devices, comprising:
At least one wellblock, comprises most storage unit; And
One Memory Controller, couple the plurality of storage unit of this at least one wellblock, when this Memory Controller performs and erases action, first perform according to one first electric signal action of erasing for the plurality of storage unit at least one wellblock of this in this flash memories, and carry out subregion to obtain most sub-wellblocks for this at least one wellblock, perform with foundation one second electric signal action of erasing respectively again for the storage unit in the plurality of sub-wellblock, wherein, the current absolute value of this first electric signal supply is less than the current absolute value of this second electric signal supply.
7. flash memory devices as claimed in claim 6, wherein this first electric signal is first to erase voltage or the first erasing current, and this second electric signal is then second to erase voltage or the second erasing current.
8. flash memory devices as claimed in claim 6, wherein the wordline that couples for the plurality of storage unit in this at least one wellblock of this Memory Controller is to carry out subregion.
9. flash memory devices as claimed in claim 6, when wherein this Memory Controller erases action for the storage unit in the plurality of sub-wellblock to perform according to this second electric signal respectively, this Memory Controller selects respectively this sub-wellblock to choose sub-wellblock as one, and provide this to choose at least one wordline one in sub-wellblock to choose word-line signal of erasing, and provide this to choose at least one wordline one of wellblock of not choosing outside sub-wellblock not choose word-line signal of erasing, and provide this second electric signal to choose the storage unit in sub-wellblock to erase action to this.
10. flash memory devices as claimed in claim 9, wherein this choose the absolute value of voltage of word-line signal of erasing to be greater than absolute value of voltage that this does not choose word-line signal of erasing.
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| CN201410041171.9A CN104810057B (en) | 2014-01-27 | 2014-01-27 | The erasing method of flash memory devices and flash memories |
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| CN201410041171.9A CN104810057B (en) | 2014-01-27 | 2014-01-27 | The erasing method of flash memory devices and flash memories |
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| US20040039870A1 (en) * | 2002-08-21 | 2004-02-26 | Micron Technology, Inc. | Non-contiguous address erasable blocks and command in flash memory |
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