CN104795798A - Power circuit - Google Patents
Power circuit Download PDFInfo
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- CN104795798A CN104795798A CN201510135758.0A CN201510135758A CN104795798A CN 104795798 A CN104795798 A CN 104795798A CN 201510135758 A CN201510135758 A CN 201510135758A CN 104795798 A CN104795798 A CN 104795798A
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- voltage
- management chip
- power management
- power circuit
- circuit
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Abstract
A power circuit comprises two input ends, an output end, an over-voltage protection circuit, a low-voltage protection circuit, a voltage control circuit and a power management chip, wherein both the over-voltage protection circuit and the low-voltage protection circuit are connected between the two input ends and the power management chip, the voltage control circuit is connected between the power management chip and the output end, and the two input ends are respectively used for connecting external voltages and being grounded. If the connected external voltage exceeds the first preset value, the power management chip stops working and the output end stops outputting the voltage. If the connected external voltage is lower than the second preset value, the power management chip stops working and the output end stops outputting the voltage. If the external voltage is between the first preset value and the second preset value, the power management chip works and outputs the corresponding voltage to the output end. The power circuit can stop outputting the voltage when the external voltage is too high or too low.
Description
Technical field
The application relates to a kind of power circuit.
Background technology
Power circuit is used for providing operating voltage for the electronic equipment of rear end.If external power supply voltage is stable not, such as too high or too low, then likely damage is caused to the electronic equipment of rear end.
Summary of the invention
The technical problem that the application mainly solves is to provide a kind of power circuit that can stop output voltage when external voltage is higher or lower.
A kind of power circuit, comprise first input end, the second input and output, overvoltage crowbar, under-voltage protecting circuit, voltage control circuit and power management chip, described overvoltage crowbar and under-voltage protecting circuit are all connected to first input end, between the second input and power management chip, described voltage control circuit is connected between power management chip and output, described first input end for accessing external voltage, described second input end grounding; When the external voltage that described first input end accesses is more than the first preset value, the voltage of described overvoltage crowbar output low level is to the Enable Pin of power management chip, and described power management chip quits work, and output stops output voltage; When the external voltage that described first input end accesses is lower than the second preset value, the voltage of described under-voltage protecting circuit output low level is to the Enable Pin of power management chip, and described power management chip quits work, and output stops output voltage; When the external voltage that described first input end accesses is between the first preset value and the second preset value, the Enable Pin of described power management chip receives high level signal, and described power management chip work also exports satisfactory voltage to output.
Further, described power circuit also comprises fuse, and described fuse is connected in series between first input end and overvoltage crowbar.
Further, described power circuit also comprises the first diode, and the anode of described first diode is connected with first input end, and the negative electrode of described first diode is connected with overvoltage crowbar.
Further; described overvoltage crowbar comprises voltage stabilizing didoe, first and second resistance, triode; the negative electrode of described voltage stabilizing didoe is connected with first input end; the anode of described voltage stabilizing didoe is connected with the second input by after first and second resistance successively; node between first and second resistance described is connected with the base stage of triode; the emitter of described triode is connected with the second input, and the collector electrode of described triode is connected with the Enable Pin of power management chip.
Further, described power circuit also comprises the first electric capacity, and described first electric capacity is connected between the negative electrode of voltage stabilizing didoe and the second input.
Further, described power circuit also comprises the second electric capacity, and described second electric capacity is connected with the first Capacitance parallel connection.
Further, described under-voltage protecting circuit comprises the 3rd and the 4th resistance, and described first input end is successively by being connected with the second input after the 3rd and the 4th resistance, and the node between the described 3rd and the 4th resistance is connected with the Enable Pin of power management chip.
Further, described power circuit also comprises inductance, and described inductance is connected between the source electrode of power management chip and output.
Further, described power circuit also comprises the 3rd electric capacity, and the first end of described 3rd electric capacity is connected between one end be not connected with power management chip of inductance and the second input.
Further, described power circuit also comprises the 4th electric capacity, and described 4th electric capacity is connected with the 3rd Capacitance parallel connection.
Above-mentioned power circuit the external voltage accessed when first input end more than the first preset value time, the voltage of described overvoltage crowbar output low level is to the Enable Pin of power management chip, described power management chip quits work, and output stops output voltage; When the external voltage that described first input end accesses is lower than the second preset value, the voltage of described under-voltage protecting circuit output low level is to the Enable Pin of power management chip, and described power management chip quits work, and output stops output voltage; When the external voltage that described first input end accesses is between the first preset value and the second preset value, the Enable Pin of described power management chip receives high level signal, described power management chip work also exports satisfactory voltage to output, can realize stopping output voltage when external voltage is higher or lower.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the better embodiment of the application's power circuit.
Embodiment
Below in conjunction with drawings and embodiments, the application is described in detail.
Please refer to shown in Fig. 1, the better embodiment of the application's power circuit comprises fuse F1, diode D1, overvoltage crowbar, under-voltage protecting circuit, voltage control circuit and power management chip U1.Described overvoltage crowbar and under-voltage protecting circuit are all connected between input IN1 and IN2 and power management chip U1; described voltage control circuit is connected between power management chip U1 and output OUT; described input IN1 for accessing external voltage, described input IN2 ground connection.When the external voltage that described input IN1 accesses is more than the first preset value; the voltage of described overvoltage crowbar output low level is to the Enable Pin EN of power management chip U1; described power management chip U1 quits work, and output OUT stops output voltage.When the external voltage that described input IN1 accesses is lower than the second preset value; the voltage of described under-voltage protecting circuit output low level is to the Enable Pin EN of power management chip U1; described power management chip U1 quits work, and output OUT stops output voltage.When the external voltage that described input IN1 accesses is between the first preset value and the second preset value, the Enable Pin EN of described power management chip U1 receives high level signal, and described power management chip U1 works and exports satisfactory voltage to output OUT.
Described overvoltage crowbar comprises voltage stabilizing didoe Z14, resistance R80, R10 and NPN triode Q19.Described under-voltage protecting circuit comprises resistance R2 and R5.Described voltage control circuit comprises resistance R3, R6 and R8.Described input IN1 is connected with the anode of diode D1 by fuse F1, the negative electrode of described diode D1 is connected with the negative electrode of voltage stabilizing didoe Z14, and the anode of described voltage stabilizing didoe Z14 is connected with input IN2 by after resistance R80 and R10 successively.Node between described resistance R80 and R10 is connected with the base stage of NPN triode Q19, and the emitter of described NPN triode Q19 is connected with input IN2.In present embodiment, described input IN2 is connected with the earth.
The negative electrode of described diode D1 is by electric capacity C5 ground connection, and described electric capacity C5 and electric capacity C78 is connected in parallel.The negative electrode of described diode D1 is also connected with input IN2 by after resistance R2 and R5 successively.Node between described resistance R2 and R5 is connected with the collector electrode of NPN triode Q19 and the Enable Pin EN of power management chip U1.
The voltage input end VIN of described power management chip U1 is connected with the negative electrode of diode D1, and the start end BOOT of described power management chip U1 is connected with the source electrode PH of power management chip U1 by after electric capacity C1.The trigger end TR of described power management chip U1 is by being connected with input IN2 after electric capacity C9, and the clock signal terminal RT of described power management chip U1 is connected with input IN2 by after resistance R32 and R1 successively.The earth terminal of described power management chip U1 is connected with input IN2, the comparison end COMP of described power management chip U1 is successively by being connected with input IN2 after resistance R7 and electric capacity C79, and the comparison end COMP of described power management chip U1 is also directly connected with input IN2 by electric capacity C8.The source electrode PH of described power management chip U1 is also sequentially by being connected with input IN2 after inductance L 1, resistance R3, R6 and R8, and the node between described resistance R6 and R8 is connected with the induction end VSNS of power management chip U1.The power supply of described power management chip U1 gets out end PWR sky and connects.The source electrode PH of described power management chip U1 is also connected with the negative electrode of diode D2, and the anode of described diode D2 is connected with input IN2.Described resistance R3, R6 and R8 of being connected in series also is connected in parallel with electric capacity C3, and electric capacity C2 and electric capacity C3 is connected in parallel.Node between described inductance L 1 and electric capacity C2 is output OUT.
In above-mentioned power circuit, described diode D1 plays line reversal protective effect.Resistance by arranging resistance R80 and R10 in described overvoltage crowbar makes when the voltage that input IN1 accesses is more than 36V; namely triode Q19 is switched on; namely the Enable Pin EN of described power management chip U1 receives low level voltage, and namely described power management chip U1 quits work.Resistance by arranging resistance R3, R6 and R8 in follow-up voltage control circuit can obtain the output voltage of 12V at output OUT place.Described inductance L 1, electric capacity C2 and C3 play filter action.
Resistance by arranging resistance R2 and R5 in described under-voltage protecting circuit makes, when the voltage that input IN1 receives is lower than during 16V time (the Enable Pin EN voltage of power management chip U1 is lower than 1.2V), power management chip U1 to be quit work.
Claims (10)
1. a power circuit, comprise first input end, the second input and output, it is characterized in that: described power circuit also comprises overvoltage crowbar, under-voltage protecting circuit, voltage control circuit and power management chip, described overvoltage crowbar and under-voltage protecting circuit are all connected to first input end, between the second input and power management chip, described voltage control circuit is connected between power management chip and output, described first input end for accessing external voltage, described second input end grounding; When the external voltage that described first input end accesses is more than the first preset value, the voltage of described overvoltage crowbar output low level is to the Enable Pin of power management chip, and described power management chip quits work, and output stops output voltage; When the external voltage that described first input end accesses is lower than the second preset value, the voltage of described under-voltage protecting circuit output low level is to the Enable Pin of power management chip, and described power management chip quits work, and output stops output voltage; When the external voltage that described first input end accesses is between the first preset value and the second preset value, the Enable Pin of described power management chip receives high level signal, and described power management chip work also exports satisfactory voltage to output.
2. the power circuit as described in claim 1, is characterized in that: described power circuit also comprises fuse, and described fuse is connected in series between the anode of first input end and the first diode.
3. the power circuit as described in claim 1, is characterized in that: described power circuit also comprises the first diode, and anode and the fuse of described first diode are connected in series in first input end, and the negative electrode of described first diode is connected with overvoltage crowbar.
4. the power circuit as described in claim 1; it is characterized in that: described overvoltage crowbar comprises voltage stabilizing didoe, first and second resistance, triode; the negative electrode of described voltage stabilizing didoe is connected with the negative electrode of the first diode; the anode of described voltage stabilizing didoe is connected with the second input by after first and second resistance successively; node between first and second resistance described is connected with the base stage of triode; the emitter of described triode is connected with the second input, and the collector electrode of described triode is connected with the Enable Pin of power management chip.
5. the power circuit as described in claim 4, is characterized in that: described power circuit also comprises the first electric capacity, and described first electric capacity is connected between the negative electrode of voltage stabilizing didoe and the second input.
6. the power circuit as described in claim 5, is characterized in that: described power circuit also comprises the second electric capacity, and described second electric capacity is connected with the first Capacitance parallel connection.
7. the power circuit as described in claim 1; it is characterized in that: described under-voltage protecting circuit comprises the 3rd and the 4th resistance; described first input end is successively by being connected with the second input after the 3rd and the 4th resistance, and the node between the described 3rd and the 4th resistance is connected with the Enable Pin of power management chip.
8. the power circuit as described in claim 1, is characterized in that: described power circuit also comprises inductance, and described inductance is connected between the source electrode of power management chip and output.
9. the power circuit as described in claim 8, is characterized in that: described power circuit also comprises the 3rd electric capacity, and the first end of described 3rd electric capacity is connected between one end be not connected with power management chip of inductance and the second input.
10. the power circuit as described in claim 9, is characterized in that: described power circuit also comprises the 4th electric capacity, and described 4th electric capacity is connected with the 3rd Capacitance parallel connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510135758.0A CN104795798A (en) | 2015-03-26 | 2015-03-26 | Power circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510135758.0A CN104795798A (en) | 2015-03-26 | 2015-03-26 | Power circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104795798A true CN104795798A (en) | 2015-07-22 |
Family
ID=53560417
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510135758.0A Pending CN104795798A (en) | 2015-03-26 | 2015-03-26 | Power circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104795798A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106451366A (en) * | 2016-10-21 | 2017-02-22 | 成都前锋电子仪器有限责任公司 | Voltage input protection circuit |
| CN112382251A (en) * | 2020-12-01 | 2021-02-19 | 深圳市华星光电半导体显示技术有限公司 | Time sequence control drive board, display panel and display device |
-
2015
- 2015-03-26 CN CN201510135758.0A patent/CN104795798A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106451366A (en) * | 2016-10-21 | 2017-02-22 | 成都前锋电子仪器有限责任公司 | Voltage input protection circuit |
| CN106451366B (en) * | 2016-10-21 | 2019-02-05 | 成都前锋电子仪器有限责任公司 | A kind of voltage input protection circuit |
| CN112382251A (en) * | 2020-12-01 | 2021-02-19 | 深圳市华星光电半导体显示技术有限公司 | Time sequence control drive board, display panel and display device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150722 |
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| WD01 | Invention patent application deemed withdrawn after publication |