CN104795390B - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing method Download PDFInfo
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- CN104795390B CN104795390B CN201410028580.5A CN201410028580A CN104795390B CN 104795390 B CN104795390 B CN 104795390B CN 201410028580 A CN201410028580 A CN 201410028580A CN 104795390 B CN104795390 B CN 104795390B
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Abstract
The present invention relates to a kind of semiconductor device and its manufacturing methods.The semiconductor device includes substrate, at least a capacitor, the first protective layer, redistributing layer and the second protective layer.The capacitor is located on the substrate, and contacts the conductive through hole of the substrate.First protective layer covers the capacitor.The redistributing layer is located on first protective layer, and is electrically connected to the capacitor.Second protective layer covers the redistributing layer and first protective layer.Whereby, electrical characteristics can be effectively improved and increase configuration region.
Description
Technical field
The present invention relates to a kind of semiconductor device and its manufacturing methods, it is manifestly that, it is related to a kind of with integrating passive dress
The semiconductor device and its manufacturing method put.
Background technology
There would generally be the passive devices such as capacitor and inductor in custom circuit.In order to which purpose is miniaturized, by the electricity
Resistance device and the inductor are integrated into semiconductor processes to be formed with integrating passive device (Integrated Passive
Device, IPD) semiconductor device just be a main trend.However, the thickness of the Conventional semiconductor devices can not effectively subtract
It is few, and the purpose of micromation is unable to reach, and its process flow is excessively tediously long and electrical characteristics are poor.
Therefore, it is necessary to a kind of semiconductor device and its manufacturing method are provided, to solve the above problems.
Invention content
This exposure relates in one aspect to a kind of semiconductor device.In one embodiment, the semiconductor device include substrate,
An at least capacitor, the first protective layer, the first interconnection metal, the second interconnection metal, redistributing layer and the second protective layer.It is described
Substrate has first surface, second surface and at least one first conductive through hole, and at least one first conductive through hole is through described
Substrate and it is revealed in the first surface and the second surface.The capacitor is located at the first surface of the substrate, and wraps
Containing first electrode, intermediate insulating layer and second electrode, wherein the area of the first electrode is more than the intermediate insulating layer or institute
State the area of second electrode, and at least one first conductive through hole described in first electrode contact.The first protective layer covering
The first surface of an at least capacitor and the substrate, wherein first protective layer has the first opening and second
Opening, first opening appears the first electrode, and second opening appears the second electrode.First interconnection
Metal is located at first opening of first protective layer.The second interconnection metal is located at the described of first protective layer
Second opening.The redistributing layer is adjacent to first protective layer, and is electrically connected the second interconnection metal.Described second protects
Sheath covers the redistributing layer and first protective layer.
The another aspect of this exposure is related to a kind of manufacturing method.In one embodiment, a kind of manufacturer of semiconductor device
Method comprises the steps of：(a) substrate is provided, the substrate has first surface, second surface and at least one first conductive through hole,
At least one first conductive through hole is revealed in the first surface；(b) the first conductive layer is sequentially formed, insulating layer and second is led
Electric layer is on the first surface of the substrate, wherein at least one first conductive through hole described in first conductive layer contact；
(c) the part insulating layer and second conductive layer are removed, to be respectively formed an at least intermediate insulating layer and at least one second
Electrode；(d) part first conductive layer is removed, to form an at least first electrode, wherein the first electrode, the centre
Insulating layer and the second electrode form capacitor, and the area of the first electrode is more than the intermediate insulating layer or described second
The area of electrode, and at least one first conductive through hole described in first electrode contact；(e) the first protective layer is formed in the electricity
On the first surface of container and the substrate, wherein first protective layer has the first opening and the second opening, it is described
First opening appears the first electrode, and second opening appears the second electrode；(f) connection gasket and redistribution are formed
Layer is respectively formed the first interconnection metal and the second interconnection metal in the described first opening and described on first protective layer
Second opening, wherein the connection gasket is located on the described first interconnection metal, the redistributing layer is located at the described second interconnection gold
On category；(g) the second protective layer is formed on the connection gasket, the redistributing layer and first protective layer；And (h) from institute
Substrate described in the second surface thinning of substrate is stated, to appear at least one first conductive through hole.
Description of the drawings
Fig. 1 shows the schematic cross-sectional view of an embodiment of semiconductor device of the present invention；
Fig. 2 to 14 shows the schematic diagram of an embodiment of the manufacturing method of semiconductor device of the present invention；
Figure 15 shows the schematic cross-sectional view of another embodiment of semiconductor device of the present invention；
Figure 16 to 17 shows the schematic diagram of another embodiment of the manufacturing method of semiconductor device of the present invention；
Figure 18 shows the schematic cross-sectional view of another embodiment of semiconductor device of the present invention；
Figure 19 to 21 shows the schematic diagram of another embodiment of the manufacturing method of semiconductor device of the present invention；
Figure 22 shows the schematic cross-sectional view of another embodiment of semiconductor device of the present invention；And
Figure 23 shows the schematic cross-sectional view of another embodiment of semiconductor device of the present invention.
Specific embodiment
With reference to figure 1, the schematic cross-sectional view of an embodiment of semiconductor device of the present invention is shown.The semiconductor device 1 wraps
Containing substrate 10, an at least capacitor 27, the first protective layer 28, first interconnection metal 42, second interconnect metal 44, third interconnects gold
It is conductive to belong to 46, inductor 36, connection gasket 40, redistributing layer 38, the second protective layer 48, multiple the first metal layers 54 and at least one
Device 62.
Substrate 10 has first surface 101, second surface 102, the first hole 103, the second hole 104, conductive metal
105th, the first conductive through hole 106 and the second conductive through hole 107.In the present embodiment, substrate 10 be glass substrate, conductive metal
105 be copper, and fills up the first hole 103 and the second hole 104 to be respectively formed the first conductive through hole 106 and the second conductive through hole
107, wherein the first conductive through hole 106 and the second conductive through hole 107 are revealed in the first surface 101 and second surface of substrate 10
102。
Capacitor 27 is located at the first surface 101 of substrate 10, and includes first electrode 161, intermediate insulating layer 201 and second
Electrode 221.Intermediate insulating layer 201 is located between first electrode 161 and second electrode 221, and the area of first electrode 161 is big
In intermediate insulating layer 201 or the area of second electrode 221, and first electrode 161 contacts the first conductive through hole 106.In this implementation
In example, first electrode 161 includes the first metal of part 121 and layer 141 is blocked in part.Block layer 141 and be located at part first in part
Between metal 121 and the first surface 101 of substrate 10.The material of the first metal of part 121 is aluminum bronze (AlCu), partly blocks layer
141 material is titanium (Ti).The material of intermediate insulating layer 201 is tantalum pentoxide (Ta2O5), the material of second electrode 221 is aluminium
Copper (AlCu).
The first surface 101 of first protective layer, 28 covering capacitor 27 and substrate 10, and with the first opening 281, second
Opening 282 and third opening 283.First opening 281 appears first electrode 161, and the second opening 282 appears second electrode 221, and
Third opening 283 appears the second conductive through hole 107.In the present embodiment, the first protective layer 28 is non-photosensitive high molecular polymer,
Such as：Benzocyclobutene (Benzocyclobutene, BCB), polyimides (Polyimide, PI) or epoxy resin
(Epoxy)。
First interconnection metal 42 is located in the first opening 281 of the first protective layer 28, and the second interconnection metal 44 is located at first
In second opening 282 of protective layer 28, and third interconnection metal 46 is located in the third opening 283 of the first protective layer 28.This reality
It applies in example, it is copper that the first interconnection metal 42, second, which interconnects metal 44 and the material of third interconnection metal 46,.
Inductor 36 is located on the first protective layer 28, and is electrically connected the first interconnection metal 42.Connection gasket 40, which is located at first, to be protected
On sheath 28, inductor 36 is electrically connected to, and on the first interconnection metal 42.Redistributing layer 38 is located at the first protective layer 28
On, and on the second interconnection metal 44 and third interconnection metal 46.Therefore, connection gasket 40 is electrically connected via the first interconnection metal 42
First electrode 161 is connected to, redistributing layer 38 is electrically connected to second electrode 221, and the redistribution via the second interconnection metal 44
Layer 38 is electrically connected to the second conductive through hole 107 via third interconnection metal 46.In the present embodiment, inductor 36, connection gasket 40
With redistributing layer 38 all comprising 34 and first seed layer 30 of third metal, wherein the first seed layer 30 is titanium copper (TiCu), and the
Three metals 34 are copper (Cu).It is understood, however, that the first seed layer 30 can be omitted, that is, the third metal of this position
34 be inductor 36, connection gasket 40 and redistributing layer 38.
Second protective layer 48 covering inductor 36, connection gasket 40,38 and first protective layer 28 of redistributing layer, and with more
A opening 481 is to appear connection gasket 40 and redistributing layer 38.In the present embodiment, the second protective layer 48 is non-photosensitive polyphosphazene polymer
Object is closed, such as：Benzocyclobutene (Benzocyclobutene, BCB), polyimides (Polyimide, PI) or epoxy resin
(Epoxy)。
The first metal layer 54 is located in the opening 481 of the second protective layer 48 to be electrically connected connection gasket 40 and redistributing layer 38.
In the present embodiment, the first metal layer 54 includes the 4th metal 52 and the second seed layer 50, wherein the second seed layer 50 is titanium copper
(TiCu), and the 4th metal 52 is copper (Cu).It is understood, however, that the second seed layer 50 can be omitted, that is, this position
The 4th metal 52 put is the first metal layer 54.In addition, the 4th metal 52 can be single or multi-layer structure.
Electric installation 62 is located at the second surface 102 of substrate 10, and it is conductive logical to be electrically connected the first conductive through hole 106 and second
Hole 107.In the present embodiment, electric installation 62 includes third seed layer 56, second metal layer 58 and convex block 60.
In the present embodiment, electric installation 62 and inductor 36 are distant due to spacing substrate 10, therefore when conductive dress
After putting 62 connection substrates 66 (Figure 22), the ground connection that is distant, therefore being not easily susceptible on substrate 66 with substrate 66 of inductor 36
Layer influences, and can effectively improve electrical characteristics.In addition, electric installation 62 is located at the second surface 102 of substrate 10, and it is not directly connected to
Pad 40, therefore, the size of connection gasket 40 can substantially reduce, and increase configuration region.
With reference to figs. 2 to 14, the schematic diagram of an embodiment of the manufacturing method of semiconductor device of the present invention is shown.
With reference to figure 2, substrate 10 (such as glass substrate) is provided.Substrate 10 has first surface 101 and second surface 102.
Then, at least one first hole 103 and at least one second hole hole 104 are formed in the first surface 101 of substrate 10.At this point, the
One hole 103 and the second hole hole 104 are blind hole.
With reference to figure 3, apply conductive metal 105 in the first hole 103 and the first surface of the second hole 104 and substrate 10
101.In the present embodiment, conductive metal 105 is copper, and fills up the first hole 103 and the second hole 104.Then, removal is located at
Conductive metal 105 on the first surface 101 of substrate 10, therefore, the conductive metal 105 for being retained in the first hole 103 form the
One conductive through hole 106, and the conductive metal 105 for being retained in the second hole 104 forms the second conductive through hole 107, wherein first leads
106 and second conductive through hole 107 of electric through-hole is revealed in the first surface 101 of substrate 10.
With reference to figure 4, the first conductive layer 16 and middle layer 18 are sequentially formed on the first surface 101 of substrate 10, wherein
One conductive layer 16 contacts the first conductive through hole 106 and the second conductive through hole 107.In the present embodiment, the first conductive layer 16 includes
First metal 12 and block layer 14, block layer 14 between the first metal 12 and the first surface 101 of substrate 10, and described the
One metal is aluminum bronze (AlCu), blocks layer 14 for titanium (Ti).Middle layer 18 is located on the first metal 12 of the first conductive layer 16, and
Material is tantalum (Ta).
With reference to figure 5, anode oxidation process is carried out so that middle layer 18 is transformed into insulating layer 20.In the present embodiment, it is intermediate
The tantalum (Ta) of layer 18 is oxidized to the tantalum pentoxide that can be insulated (Ta2O5).Then, the second conductive layer 22 is formed in insulating layer 20
On.In the present embodiment, the material of the second conductive layer 22 is the second metal, is aluminum bronze (AlCu).
With reference to figure 6, the first photoresist 24 is formed on the second conductive layer 22, and remove the first photoresist of part 24 so that first
The second conductive layer of remainder covering part 22 of photoresist 24.
With reference to figure 7, the second conductive layer 22 not covered by the first photoresist 24 and insulating layer 20 are removed.That is, removal part is exhausted
20 and second conductive layer 22 of edge layer, to be respectively formed an at least intermediate insulating layer 201 and an at least second electrode 221.
With reference to figure 8, after removing the first photoresist 24, the second photoresist 26 is re-formed in the first conductive layer 16 and second electrode 221
On, and removing the second photoresist of part 26 so that the remainder covering second electrode 221 of the second photoresist 26 and part first are conductive
Layer 16.In the present embodiment, the area of the remainder of the second photoresist 26 is more than the face of the remainder (Fig. 7) of the first photoresist 24
Product.
With reference to figure 9, the first conductive layer 16 not covered by the second photoresist 26 is removed.That is, removal the first conductive layer of part 16,
To form an at least first electrode 161.First electrode 161 includes the first metal of part 121 and layer 141 is blocked in part.First electricity
Pole 161, intermediate insulating layer 201 and second electrode 221 form capacitor 27, and the wherein area of first electrode 161 is more than intermediate exhausted
The area of edge layer 201 or second electrode 221, and first electrode 161 contacts the first conductive through hole 106.Then, the second photoresist is removed
26。
With reference to figure 10, the first protective layer 28 is formed on the first surface 101 of capacitor 27 and substrate 10, wherein first protects
Sheath 28 has first the 281, second opening 282 of opening and third opening 283.First opening 281 appears first electrode 161, the
Two openings 282 appear second electrode 221, and third opening 283 appears the second conductive through hole 107.In the present embodiment, the first protection
Layer 28 is non-photosensitive high molecular polymer, such as：Benzocyclobutene (Benzocyclobutene, BCB), polyimides
(Polyimide, PI) or epoxy resin (Epoxy).
With reference to figure 11, the first seed layer 30 is formed on the first protective layer 28 and its in opening.First seed layer 30 is titanium
Copper (TiCu).Then, third photoresist 32 is formed, third photoresist 32 has multiple openings.
With reference to figure 12, third metal 34 is formed in the opening of third photoresist 32.In the present embodiment, third metal 34 is
Copper (Cu).Then, removal third photoresist 32.Then, the first seed layer 30 not covered by third metal 34 is removed so that third
Metal 34 forms inductor 36, connection gasket 40 and redistributing layer 38 on the first protective layer 28.Meanwhile third metal 34 distinguishes shape
Metal 44 and third interconnection metal 46 are interconnected in first the 281, second opening of opening 282 and the into the first interconnection metal 42, second
In three openings 283.Inductor 36 is electrically connected connection gasket 40, and connection gasket 40 is located on the first interconnection metal 42, redistributing layer 38
In on the second interconnection metal 44 and third interconnection metal 46.
In the present embodiment, inductor 36, connection gasket 40 and redistributing layer 38 all include 34 and first crystal seed of third metal
Layer 30.It is understood, however, that the first seed layer 30 can be omitted, that is, the third metal 34 of this position is inductor
36th, connection gasket 40 and redistributing layer 38, and the step of removing the first seed layer 30 can be omitted.
With reference to figure 13, the second protective layer 48 is formed in inductor 36, connection gasket 40,38 and first protective layer of redistributing layer
On 28.In the present embodiment, the second protective layer 48 is non-photosensitive high molecular polymer, such as：Benzocyclobutene
(Benzocyclobutene, BCB), polyimides (Polyimide, PI) or epoxy resin (Epoxy).
With reference to figure 14, multiple openings 481 are formed in the second protective layer 48, to appear connection gasket 40 and redistributing layer 38.It connects
, formed the second seed layer 50 in the second protective layer 48 and its opening 481 in, to connect pad 40 and redistributing layer 38.
In the present embodiment, the second seed layer 50 is titanium copper (TiCu).Then, the 4th photoresist (not shown) is formed in the second seed layer 50
On, the 4th photoresist has multiple openings, corresponds to the opening 481 of the second protective layer 48.Then, formed the 4th metal 52 in
In the opening 481 of second protective layer 48, and the 4th photoresist and the second seed layer 50 not covered by the 4th metal 52 are removed,
To form multiple the first metal layers 54.
The first metal layer 54 is electrically connected connection gasket 40 and redistributing layer 38.In the present embodiment, the first metal layer 54 includes
4th metal 52 and the second seed layer 50.It is understood, however, that the second seed layer 50 can be omitted, that is, this position
4th metal 52 is the first metal layer 54, and can omit the step of removing the second seed layer 50.In addition, the 4th metal 52 can be with
It is single or multi-layer structure.
Then, it is conductive to appear the first conductive through hole 106 and second from 102 thinning substrate 10 of the second surface of substrate 10
Through-hole 107.Then, an at least electric installation 62 is formed on the second surface 102 of substrate 10, and is made as shown in Figure 1 half
Conductor device 1.Electric installation 62 is electrically connected the first conductive through hole 106 and the second conductive through hole 107.In the present embodiment, it is conductive
Device 62 includes third seed layer 56, second metal layer 58 and convex block 60.
With reference to figure 15, the schematic cross-sectional view of another embodiment of semiconductor device of the present invention is shown.Semiconductor device 1a with
Semiconductor device 1 shown in FIG. 1 is roughly the same, wherein identical device is endowed and is identically numbered.Semiconductor device 1a and Fig. 1
Shown 1 difference of semiconductor device is in the structure in conductive through hole.In semiconductor device 1a, conductive metal 105 is unfilled
First hole 103 and the second hole 104, and positioned at the first hole 103 and the side wall of the second hole 104, to define at least one
Central channel.Insulating materials 108 is located at an at least central channel, to form at least one first conductive through hole 106a and at least 1 the
Two conductive through hole 107a.
With reference to figure 16 to 17, the schematic diagram of another embodiment of the manufacturing method of semiconductor device of the present invention is shown.This reality
The manufacturing method for applying example is roughly the same with the manufacturing method of Fig. 2 to 14, does not exist together as follows.The present embodiment is the step of hookup 2
Suddenly.
With reference to figure 16, apply conductive metal 105 in the side wall, the side wall of the second hole 104 and substrate 10 of the first hole 103
First surface 101.In the present embodiment, conductive metal 105 be copper, and 103 and second hole 104 of unfilled first hole and
Define an at least central channel 109.Then, conductive metal 105 of the removal on the first surface 101 of substrate 10.
With reference to figure 17, apply central insulation material 108 in an at least central channel 109.Therefore, it is retained in the first hole 103
Conductive metal 105 and central insulation material 108 form the first conductive through hole 106a, and be retained in the conductive metal of the second hole 104
105 and the second conductive through hole 107a of formation of central insulation material 108, wherein the first conductive through hole 106a and the second conductive through hole 107a
It is revealed in the first surface 101 of substrate 10.Then, the subsequent process of the present embodiment is all identical with the manufacturing method of Fig. 4 to 14, with
Semiconductor device 1a as shown in figure 15 is made.
With reference to figure 18, the schematic cross-sectional view of another embodiment of semiconductor device of the present invention is shown.Semiconductor device 1b with
Semiconductor device 1 shown in FIG. 1 is roughly the same, wherein identical device is endowed and is identically numbered.Semiconductor device 1b and Fig. 1
Shown semiconductor device 1 does not exist together as described below.Semiconductor device 1b further includes at least one first metal gasket 162.First gold medal
Belong to the first surface 101 that pad 162 is located at substrate 10, and contact the second conductive through hole 107.The third opening of first protective layer 28
283 appear the first metal gasket 162, and third interconnection metal 46 is electrically connected to the second conductive through hole 107 via the first metal gasket 162.
In the present embodiment, the first metal gasket 162 is formed simultaneously with first electrode 161, therefore it further includes 121 He of the first metal of part
Block layer 141 in part.Block layer 141 and be located between the first metal of part 121 and the first surface 101 of substrate 10 in part.Part
The material of first metal 121 is aluminum bronze (AlCu), and the material for partly blocking layer 141 is titanium (Ti).
With reference to figure 19 to 21, the schematic diagram of another embodiment of the manufacturing method of semiconductor device of the present invention is shown.This reality
The manufacturing method for applying example is roughly the same with the manufacturing method of Fig. 2 to 14, does not exist together as follows.The present embodiment is the step of hookup 7
Suddenly.
With reference to figure 19, the second photoresist 26 is formed on the first conductive layer 16 and second electrode 221, and remove the second light of part
Resistance 26 so that the remainder covering second electrode 221 and the first conductive layer of part 16 of the second photoresist 26.It is in Fig. 8 differences
In in the present embodiment, the remainder of the second photoresist 26 is more covered in 107 top of the second conductive through hole.
With reference to figure 20, the first conductive layer 16 not covered by the second photoresist 26 is removed.That is, removal the first conductive layer of part
16, to form first electrode 161 and at least one first metal gasket 162, wherein 161 and first metal gasket 162 of first electrode all wraps
Block layer 141, and the first metal gasket 162 is located on the second conductive through hole 107 containing the first metal of part 121 and part.Then, it goes
Except the second photoresist 26.
With reference to figure 21, the first protective layer 28 is formed on the first surface 101 of capacitor 27 and glass 10, wherein first protects
Sheath 28 has first the 281, second opening 282 of opening and third opening 283.Third opening 283 appears the first metal gasket 162.
Then, the subsequent process of the present embodiment is all identical with the manufacturing method of Figure 11 to 14, is filled with the semiconductor for being made as shown in figure 18
Put 1b.
With reference to figure 22, the schematic cross-sectional view of another embodiment of semiconductor device of the present invention is shown.Semiconductor device 1c with
Semiconductor device 1a shown in figure 15 is roughly the same, wherein identical device is endowed and is identically numbered.Semiconductor device 1c with
Semiconductor device 1a shown in figure 15 does not exist together as described below.Semiconductor device 1c does not include the first metal layer 54, and second protects
Sheath 48 does not have any opening.
With reference to figure 23, the schematic cross-sectional view of another embodiment of semiconductor device of the present invention is shown.Semiconductor device 1d with
Semiconductor device 1 shown in FIG. 1 is roughly the same, wherein identical device imparting is identically numbered.Semiconductor device 1d and Fig. 1 institutes
The semiconductor device 1 shown does not exist together as described below.Semiconductor device 1d further includes at least a semiconductor device 64 and substrate 66.
Semiconductor device 64 is attached to the second protective layer 48, and is electrically connected to the first metal layer 54.Substrate 66 is attached to substrate 10
Second surface 102, wherein the first conductive through hole 106 and the second conductive through hole 107 are electrically connected to substrate 66 via electric installation 62.
Only above-described embodiment is only to illustrate the principle of the present invention and its effect rather than to limit the present invention.Therefore, it is affiliated
The technical staff in field, which modifies to above-described embodiment and changes, does not take off spirit of the invention still.The interest field of the present invention should
Listed by claims as be described hereinafter.
Claims (10)
1. a kind of semiconductor device, it includes：
Substrate, it is described with first surface, second surface, at least one first conductive through hole and at least one second conductive through hole
At least one first conductive through hole is through the substrate and is revealed in the first surface and the second surface, and described at least 1 the
Two conductive through holes are through the substrate and are revealed in the first surface and the second surface, and the substrate is glass lined
Bottom；
An at least capacitor, be located at the substrate first surface, the capacitor include first electrode, intermediate insulating layer and
Second electrode, wherein the area of the first electrode is more than the intermediate insulating layer or the area of the second electrode, and described
At least one first conductive through hole described in first electrode contact；
First protective layer, the first surface of an at least capacitor and the substrate described in covering, wherein described first protects
Sheath has the first opening, the second opening and third opening, and first opening appears the first electrode, second opening
Appear the second electrode, and third opening appears second conductive through hole；
First interconnection metal is located at first opening of first protective layer；
Second interconnection metal is located at second opening of first protective layer；
Redistributing layer is adjacent to first protective layer, and is electrically connected the second interconnection metal；
Second protective layer covers the redistributing layer and first protective layer；And
Third interconnects metal, and the third interconnection metal is located at third opening, and the redistributing layer is located at the third
It interconnects on metal.
2. semiconductor device according to claim 1, wherein the substrate further has at least a hole and conductive gold
Belong to, the conductive metal fills up an at least hole to form at least one first conductive through hole.
3. semiconductor device according to claim 1, wherein the substrate further has at least a hole, conductive metal
And central insulating material, the conductive metal is located at the side wall of an at least hole, described to define an at least central channel
Insulating materials is located at an at least central channel, at least one first conductive through hole described in formation.
4. semiconductor device according to claim 1, further includes inductor, it is adjacent to first protection
Layer, and it is electrically connected the first interconnection metal；Second protective layer further covers the inductor.
5. semiconductor device according to claim 4, further includes connection gasket, it is electrically connected to the inductor, institute
Connection gasket is stated on the described first interconnection metal, and the redistributing layer is located on the described second interconnection metal.
6. semiconductor device according to claim 1 further includes multiple the first metal layers, wherein described second protects
Sheath has multiple openings, and to appear the redistributing layer, the first metal layer is located at the described of second protective layer and opens
Mouthful.
7. semiconductor device according to claim 6 further includes an at least semiconductor device, it is attached to described
Second protective layer, and it is electrically connected to the first metal layer.
8. a kind of semiconductor device, it includes：
Substrate, it is described with first surface, second surface, at least one first conductive through hole and at least one second conductive through hole
At least one first conductive through hole is through the substrate and is revealed in the first surface and the second surface, and described at least 1 the
Two conductive through holes are through the substrate and are revealed in the first surface and the second surface, wherein the substrate is glass lined
Bottom；
At least one first metal gasket is located at the first surface of the substrate, and at least one second conductive through hole described in contact；
An at least capacitor, be located at the substrate first surface, the capacitor include first electrode, intermediate insulating layer and
Second electrode, wherein the area of the first electrode is more than the intermediate insulating layer or the area of the second electrode, and described
At least one first conductive through hole described in first electrode contact；
First protective layer, the first surface of an at least capacitor and the substrate described in covering, wherein described first protects
Sheath has the first opening, the second opening and third opening, and first opening appears the first electrode, second opening
Appear the second electrode, and third opening appears first metal gasket；
First interconnection metal is located at first opening of first protective layer；
Second interconnection metal is located at second opening of first protective layer；
Redistributing layer is adjacent to first protective layer, and is electrically connected the second interconnection metal；
Third interconnects metal, and the third for being located at first protective layer is open, and the redistributing layer is located at described the
On three interconnection metals；And
Second protective layer covers the redistributing layer and first protective layer.
9. semiconductor device according to claim 8, wherein the substrate further has at least a hole and conductive gold
Belong to, the conductive metal fills up an at least hole to form at least one first conductive through hole.
10. semiconductor device according to claim 8, wherein the substrate further has at least a hole, conductive gold
Category and central insulating material, the conductive metal is located at the side wall of an at least hole, to define an at least central channel, institute
It states insulating materials and is located at an at least central channel, at least one first conductive through hole described in formation.
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| CN103137601A (en) * | 2011-11-28 | 2013-06-05 | 日月光半导体制造股份有限公司 | Semiconductor device and method for manufacturing the same |
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| CN101996270A (en) * | 2009-08-12 | 2011-03-30 | 瑞萨电子株式会社 | Method of designing semiconductor device and method of manufacturing the same |
| CN103137601A (en) * | 2011-11-28 | 2013-06-05 | 日月光半导体制造股份有限公司 | Semiconductor device and method for manufacturing the same |
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