CN104795317A - Wafer positioning method - Google Patents
Wafer positioning method Download PDFInfo
- Publication number
- CN104795317A CN104795317A CN201510189321.5A CN201510189321A CN104795317A CN 104795317 A CN104795317 A CN 104795317A CN 201510189321 A CN201510189321 A CN 201510189321A CN 104795317 A CN104795317 A CN 104795317A
- Authority
- CN
- China
- Prior art keywords
- wafer
- positioning method
- alignment mark
- exposed areas
- normal region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
Abstract
The invention discloses a wafer positioning method. The wafer positioning method includes providing a wafer comprising a normal area and a non-exposure area, and setting alignment marks on the normal area and the non-exposure area respectively; implementing Taiko process; positioning the wafer and forming a device on the normal area of the wafer. By means of the Taiko process, the peripheral edge of the wafer, namely the non-exposure area, should be reserved, and the normal area and the non-exposure area of the wafer are provided with alignment marks at the same time. When the Taiko process is performed, the normal area of the wafer is ground and thinned, the alignment marks of the normal area are ground and become shallow or disappear, and the alignment marks of the non-exposure area are still reserved. Therefore, the non-exposure area is provided with the alignment marks, resistance of the semiconductor power device of an automobile electronic product can be reduced, formation of a subsequent device can be ensured, and low yield of the semiconductor power device due to the fact that the wafer is hard to position is avoided.
Description
Technical field
The present invention relates to IC manufacturing field, particularly a kind of wafer positioning method.
Background technology
Semiconductor power device is (referred to as power device, English: Power MOS) to carry out Power Processing, have the semiconductor device of process high voltage, big current ability, its voltage process range can from tens volts to several kilovolts, and its current handling capability reaches as high as a few kiloampere.Typical Power Processing comprises frequency-conversion processing, transformation process, unsteady flow process, power management etc.Early stage semiconductor power device comprises heavy-duty diode and thyristor etc., be mainly used in industry and electric power system, afterwards, along with the developing rapidly of novel semi-conductor power device taking power MOSFET device as representative, present semiconductor power device widely, in computer, the 4C industry (Computer, Communication, Consumer Electronics, Cartronics) that current, consumer electronics, automotive electronics are representative, the increasing extent of semiconductor power device application is wide, also more and more welcome.At present, semiconductor power device, is in most of the cases used by as switch, briefly, is just used to control passing through and blocking of electric current.Therefore, the research and development of semiconductor power device, constantly advances round this target.Present semiconductor power device, has had good performance, in the electric current and voltage process range required, and can close to a more satisfactory switch.
For the semiconductor power device being applied to automobile electronics, be the special requirement of fit, need the resistance value (Rdson) further reducing semiconductor power device.Because the resistance value size of this semiconductor power device and the thickness of preparation process and wafer have very large relation, that is, in order to reduce the resistance value of semiconductor power device, further must reduce the thickness of wafer (being generally silicon chip), make wafer thinning more than 180um, the wafer thickness after thinning is less than 100um.Above-mentioned wafer thinning process needs to use Taiko technique (a kind of wafer rear grinding process), therefore, the alignment mark be arranged on wafer can be ground and shoal or be eliminated in Taiko process, Here it is make follow-up when forming device on wafer, be difficult to accurately locate wafer, cause subsequent technique to produce difficulty.
Summary of the invention
The invention provides a kind of wafer positioning method, to solve in prior art the problem that there is wafer and be difficult to locate in Taiko technique.
For solving the problems of the technologies described above, the invention provides a kind of wafer positioning method, comprising: providing wafer, this wafer comprises normal region and non-exposed areas, arranges alignment mark respectively in described normal region and non-exposed areas; Perform Taiko technique; Location wafer, and device is formed on the normal region of wafer.
As preferably, after device is formed, remove the non-exposed areas of described wafer.
As preferably, locate described wafer by the alignment mark of non-exposed areas described in manual identified.
As preferably, described in the mode identification adopting machine recognition, the alignment mark of non-exposed areas is to locate wafer.
As preferably, the normal region of described wafer comprises multiple chip with same structure, and the region between adjacent chips is Cutting Road.
As preferably, in described Cutting Road, be provided with feeler switch.
As preferably, the mode adopting machine to coordinate with feeler switch locates wafer.
As preferably, the alignment mark of described non-exposed areas has one at least.
As preferably, the alignment mark of normal region is at least provided with one.
As preferably, described alignment mark is formed by etching, printing or laser.
Compared with prior art, a kind of wafer positioning method of the present invention, comprising: provide wafer, and this wafer comprises normal region and non-exposed areas, arranges alignment mark respectively in described normal region and non-exposed areas; Perform Taiko technique; Location wafer, and device is formed on the normal region of wafer.The present invention utilizes in Taiko technique the characteristic needing to retain wafer periphery marginal portion i.e. described non-exposed areas, in the normal region of wafer and non-exposed areas, alignment mark is set simultaneously, when carrying out Taiko technique, because the normal region of wafer is ground, thinning, the alignment mark of normal region is polished, shoal or disappear, and the alignment mark of non-exposed areas still retains, therefore by arranging alignment mark in non-exposed areas, not only can reduce the resistance value of the semiconductor power device being applied to automobile electronics, and the formation of subsequent device can be guaranteed, avoid because wafer is difficult to location and cause semiconductor power device yield low.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, more easily its adjoint advantage and feature will more easily be understood to the present invention by more complete understanding, wherein:
Fig. 1 diagrammatically illustrates the flow chart according to wafer positioning method of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.It should be noted that, accompanying drawing of the present invention all adopts the form of simplification and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
As shown in Figure 1, the invention provides a kind of wafer positioning method, specifically comprise the following steps:
Step 1: provide wafer, this wafer comprises normal region and non-exposed areas.Wherein, the normal region of described wafer is for follow-up region of carrying out exposing, being formed device; Described non-exposed areas is the marginal portion of wafer, within one week, arranges around described normal region, and without the need to forming device on it.In the present invention, after normal region place forms device, removal need be cut in this non-exposed areas.
Step 2: alignment mark is set respectively in the normal region of described wafer and non-exposed areas.Particularly, described alignment mark is used for follow-up aligning wafer, to form device at the fixed position place of wafer.Wherein, the generation type of described alignment mark has multiple, can be formed by etching, also can be formed by printing, can also be formed by laser.Certainly, the shape of described alignment mark also has multiple, and because this is prior art, and implementation has multiple, repeats no more herein.
Step 3: perform Taiko technique.Particularly, described Taiko technique is a kind of wafer rear grinding technique, and this technology is different with back side grinding in the past, and it is when carrying out grinding to wafer, will retain the edge 3 ~ 5mm of wafer periphery, namely only carries out grinding slimming to the normal region of wafer.By performing described Taiko technique, can be not only the thickness that wafer is thinned to automobile electronics requirement, can realize reducing the carrying risk of slim wafer and reducing the effect of warpage simultaneously.Particularly, Taiko technique, by staying limit in wafer periphery, reduces silicon wafer warpage, improves wafer intensity, and wafer uses more convenient, the through-hole mounting after slimming, and the first-class processing of configuration wiring is more convenient.In addition, when carrying out high-temperature process (plating etc.) after wafer slimming, degassed phenomenon is not had to occur, because be Construction integration, shape is single, can reduce particle and bring phenomenon into, without the need to using hard matrix etc., only rely on wafer self can maintain structure (shape); Have during grinding not in the advantage that outer peripheral areas is born a heavy burden, without the need to grinding outer peripheral areas, therefore Taiko technique is more convenient compared to other technique, and after Taiko technique, the angle phenomenon that collapses of wafer is zero.
Step 4: location wafer, and device is formed on the normal region of wafer.
Location wafer mode have multiple, a kind of mode for: by the alignment mark (being mainly the alignment mark of non-exposed areas) on wafer described in manual identified, thus location wafer.
Another kind of mode is the alignment mark by non-exposed areas described in machine recognition, to identify wafer.
Further, when non-exposed areas is compared with normal region, brightness when contrast difference is larger in other words, when machine is difficult to identify the alignment mark on non-exposed areas, can adopt feeler switch to locate wafer.Particularly, the normal region due to described wafer comprises multiple chip with same structure, and the adjacent region between two between chip is Cutting Road, is provided with feeler switch in described Cutting Road.Because the effect of the feeler switch between different chip is different, therefore, machine can by identifying that the feeler switch of normal region locates wafer.
That is, wafer is positioned with three kinds of modes, and one is by artificial location, and a kind of is simple machine location wafer, also has a kind of mode being machine coordinates with feeler switch to locate wafer.
Step 5: after device is formed, removes the non-exposed areas of described wafer, and that is, the non-exposed areas of crystal round fringes is removed in cutting.
As preferably, the alignment mark of described non-exposed areas and normal region is arranged has one at least, so that identify alignment mark, realizes width location wafer.
In sum, the invention provides a kind of wafer positioning method, comprising: provide wafer, this wafer comprises normal region and non-exposed areas, arranges alignment mark respectively in described normal region and non-exposed areas; Perform Taiko technique; Location wafer, and device is formed on the normal region of wafer.The present invention utilizes in Taiko technique the characteristic needing to retain wafer periphery marginal portion i.e. described non-exposed areas, in the normal region of wafer and non-exposed areas, alignment mark is set simultaneously, when carrying out Taiko technique, because the normal region of wafer is ground, thinning, the alignment mark of normal region is polished, shoal or disappear, and the alignment mark of non-exposed areas still retains, therefore by arranging alignment mark in non-exposed areas, not only can reduce the resistance value of the semiconductor power device being applied to automobile electronics, and the formation of subsequent device can be guaranteed, avoid because wafer is difficult to location and cause semiconductor power device yield low, thus the yield of semiconductor power device can be improved, and then reduction production cost.
In addition, it should be noted that, unless stated otherwise or point out, otherwise term " first " " second " in specification etc. describe only for distinguishing each assembly, element, step etc. in specification, instead of for representing logical relation between each assembly, element, step or ordinal relation etc.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a wafer positioning method, is characterized in that, comprising: provide wafer, and this wafer comprises normal region and non-exposed areas, arranges alignment mark respectively in described normal region and non-exposed areas; Perform Taiko technique; Location wafer, and device is formed on the normal region of wafer.
2. wafer positioning method as claimed in claim 1, is characterized in that, after device is formed, remove the non-exposed areas of described wafer.
3. wafer positioning method as claimed in claim 1, is characterized in that, locate described wafer by the alignment mark of non-exposed areas described in manual identified.
4. wafer positioning method as claimed in claim 1, is characterized in that, described in the mode identification of employing machine recognition, the alignment mark of non-exposed areas is to locate wafer.
5. wafer positioning method as claimed in claim 1, it is characterized in that, the normal region of described wafer comprises multiple chip with same structure, and the region between adjacent chips is Cutting Road.
6. wafer positioning method as claimed in claim 5, is characterized in that, be provided with feeler switch in described Cutting Road.
7. wafer positioning method as claimed in claim 6, is characterized in that, the mode adopting machine to coordinate with feeler switch locates wafer.
8. wafer positioning method as claimed in claim 1, it is characterized in that, the alignment mark of described non-exposed areas has one at least.
9. wafer positioning method as claimed in claim 1, it is characterized in that, the alignment mark of normal region is at least provided with one.
10. wafer positioning method as claimed in claim 1, is characterized in that, described alignment mark is formed by etching, printing or laser.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510189321.5A CN104795317A (en) | 2015-04-17 | 2015-04-17 | Wafer positioning method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510189321.5A CN104795317A (en) | 2015-04-17 | 2015-04-17 | Wafer positioning method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104795317A true CN104795317A (en) | 2015-07-22 |
Family
ID=53560040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510189321.5A Pending CN104795317A (en) | 2015-04-17 | 2015-04-17 | Wafer positioning method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104795317A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105374726A (en) * | 2015-10-22 | 2016-03-02 | 北京同方微电子有限公司 | Positioning method for packaging and picking up chips |
| CN105428220A (en) * | 2015-12-22 | 2016-03-23 | 上海华虹宏力半导体制造有限公司 | Annular cutting process method of Taiko thinning process |
| CN107452716A (en) * | 2016-05-25 | 2017-12-08 | 英飞凌科技股份有限公司 | For forming the method and semiconductor devices of semiconductor devices |
| CN113871455A (en) * | 2021-09-28 | 2021-12-31 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855381A (en) * | 2005-04-27 | 2006-11-01 | 株式会社迪斯科 | Semiconductor crystal plate and method for processing same |
| US7527547B2 (en) * | 2006-05-12 | 2009-05-05 | Disco Corporation | Wafer processing method |
| US7559826B2 (en) * | 2005-07-25 | 2009-07-14 | Disco Corporation | Processing method and grinding apparatus of wafer |
| CN103811407A (en) * | 2012-11-06 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Technique method for patterning back surface of silicon wafer |
| CN104517804A (en) * | 2014-07-29 | 2015-04-15 | 上海华虹宏力半导体制造有限公司 | Ring removing method of Taiko thinning process |
-
2015
- 2015-04-17 CN CN201510189321.5A patent/CN104795317A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855381A (en) * | 2005-04-27 | 2006-11-01 | 株式会社迪斯科 | Semiconductor crystal plate and method for processing same |
| US7559826B2 (en) * | 2005-07-25 | 2009-07-14 | Disco Corporation | Processing method and grinding apparatus of wafer |
| US7527547B2 (en) * | 2006-05-12 | 2009-05-05 | Disco Corporation | Wafer processing method |
| CN103811407A (en) * | 2012-11-06 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Technique method for patterning back surface of silicon wafer |
| CN104517804A (en) * | 2014-07-29 | 2015-04-15 | 上海华虹宏力半导体制造有限公司 | Ring removing method of Taiko thinning process |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105374726A (en) * | 2015-10-22 | 2016-03-02 | 北京同方微电子有限公司 | Positioning method for packaging and picking up chips |
| CN105374726B (en) * | 2015-10-22 | 2018-02-27 | 北京同方微电子有限公司 | A kind of localization method for encapsulating pickup chip |
| CN105428220A (en) * | 2015-12-22 | 2016-03-23 | 上海华虹宏力半导体制造有限公司 | Annular cutting process method of Taiko thinning process |
| CN105428220B (en) * | 2015-12-22 | 2017-12-05 | 上海华虹宏力半导体制造有限公司 | The ring cutting process of too bulging reduction process |
| CN107452716A (en) * | 2016-05-25 | 2017-12-08 | 英飞凌科技股份有限公司 | For forming the method and semiconductor devices of semiconductor devices |
| CN107452716B (en) * | 2016-05-25 | 2020-10-16 | 英飞凌科技股份有限公司 | Method for forming semiconductor device and semiconductor device |
| CN113871455A (en) * | 2021-09-28 | 2021-12-31 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
| CN113871455B (en) * | 2021-09-28 | 2023-08-18 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104795317A (en) | Wafer positioning method | |
| US11367701B2 (en) | Apparatus and method for securing substrates with varying coefficients of thermal expansion | |
| US10553489B2 (en) | Partitioned wafer and semiconductor die | |
| US8531042B2 (en) | Technique for fabricating microsprings on non-planar surfaces | |
| CN105720017A (en) | Fingerprint identification chip with enhanced electrostatic discharge protection, system and manufacturing method | |
| CN111199951A (en) | Semiconductor device, manufacturing method thereof and manufacturing method of alignment mark | |
| US20030215966A1 (en) | Circular test pads on scribe street area | |
| Albrecht et al. | Multi-chip patch in low stress polymer foils based on an adaptive layout for flexible sensor systems | |
| US10700041B2 (en) | Stacking of three-dimensional circuits including through-silicon-vias | |
| CN103928410B (en) | Encapsulating structure and preparation method thereof | |
| JP6740831B2 (en) | Semiconductor device | |
| EP4071828A1 (en) | Power device and method of manufacturing the same | |
| US20170338126A1 (en) | Systems and methods for fabricating a polycrystaline semiconductor resistor on a semiconductor substrate | |
| DE102016101452B4 (en) | Inspection of electronic chips through backlighting | |
| US20130240882A1 (en) | Die, wafer and method of processing a wafer | |
| US20220278068A1 (en) | Apparatus and method for securing substrates with varying coefficients of thermal expansion | |
| US20210125871A1 (en) | Systems and methods for precision fabrication of an orifice within an integrated circuit | |
| CN111769051A (en) | Positioning method for packaging patch | |
| US9412637B2 (en) | Device wafer processing method | |
| US20210349392A1 (en) | Method for creation of different designs by combining a set of pre-defined disjoint masks | |
| CN106298493A (en) | Method for manufacturing semiconductor device | |
| TW202005047A (en) | Stacked wafer integrated circuit | |
| CN115424970B (en) | Semiconductor package alignment method and semiconductor package structure | |
| CN106206726A (en) | Power metal oxide semiconductor field effect transistor and manufacturing method thereof | |
| US11329021B2 (en) | Method for fabricating a semiconductor device comprising a paste layer and semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150722 |
|
| RJ01 | Rejection of invention patent application after publication |