CN104779282A - Trench-type power metal oxide semiconductor field effect transistor and manufacturing method thereof - Google Patents
Trench-type power metal oxide semiconductor field effect transistor and manufacturing method thereof Download PDFInfo
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- CN104779282A CN104779282A CN201410010625.6A CN201410010625A CN104779282A CN 104779282 A CN104779282 A CN 104779282A CN 201410010625 A CN201410010625 A CN 201410010625A CN 104779282 A CN104779282 A CN 104779282A
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- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 42
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000002353 field-effect transistor method Methods 0.000 title 1
- 230000005669 field effect Effects 0.000 claims abstract description 44
- 239000011248 coating agent Substances 0.000 claims description 73
- 238000000576 coating method Methods 0.000 claims description 73
- 239000011159 matrix material Substances 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 15
- 230000004888 barrier function Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 230000005684 electric field Effects 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 210000000746 body region Anatomy 0.000 abstract description 3
- 238000009826 distribution Methods 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 5
- 230000009467 reduction Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 206010020718 hyperplasia Diseases 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The invention discloses a trench-type power metal oxide semiconductor field effect transistor and a manufacturing method thereof. An embedded oxide layer is formed in an epitaxial layer of the trench-type power metal oxide semiconductor field effect transistor and located below a body region, and thus, longitudinal electric field distribution is changed, disruptive voltage of the transistor is improved, and low on-resistance can be obtained. According to the trench-type power metal oxide semiconductor field effect transistor and the manufacturing method thereof, the embedded oxide layer formed in the epitaxial layer is used for changing the longitudinal electric field distribution, the disruptive voltage of an element is thus improved, silicon limitation can be broken, and low on-resistance can be obtained.
Description
Technical field
The present invention relates to a kind of power MOSFET transistor, particularly relate to a kind of trench power metal-oxide semiconductor field-effect transistor and its manufacture method with low conduction impedance and high breakdown voltage.
Background technology
Power metal oxide field-effect transistor (Power Metal Oxide SemiconductorField Transistor, Power MOSFET) be a kind of voltage controlled element, mainly contain horizontal and rectilinear two kinds of structures, it has, and switching speed is fast, high frequency characteristics is good, input impedance is high with the advantage such as driving power is little.Power metal oxide field-effect transistor is widely used in the switching device of electric device, such as, be power supply unit, rectifier or low voltage motor controller etc.Power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) now takes the design of vertical stratification more, with lift elements density.
The work-loss costs of power metal oxide field-effect transistor can be divided into switch cost (switchingloss) and the large class of conduction losses (conducting loss) two, and the conducting resistance Rds wherein under transistor turns state (ON) is the important parameter affecting work-loss costs.Conducting resistance Rds is less, and the conduction losses of transistor is less, and power consumption is lower.The conducting resistance Rds of power metal oxide field-effect transistor is usually relevant to the thickness of drift region, and the thickness reducing drift region can reduce conductive resistance Rds, but the thickness reducing drift region can cause breakdown voltage reduce and affect the voltage endurance of transistor.
Summary of the invention
The invention provides a kind of groove-type power type burning field-effect transistor and its manufacture method, it utilizes and reduces surface field (reduced surface field, RESURF) technology arranges oxide skin(coating) to increase breakdown voltage in matrix region (body region) below, obtains lower conducting resistance whereby under identical breakdown voltage characteristic.
The embodiment of the present invention proposes a kind of trench power metal-oxide semiconductor field-effect transistor, comprises a base material, an epitaxial layer, monoxide layer, a channel region, a matrix region, one second heavily doped region and a trench gate structure.Base material has one first heavily doped region; Epitaxial layer is formed at above base material, wherein has a drift region in epitaxial layer; Oxide skin(coating) is formed at above drift region; Channel region is formed at the side of oxide skin(coating); Matrix region is formed at above oxide skin(coating) and channel region, and wherein channel region connects matrix region and drift region; Second heavily doped region is formed at above matrix region; First trench gate structure is formed at the side of the second heavily doped region and matrix region.Wherein, channel region is between trench gate structure and oxide skin(coating).
Better, wherein the width of channel region is less than the width of this oxide skin(coating).
Better, wherein channel region and drift region are N-type doped region, and matrix region is P type doped region, and the first heavily doped region and the second heavily doped region are N-type doped region.
Better, wherein oxide skin(coating), channel region, matrix region, second heavily mixes district and the first trench gate structure is formed in this epitaxial layer, and the first trench gate structure may extend among drift region.
The present invention also proposes a kind of manufacture method of trench power metal-oxide semiconductor field-effect transistor, and comprising the following steps: provides a substrate; Form an epitaxial layer in surface, and in epitaxial layer, form a drift region and monoxide layer, wherein oxide skin(coating) is positioned at above drift region; Form a trench gate structure and a channel region in epitaxial layer, wherein channel region is between oxide skin(coating) and trench gate structure; Form a matrix region above oxide skin(coating) and channel region, wherein channel region connects matrix region and drift region; And form a heavily doped region above matrix region.
Better, in the step of above-mentioned formation epitaxial layer, comprise the following steps: to be formed epitaxial layer on substrate; Form a main oxide skin(coating) above once epitaxial layer; Etch main oxide layer to form multiple section, wherein one of those sections form oxide skin(coating); And lower epitaxial layer is upwards grown up increase thickness to form epitaxial layer with capping oxidation nitride layer.
In sum, trench power metal-oxide semiconductor field-effect transistor of the present invention and its manufacture method utilize the oxide skin(coating) forming a flush type in epitaxial layer to distribute to change longitudinal electric field, improve the breakdown voltage of element whereby, so silicon restriction (silicon limitation) can be broken through, obtain lower conducting resistance.
In order to above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate accompanying drawing, be described in detail below.
Accompanying drawing explanation
Figure 1A ~ Fig. 1 H is the manufacture method schematic diagram of trench power metal-oxide semiconductor field-effect transistor of the present invention;
Fig. 2 is the manufacture method flow chart of trench power metal-oxide semiconductor field-effect transistor of the present invention;
Fig. 3 is the partial structurtes schematic diagram of trench power metal-oxide semiconductor field-effect transistor of the present invention.
[description of reference numerals]
Substrate 110
Lower epitaxial layer 119
Epitaxial layer 120
Main oxide skin(coating) 130
Oxide skin(coating) 131,132,133
Channel grid structure 150,155
Conductive grid 151
Insulating barrier 152
Groove 153
Second heavily doped region 160
Matrix region 170
First channel region 181
Second channel region 182
Flow chart step S210 ~ S250
Trench power metal-oxide semiconductor field-effect transistor 300
Drift region 310
First heavily doped region 320
Embodiment
Hereinafter, will illustrate that embodiments of the invention are to describe the present invention in detail by accompanying drawing, and the same reference numbers in accompanying drawing can in order to element like representation class.Aforementioned and other technology contents, feature and effect for the present invention, in the following detailed description coordinated with reference to each embodiment of accompanying drawing, can clearly present.The direction term mentioned in following examples such as: (on), (under), (front), (afterwards), (left side), (right side) etc., is only the direction with reference to accompanying drawing.Therefore, the direction term of use is used to illustrate, and is not used for limiting this patent.Further, in following each embodiment, adopt identical label to represent identical or approximate element.
Figure 1A ~ Fig. 1 H is the manufacture method schematic diagram of trench power metal-oxide semiconductor field-effect transistor of the present invention.As shown in Figure 1A, first, one substrate 110 is provided, then on substrate 110, form lower epitaxial layer (epitaxial layer) 119, wherein substrate 110 is such as silicon substrate (siliconsubstrate), its first heavily doped region with high-dopant concentration is using the drain electrode (drain) as trench power metal-oxide semiconductor field-effect transistor, and lower epitaxial layer 119 is low doping concentration, and it can form the drift region of trench power metal-oxide semiconductor field-effect transistor.
For example, substrate 110 can local or whole substrate be all heavily doped region to determine the region of drain electrode.The present embodiment is that the first heavily doped region illustrates for whole substrate 110, but the present embodiment is not restricted to this.Lower epitaxial layer 119 is identical with the doping type of substrate 110, but the doping content of lower epitaxial layer 119 is less than the doping content of substrate 110.For N-type transistor, substrate 110 is the N-type doping (N of high concentration
+), lower epitaxial layer 119 is then the N-type doping (N of low concentration
-).Otherwise for PMOS, substrate 110 is the P type doping (P of high concentration
+doping), lower epitaxial layer 119 is then the P type doping (P of low concentration
-doping).In trench power metal-oxide semiconductor field-effect transistor, drain electrode is formed at substrate 110, source electrode is then formed at the upper surface of epitaxial layer, and grid is then formed in the groove of epitaxial layer, and wherein epitaxial layer can directly upwards be grown up to increase after thickness by lower epitaxial layer 119 and realized.
Then, with reference to Figure 1B and Fig. 1 C, directly with mode of oxidizing, above lower epitaxial layer 119, form main oxide skin(coating) 130, and form multiple section to form the oxide skin(coating) 131,132,133 of multiple separation via etching.Fig. 1 C illustrates for three regions, and namely oxide skin(coating) 132 is made up of one of them region, but in the present embodiment, main oxide skin(coating) 130 can form multiple section to form oxide skin(coating) at diverse location simultaneously according to demand etching.Oxide skin(coating) 131,132,133 is such as silicon dioxide (SiO
2).Then, as shown in figure ip, with selectivity (selective epitaxial growth) manufacturing process of heap of stone brilliant, lower epitaxial layer 119 is made to continue upwards to grow up and increase thickness with capping oxidation nitride layer 131,132,133 and form epitaxial layer 120, as referring to figure 1e.Oxide skin(coating) 131,132,133 can be covered by the epitaxial layer 120 after hyperplasia and form the oxide skin(coating) of flush type.Then as referring to figure 1e, build the brilliant rear epitaxial layer 120 formed to selectivity and carry out surface planarisation manufacturing process, its mode is such as utilize chemical mechanical milling method (Chemical Mechanical Polishing/Planarization; As shown in fig. 1f, but the mode of the present embodiment not limiting surface planarization manufacturing process CMP).
In the present embodiment, as shown in fig. 1f, the epitaxial layer 120 utilizing twice manufacturing process to be formed can be considered single epitaxial layer 120, and the epitaxial layer that its function can be used as trench power metal-oxide semiconductor field-effect transistor uses.To make oxide skin(coating) 131,132,133 be embedded among epitaxial layer 120 with the main cause that selectivity is built brilliant mode and increased lower epitaxial layer 119 thickness.In an alternative embodiment of the invention, lower epitaxial layer 119 directly can grow to required height to form epitaxial layer 120, then multiple groove is etched, form oxide skin(coating) 131,132,133 at its bottom portion of groove, above oxide skin(coating) 131,132,133, then carry out selectivity build brilliant manufacturing process with capping oxidation nitride layer 131,132,133.Therefore, the present embodiment does not limit the mode of the oxide skin(coating) 131,132,133 forming built-in type, does not limit the manufacture method forming epitaxial layer with two-part, as long as can form the oxide skin(coating) 131,132,133 of built-in type yet.
From the above, the step major function of Figure 1B ~ Fig. 1 F is in epitaxial layer 120, form oxide skin(coating) 131,132,133, and be located at the top of drift region, the first half of epitaxial layer 120 then can be used for being formed all the other structures of power transistor, as grid structure, source electrode, matrix region etc.
Please refer to Fig. 1 G, then, in epitaxial layer 120, form multiple groove 153, then respectively at forming channel grid structure 150,155 in groove 153.Channel grid structure 150 is made up of insulating barrier 152 and conductive grid 151, and its insulating barrier 152 is positioned at the madial wall of groove 153, in order to isolate conductive grid 151 and epitaxial layer 120.Insulating barrier 152 is such as silicon dioxide, and conductive grid 151 be such as polysilicon gate or conducting metal can.
Trench power metal-oxide semiconductor field-effect transistor has multiple channel grid structure 150,155, and wherein oxide skin(coating) 132 is between channel grid structure 150 and channel grid structure 155.Gap-forming first channel region 181 between oxide skin(coating) 132 and channel grid structure 150, and the gap-forming second channel region 182 between oxide skin(coating) 132 and channel grid structure 155.Above-mentioned two channel regions 181,182 are formed at the both sides of oxide skin(coating) 132, and use as the current channel between source class and drain electrode, its material is identical with epitaxial layer 120.
Please refer to Fig. 1 H, utilize doping manufacturing process, matrix region (body region) 170 and the second heavily doped region 160 is formed above oxide skin(coating) 132, matrix region 170 is between oxide skin(coating) 132 and the second heavily doped region 160, wherein the second heavy doping is driven 160 and be can be used as source electrode, and matrix region 170 is the substrate of transistor.The Main Differences of matrix region 170 and the second heavily doped region 160 is the semi-conductor type of doping content and doping.For nmos pass transistor, the second heavily doped region 160 is N-type doping, and matrix region 170 is P type doping (as p type wells, P-well).The doping content of matrix region 170 is less than the doping content of the second heavily doped region 160.
Oxide skin(coating) 132 is a built-in type structure, the bottom of its next-door neighbour matrix region 170.In more detail, oxide skin(coating) 132 is positioned at matrix region 170 and sentences with the junction of epitaxial layer 120 the longitudinal electric field intensity that reduction is positioned at PN junction (PN junction), improves the breakdown voltage of element whereby.Oxide skin(coating) 132 can form one and reduce surface field structure (RESURF structure) below matrix region 170, so as to improving the breakdown voltage of transistor.In like manner, oxide skin(coating) 131,133 is positioned at below corresponding matrix region separately, change its Electric Field Distribution state whereby, form the RESURF structure that longitudinal electric field intensity is reduced, utilize RESURF technology improve trench power metal-oxide semiconductor field-effect transistor source drain between breakdown voltage (Drain-SourceBreakdown Voltage, BVdss).By the reduction surface field structure that oxide skin(coating) 131,132,133 is formed, the trench power metal-oxide semiconductor field-effect transistor of the present embodiment can be made to have higher source-drain electrodes breakdown voltage, and under identical breakdown voltage characteristic, obtain relatively low source-drain electrodes conducting resistance (Drain-Source On-state Resistance, Rdson, is called for short conducting resistance).
Further illustrate, rectilinear power transistor can improve breakdown voltage by the doping content of the thickness or reduction matrix region 170 that increase drift region, but the thickness increasing drift region or the doping content reducing matrix region 170 can make the conducting resistance of power transistor improve, and this can cause the loss of power switched.But, by the setting of oxide skin(coating) 131,132,133, can make power transistor at identical built crystal layer thickness with under identical doping content, obtain higher source drain breakdown voltage, breakthrough silicon limits (silicon limitation) whereby.That is, under identical breakdown voltage requires, the power transistor structure of the present embodiment can obtain lower conducting resistance.Above-described embodiment can summarize a kind of manufacture method of trench power metal-oxide semiconductor field-effect transistor, and as shown in Figure 2, Fig. 2 is the manufacture method flow chart of trench power metal-oxide semiconductor field-effect transistor of the present invention.As shown in Figure 2, first manufacture method comprises the following steps:, provides a substrate (S210); Then, form an epitaxial layer on substrate, and form drift region and oxide skin(coating) at epitaxial layer, wherein oxide skin(coating) is positioned at (S220) above drift region; Then, a trench gate structure and a channel region is formed in epitaxial layer, wherein channel region (S230) between oxide skin(coating) and trench gate structure; Then, form a matrix region above oxide skin(coating) and channel region, wherein channel region connects matrix region and drift region (S240); Then, a heavily doped region (S250) above matrix region is formed.
In the present invention, in above-mentioned S220, the step wherein forming epitaxial layer more comprise the following steps: to be formed epitaxial layer on substrate; Form a main oxide skin(coating) above once epitaxial layer; Main oxide etch is become multiple section, wherein one of those sections forms oxide skin(coating); And lower epitaxial layer is upwards grown up increase thickness to form complete epitaxial layer with capping oxidation nitride layer.Aforesaid way is the wherein a kind of mode realizing built-in type oxide skin(coating), and the present invention is not restricted to this.
It should be noted that, a trench power metal-oxide semiconductor field-effect transistor can comprise multiple oxide skin(coating), lay respectively between corresponding matrix region and drift region, these oxide skin(coating)s can utilize above-mentioned S220 to be formed simultaneously, or repeatedly carrying out S220 is formed respectively.Diverse location.In S230, can form multiple trench gate structure and multiple corresponding channel region, other channel region individual lays respectively between corresponding trench gate structure and oxide skin(coating) to use as current path simultaneously.Multiple channel region then can be used for reducing the conducting resistance of power transistor.
Above-mentioned S210 ~ S250 can according to manufacturing process demand adjustment sequencing, and such as S230 and S240 can exchange, and the present embodiment does not limit the order of above-mentioned S210 ~ S250.The implementation detail of above-mentioned S210 ~ S250 is specified in the explanation of above-mentioned Figure 1A ~ Fig. 1 H and other embodiments of the invention, does not add repeat at this.
Please refer to Fig. 3, Fig. 3 is the partial structurtes schematic diagram of trench power metal-oxide semiconductor field-effect transistor of the present invention.Substrate 110 has the first heavily doped region 320, as the drain electrode of trench power metal-oxide semiconductor field-effect transistor 300.First heavily doped region 320 can be local or the whole substrate 110 of substrate 110, is the first heavily doped region 320 explanation for whole substrate 110 in the present embodiment.There is in epitaxial layer 120 second heavily doped region 160, matrix region 170, oxide skin(coating) 132, first channel region 181, second channel region 182 and drift region 310.Second heavily doped region 160 is as the source electrode of trench power metal-oxide semiconductor field-effect transistor 300, and matrix region 170 is between the second heavily doped region 160 and oxide skin(coating) 132.First channel region 181, second channel region 182 and oxide skin(coating) 132 between matrix region 170 and drift region 310, in order to matrix region, interval 170 and drift region 310.First channel region 181 and second channel region 182 are positioned at the both sides of oxide skin(coating) 132, connect matrix region 170 and drift region 310, in order to provide two current paths to reduce conducting resistance.That is, matrix region 170 is connected to drift region 310 via the first channel region 181 and second channel region 182 and can via the first channel region 181 and second channel region 182 On current.First channel region 181 and the width in second channel region 182 can affect impedance during conducting, and its width can be arranged according to demand, such as, be less than the width of oxide skin(coating) 132.
For N-type power transistor, substrate 110 is N-type doped region (the i.e. heavily doped region N of heavy dopant concentration
+) to form the first heavily doped region, the first channel region 181 and second channel region 182 are N-type doped region (the i.e. light doping section N of low doping concentration
-).Epitaxial layer 120 below oxide skin(coating) 132 is that the N-type doped region of low doping concentration is to form drift region 310.The doped region that drift region 310 also can utilize the mode of ion implantation to form local below oxide skin(coating) 132 is formed.In the present embodiment, the epitaxial layer 120 below oxide skin(coating) 132 is that the N-type doped region of low doping concentration is to form drift region 310.Matrix region 170 is the P type doped region of low doping concentration, and the second heavily doped region 160 is then that the N-type doped region of high-dopant concentration is to form source electrode.Trench gate structure 150,155 is formed in the groove of epitaxial layer 120, and it can extend downward in drift region 310 according to design requirement.Trench gate structure 150,155 is positioned at the both sides of oxide skin(coating) 132, and the first channel region 181 and second channel region 182 are then formed between trench gate structure 150,155 and oxide skin(coating) 132 respectively.
Generally speaking, in the semiconductor of high-dopant concentration, the concentration ratio of alloy and semiconductor atom is about one thousandth, and low doping concentration then may to the ratio of part per billion, and its ratio can be determined according to different element demands, and the present embodiment is not limited.The mode of doping is such as utilize ionic-implantation (Ion Implantation) and thermal diffusion method (Diffusion).
Complete groove type gold oxygen half field effect power transistor be by multiple construction unit as Fig. 3 form to increase width and the On current of passage, the partial structurtes of Fig. 3 position groove type gold oxygen half field effect power transistor.Via the explanation of above-described embodiment, those of ordinary skill in the art should know all the other structure implementation details easily by inference, do not add repeat at this.
In sum, trench power metal-oxide semiconductor field-effect transistor of the present invention utilizes reduction surface field technology to be to form built-in type oxide skin(coating) below matrix region to reduce longitudinal electric field intensity.This reduction surface field structure can improve the breakdown voltage of transistor, so can break through silicon restriction, under identical structure, obtains lower on-resistance characteristics.
Although embodiments of the invention have disclosed as above; but the present invention is not limited to above-described embodiment; any those of ordinary skill in the art; not departing from the scope disclosed by the present invention; when doing a little change and adjustment, what therefore protection scope of the present invention should define with right is as the criterion.
Claims (9)
1. a trench power metal-oxide semiconductor field-effect transistor, is characterized in that, comprising:
One base material, has one first heavily doped region;
One epitaxial layer, is formed at above this base material, wherein has a drift region in this epitaxial layer;
Monoxide layer, is formed at above this drift region;
One channel region, is formed at the side of this oxide skin(coating);
One matrix region, be formed at above this oxide skin(coating) and this channel region, wherein this channel region connects this matrix region and this drift region;
One second heavily doped region, is formed at above this matrix region; And
One trench gate structure, is formed at the side of this second heavily doped region and this matrix region;
Wherein, this channel region is between this trench gate structure and this oxide skin(coating).
2. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 1, it is characterized in that, the width of this channel region is less than the width of this oxide skin(coating).
3. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 1, it is characterized in that, this channel region and this drift region are N-type doped region, and this matrix region is P type doped region, and this first heavily doped region and this second heavily doped region are N-type doped region.
4. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 1, it is characterized in that, this trench gate structure extends among this drift region.
5. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 1, it is characterized in that, this oxide skin(coating), this channel region, this matrix region, this second heavily mixes district and this trench gate structure is formed in this epitaxial layer.
6. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 1, it is characterized in that, this trench gate structure is formed in a groove of this epitaxial layer, and this trench gate structure comprises:
One insulating barrier, is formed at the madial wall of this groove; And
One conductive grid, is formed in this groove, and this insulating barrier is between this conductive grid and this epitaxial layer.
7. a manufacture method for trench power metal-oxide semiconductor field-effect transistor, is characterized in that, comprising:
One substrate is provided;
Form an epitaxial layer in this surface, and in this epitaxial layer, form a drift region and monoxide layer, wherein this oxide skin(coating) is positioned at above this drift region;
Form a trench gate structure and a channel region in this epitaxial layer, wherein this channel region is between this oxide skin(coating) and this trench gate structure;
Form a matrix region above this oxide skin(coating) and this channel region, wherein this channel region connects this matrix region and this drift region; And
Form a heavily doped region above this matrix region.
8. the manufacture method of trench power metal-oxide semiconductor field-effect transistor as claimed in claim 7, it is characterized in that, this channel region and this drift region are N-type doped region, and this matrix region is P type doped region, and this heavily doped region is that N-type mixes district.
9. the manufacture method of trench power metal-oxide semiconductor field-effect transistor as claimed in claim 7, is characterized in that, comprises in the step forming this epitaxial layer:
Formed epitaxial layer on this substrate;
Form a main oxide skin(coating) above once epitaxial layer;
Etch this main oxide layer to form multiple section, wherein one of those sections form this oxide skin(coating); And
This lower epitaxial layer is upwards grown up increases thickness to cover this oxide skin(coating) and to form this epitaxial layer.
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| EP0580213A1 (en) * | 1992-07-23 | 1994-01-26 | SILICONIX Incorporated | High voltage transistor having edge termination utilizing trench technology |
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| JP2008140805A (en) * | 2006-11-30 | 2008-06-19 | Sanyo Electric Co Ltd | Semiconductor device |
| CN101542741A (en) * | 2007-09-28 | 2009-09-23 | 三洋电机株式会社 | Trench gate type transistor and method for manufacturing the same |
| WO2009144640A1 (en) * | 2008-05-28 | 2009-12-03 | Nxp B.V. | Trench gate semiconductor device and method of manufacturing thereof. |
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2014
- 2014-01-10 CN CN201410010625.6A patent/CN104779282B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0580213A1 (en) * | 1992-07-23 | 1994-01-26 | SILICONIX Incorporated | High voltage transistor having edge termination utilizing trench technology |
| US6177704B1 (en) * | 1997-09-26 | 2001-01-23 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Semiconductor device containing a lateral MOS transistor |
| US20050253187A1 (en) * | 2004-03-31 | 2005-11-17 | Kabushiki Kaisha Toshiba | Semiconductor device |
| JP2008140805A (en) * | 2006-11-30 | 2008-06-19 | Sanyo Electric Co Ltd | Semiconductor device |
| CN101542741A (en) * | 2007-09-28 | 2009-09-23 | 三洋电机株式会社 | Trench gate type transistor and method for manufacturing the same |
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