CN104778098A - Memory mirroring method and system and memory monitor - Google Patents
Memory mirroring method and system and memory monitor Download PDFInfo
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- CN104778098A CN104778098A CN201510163863.5A CN201510163863A CN104778098A CN 104778098 A CN104778098 A CN 104778098A CN 201510163863 A CN201510163863 A CN 201510163863A CN 104778098 A CN104778098 A CN 104778098A
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Abstract
The invention provides a memory mirroring method and system and a memory monitor. The method comprises the following steps: presetting a mirroring memory interval corresponding to a mirrored memory interval; S1, determining an access message for performing write operation on the mirrored memory interval; S2, determining an accessed memory address according to the access message; S3, reading data from the memory address, and writing the data into the mirroring memory interval. By adopting the memory mirroring method and system and the memory monitor provided by the invention, the mirror memory can be set flexibly.
Description
Technical field
The present invention relates to field of computer technology, particularly a kind of method and system, a kind of internal memory monitoring device of memory mirror.
Background technology
System reliability corresponds to the server-type computing machine of enterprise's bussiness class, has vital effect.And namely memory mirror is the very effective means realizing reliability.Data, the spitting image of disk mirroring, are written to two simultaneously and independently configure in identical RAM (random access memory) card by the principle of work of memory mirror exactly, and when system is normally run, internal storage data reads and only carries out in the RAM (random access memory) card activated.If be enough to the soft fault causing system alarm in an internal memory, this memory bar of the frequent Reports Administration person of system will be out of order, or whole memory bar all will thoroughly damage, server will automatically be switched to mirror memory card, until out of order internal memory is replaced.
In prior art, usually there is multiple processor, each processor is loaded with internal memory in a computer system, the Memory Controller Hub of processor can operate the internal memory loaded with this processor.And processor only supports to be positioned at the memory mirror within same processor, and do not support the memory mirror between processor.That is, a processor generally can load several pieces of internal memories, processor load internal memory mirror memory also must its load several pieces of internal memories in, in the internal memory that mirror memory can not load at other processors.When processor conducts interviews to loading internal memory, the data of access are written in the mirror memory of this internal memory by the Memory Controller Hub of this processor.For example, processor A is loaded with 4 pieces of internal memories, processor B is loaded with 4 pieces of internal memories, wherein, the internal memory 1 of processor A and internal memory 2 are internal memories that processor A normally uses, the internal memory 1 of processor A and the mirror memory of internal memory 2 can be internal memory 3 and the internal memory 4 of processor A, and can not be the internal memory that processor B loads.
Visible by foregoing description, the method for memory mirror in prior art, in the internal memory that the mirror memory of the internal memory that processor loads can only load at this processor, mirror memory can not be arranged flexibly.
Summary of the invention
In view of this, the invention provides a kind of method and system of memory mirror, a kind of internal memory monitoring device, mirror memory can be set flexibly.
First aspect, the invention provides a kind of method of memory mirror, comprising: pre-set and be mirrored mirror memory interval corresponding between memory field, also comprise:
S1: determine to be mirrored the access message of carrying out write operation between memory field to described;
S2: determine the memory address of accessing according to described access message;
Described data are written to described mirror memory interval by S3: read data from described memory address.
Further, described S1 comprises:
According to described consistance message, A1: receive the consistance message carrying out internal storage access, judges whether current memory access is write operation, if so, then performs steps A 2, otherwise, terminate current process;
A2: obtain reference address from described consistance message, judges described reference address is mirrored between memory field described in whether belonging to, and if so, then performs step S2, otherwise, terminate current process;
Wherein, described access message comprises: described consistance message.
Further, described in pre-set that to be mirrored between memory field corresponding mirror memory interval, comprising:
In advance described being mirrored to be set between the first memory field that first processor loads between memory field, described mirror memory interval to be set between the second memory field that the second processor loads.
Further, after described S3, also comprise:
B1: determine to switch with described mirror memory interval described being mirrored between memory field;
B2: be silent status by the described Operation system setting being mirrored internal memory place;
B3: be mirrored between memory field interval with described mirror memory described in switching;
B4: the silent status removing described system.
And/or described B3, comprising:
The address between memory field is mirrored described in being revised as the address in described mirror memory interval by memory decoder.
Second aspect, the invention provides a kind of internal memory monitoring device, comprising:
Setting unit, is mirrored mirror memory interval corresponding between memory field for arranging;
First determining unit, is mirrored the access message of carrying out write operation between memory field for determining to described;
Second determining unit, for determining the memory address of accessing according to described access message;
Described data, for reading data from described memory address, are written to described mirror memory interval by writing unit.
Further, described first determining unit, comprising:
According to described consistance message, first judging unit, for receiving the consistance message carrying out internal storage access, judges whether current memory access is write operation, when judged result is for being, notifies the second judging unit;
Second judging unit, for obtaining reference address from described consistance message, judging described reference address is mirrored between memory field described in whether belonging to, when judged result is for being, notifying described second determining unit;
Wherein, described access message comprises: described consistance message.
Further, described setting unit, for being set between the first memory field that first processor loads between memory field by described being mirrored, is set to described mirror memory interval between the second memory field that the second processor loads.
Further, also comprise:
3rd determining unit, switches with described mirror memory interval described being mirrored between memory field for determining;
To mourn in silence unit, for being silent status by the described Operation system setting being mirrored internal memory place;
Switch unit, interval with described mirror memory for being mirrored described in switching between memory field;
Lifting unit, for removing the silent status of described system.
And/or described switch unit, for being mirrored the address between memory field described in being revised as the address in described mirror memory interval by memory decoder.
The third aspect, the invention provides a kind of system of memory mirror, comprising:
At least one processor, internal memory monitoring device as described in claim 5-8;
Described internal memory monitoring device is connected with each processor;
Described processor, for sending described access message to described internal memory monitoring device.
Further, described internal memory monitoring device is connected by the interconnected QPI bus of express passway with each processor.
By the method and system of a kind of memory mirror provided by the invention, a kind of internal memory monitoring device, pre-set and be mirrored mirror memory interval corresponding between memory field, this mirror memory interval can be between intrasystem any memory field at its place, can be between memory field that in this system, arbitrary processor loads, when determining that current access message conducts interviews to being mirrored internal memory, and current access is when being the write operation to internal memory, the memory address of access is determined from access message, data are read from this memory address, the data of reading are written in corresponding mirror memory interval, realize memory mirror, the method of this memory mirror is not by the restriction of position between memory field, can using interval as mirror memory between memory field arbitrary in system, mirror memory can be set flexibly.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the process flow diagram of the method for a kind of memory mirror that one embodiment of the invention provides;
Fig. 2 is the process flow diagram of the method for the another kind of memory mirror that one embodiment of the invention provides;
Fig. 3 is the schematic diagram of a kind of internal memory monitoring device that one embodiment of the invention provides;
Fig. 4 is the schematic diagram of the another kind of internal memory monitoring device that one embodiment of the invention provides;
Fig. 5 is the schematic diagram of the system of a kind of memory mirror that one embodiment of the invention provides;
Fig. 6 is the schematic diagram that in the system of a kind of memory mirror that one embodiment of the invention provides, consistance message sends.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly; below in conjunction with the accompanying drawing in the embodiment of the present invention; technical scheme in the embodiment of the present invention is clearly and completely described; obviously; described embodiment is the present invention's part embodiment, instead of whole embodiments, based on the embodiment in the present invention; the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not making creative work, all belongs to the scope of protection of the invention.
As shown in Figure 1, embodiments provide a kind of method of memory mirror, the method can comprise the following steps:
S0: pre-set and be mirrored mirror memory interval corresponding between memory field;
S1: determine to be mirrored the access message of carrying out write operation between memory field to described;
S2: determine the memory address of accessing according to described access message;
Described data are written to described mirror memory interval by S3: read data from described memory address.
The method of a kind of memory mirror provided by the embodiment of the present invention, pre-set and be mirrored mirror memory interval corresponding between memory field, this mirror memory interval can be between intrasystem any memory field at its place, can be between memory field that in this system, arbitrary processor loads, when determining that current access message conducts interviews to being mirrored internal memory, and current access is when being the write operation to internal memory, the memory address of access is determined from access message, data are read from this memory address, the data of reading are written in corresponding mirror memory interval, realize memory mirror, the method of this memory mirror is not by the restriction of position between memory field, can using interval as mirror memory between memory field arbitrary in system, mirror memory can be set flexibly.
According to Computer Organization Principles, need between all processors to keep cache consistance, when internal storage access occurs, can along with the generation of consistance message.Arrange system, when each internal storage access is occurred, the Memory Controller Hub in processor sends consistance message to each processor and internal memory monitoring device.In a kind of possible implementation, access message can be realized by consistance message, and described access message comprises: consistance message.Described S1 comprises:
According to described consistance message, A1: receive the consistance message carrying out internal storage access, judges whether current memory access is write operation, if so, then performs steps A 2, otherwise, terminate current process.
A2: obtain reference address from described consistance message, judges described reference address is mirrored between memory field described in whether belonging to, and if so, then performs step S2, otherwise, terminate current process.
In a kind of possible implementation, described S0 comprises:
In advance described being mirrored to be set between the first memory field that first processor loads between memory field, described mirror memory interval to be set between the second memory field that the second processor loads.
In addition, can in computer system design mistake testing mechanism, when reading internal memory generation mortality mistake, need switching to be mirrored between memory field interval with mirror memory, then triggered interrupts, system enters interrupt service routine.Particularly, after described S3, also comprise:
B1: determine to switch with described mirror memory interval described being mirrored between memory field;
B2: be silent status by the described Operation system setting being mirrored internal memory place;
B3: be mirrored between memory field interval with described mirror memory described in switching;
B4: the silent status removing described system.
In this implementation, be silent status by Operation system setting before handover, make processor break-off, after the handover, the silent status of deactivation system, makes processor resume work.
After B1, triggered interrupts signal, step B2-B4 can be realized by interrupt service routine.
Wherein, described B3, comprising: be mirrored the address between memory field described in being revised as the address in described mirror memory interval by memory decoder.For example, the address be mirrored between memory field is 1G-2G, and the address in corresponding mirror memory interval is 5G-6G, when switching, by memory decoder, the address 5G-6G in mirror memory interval is revised as the address 1G-2G be mirrored between memory field.
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with drawings and the specific embodiments, the present invention is described in further detail.
As shown in Figure 2, embodiments provide a kind of method of memory mirror, the method can comprise the following steps:
Step 201: the mirror memory in advance A between memory field being set to internal memory interval B is interval.
Step 201 is a kind of implementations of following step:
Pre-set and be mirrored mirror memory interval corresponding between memory field, wherein, between memory field, A is that mirror memory is interval, and internal memory interval B is mirrored between memory field.
Between memory field, A and internal memory interval B are between the arbitrary memory field in the system at its place, not by the restriction of their processor of loading, can arrange flexibly.
Step 202: receiving processor carries out the consistance message that internal storage access sends.
Processor in systems in which is internally deposited and is conducted interviews, and have issued consistance message.
Step 203: determine that the access mode that the current memory of processor is accessed is write operation according to consistance message.
When writing data in internal memory interval, needing to back up the data of write, that is, needing to write identical data in mirror memory interval.For example, be written with data S in internal memory interval B, then between memory field, A also will write data S, realizes memory mirror.
When not writing data in internal memory interval, then the data in current memory interval do not change, and do not need to modify to data in its mirror memory interval, do not operate, and terminate current process.
Step 204: the reference address obtaining processor from described consistance message is 5FFFH.
Step 205: the reference address 5FFFH of processor and the address 0-7FFFH of internal memory interval B is compared, show that the reference address of processor belongs to internal memory interval B.
This step is the implementation of following step: judge described reference address is mirrored between memory field described in whether belonging to, and if so, then performs step S2, otherwise, terminate current process.
By step 203-step 205, determine that the internal storage access of processor is the write operation to internal memory interval B, therefore, need also to write identical data to the interval A of internal memory, realize memory mirror.
Step 206: determine that the memory address of access is 5FFFH according to consistance message.
Because processor writes data in the 5FFFH of address, therefore, data can be taken out from this address and be stored in mirror memory interval.
The data read out are written to internal memory interval B by step 207: read data from memory address 5FFFH.
As shown in Figure 3, Figure 4, a kind of internal memory monitoring device is embodiments provided.Device embodiment can pass through software simulating, also can be realized by the mode of hardware or software and hardware combining.Say from hardware view; as shown in Figure 3; for a kind of hardware structure diagram of a kind of internal memory monitoring device place equipment that the embodiment of the present invention provides; except the processor shown in Fig. 3, internal memory, network interface and nonvolatile memory; in embodiment, the equipment at device place can also comprise other hardware usually, as the forwarding chip etc. of responsible process message.For software simulating, as shown in Figure 4, as the device on a logical meaning, be by the CPU of its place equipment, computer program instructions corresponding in nonvolatile memory is read operation in internal memory to be formed.A kind of internal memory monitoring device that the present embodiment provides, comprising:
Setting unit 401, is mirrored mirror memory interval corresponding between memory field for arranging;
First determining unit 402, is mirrored the access message of carrying out write operation between memory field for determining to described;
Second determining unit 403, for determining the memory address of accessing according to described access message;
Described data, for reading data from described memory address, are written to described mirror memory interval by writing unit 404.
In a kind of possible implementation, described first determining unit 402, comprising:
According to described consistance message, first judging unit, for receiving the consistance message carrying out internal storage access, judges whether current memory access is write operation, when judged result is for being, notifies the second judging unit;
Second judging unit, for obtaining reference address from described consistance message, judges described reference address is mirrored between memory field described in whether belonging to, and when judged result is for being, notifies described second determining unit 403;
Wherein, described access message comprises: described consistance message.
In a kind of possible implementation, described setting unit 401, for being set between the first memory field that first processor loads between memory field by described being mirrored, is set to described mirror memory interval between the second memory field that the second processor loads.
In a kind of possible implementation, this internal memory monitoring device also comprises:
3rd determining unit, switches with described mirror memory interval described being mirrored between memory field for determining;
To mourn in silence unit, for being silent status by the described Operation system setting being mirrored internal memory place;
Switch unit, interval with described mirror memory for being mirrored described in switching between memory field;
Lifting unit, for removing the silent status of described system.
Wherein, described switch unit, for being mirrored the address between memory field described in being revised as the address in described mirror memory interval by memory decoder.
The content such as information interaction, implementation between each unit in said apparatus, due to the inventive method embodiment based on same design, particular content can see in the inventive method embodiment describe, repeat no more herein.
The embodiment of the present invention additionally provides a kind of system of memory mirror, and this system comprises:
At least one processor, internal memory monitoring device as shown in Figure 4;
Described internal memory monitoring device is connected with each processor;
Described processor, for sending access message to described internal memory monitoring device.
In a kind of possible implementation, described internal memory monitoring device and each processor are connected by QPI (Quick Path Interconnect, express passway is interconnected) bus.
See Fig. 5, the system of a kind of memory mirror that the embodiment of the present invention provides, this system comprises:
4 processors 501, internal memory monitoring device 502 as shown in Figure 4;
Described internal memory monitoring device is connected by QPI bus with each processor;
Described processor 501, for sending access message to described internal memory monitoring device 502.
When processor access internal memory in system, current processor sends consistance message to the internal memory monitoring device in system and other processors, and as shown in Figure 6, processor A sends consistance message to other processors in system and internal memory monitoring device.
The embodiment of the present invention has following beneficial effect:
The method and system of a kind of memory mirror provided by the embodiment of the present invention, a kind of internal memory monitoring device, pre-set and be mirrored mirror memory interval corresponding between memory field, this mirror memory interval can be between intrasystem any memory field at its place, can be between memory field that in this system, arbitrary processor loads, when determining that current access message conducts interviews to being mirrored internal memory, and current access is when being the write operation to internal memory, the memory address of access is determined from access message, data are read from this memory address, the data of reading are written in corresponding mirror memory interval, realize memory mirror, the method of this memory mirror is not by the restriction of position between memory field, can using interval as mirror memory between memory field arbitrary in system, mirror memory can be set flexibly.
It should be noted that, in this article, the relational terms of such as first and second and so on is only used for an entity or operation to separate with another entity or operational zone, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element " being comprised " limited by statement, and be not precluded within process, method, article or the equipment comprising described key element and also there is other same factor.
One of ordinary skill in the art will appreciate that: all or part of step realizing said method embodiment can have been come by the hardware that programmed instruction is relevant, aforesaid program can be stored in the storage medium of embodied on computer readable, this program, when performing, performs the step comprising said method embodiment; And aforesaid storage medium comprises: ROM, RAM, magnetic disc or CD etc. various can be program code stored medium in.
Finally it should be noted that: the foregoing is only preferred embodiment of the present invention, only for illustration of technical scheme of the present invention, be not intended to limit protection scope of the present invention.All any amendments done within the spirit and principles in the present invention, equivalent replacement, improvement etc., be all included in protection scope of the present invention.
Claims (10)
1. a method for memory mirror, is characterized in that, comprising: pre-set and be mirrored mirror memory interval corresponding between memory field, also comprise:
S1: determine to be mirrored the access message of carrying out write operation between memory field to described;
S2: determine the memory address of accessing according to described access message;
Described data are written to described mirror memory interval by S3: read data from described memory address.
2. method according to claim 1, is characterized in that, described S1 comprises:
According to described consistance message, A1: receive the consistance message carrying out internal storage access, judges whether current memory access is write operation, if so, then performs steps A 2, otherwise, terminate current process;
A2: obtain reference address from described consistance message, judges described reference address is mirrored between memory field described in whether belonging to, and if so, then performs step S2, otherwise, terminate current process;
Wherein, described access message comprises: described consistance message.
3. method according to claim 1, is characterized in that, described in pre-set that to be mirrored between memory field corresponding mirror memory interval, comprising:
In advance described being mirrored to be set between the first memory field that first processor loads between memory field, described mirror memory interval to be set between the second memory field that the second processor loads.
4. method according to claim 1, is characterized in that, after described S3, also comprises:
B1: determine to switch with described mirror memory interval described being mirrored between memory field;
B2: be silent status by the described Operation system setting being mirrored internal memory place;
B3: be mirrored between memory field interval with described mirror memory described in switching;
B4: the silent status removing described system.
And/or described B3, comprising:
The address between memory field is mirrored described in being revised as the address in described mirror memory interval by memory decoder.
5. an internal memory monitoring device, is characterized in that, comprising:
Setting unit, is mirrored mirror memory interval corresponding between memory field for arranging;
First determining unit, is mirrored the access message of carrying out write operation between memory field for determining to described;
Second determining unit, for determining the memory address of accessing according to described access message;
Described data, for reading data from described memory address, are written to described mirror memory interval by writing unit.
6. internal memory monitoring device according to claim 5, is characterized in that, described first determining unit, comprising:
According to described consistance message, first judging unit, for receiving the consistance message carrying out internal storage access, judges whether current memory access is write operation, when judged result is for being, notifies the second judging unit;
Second judging unit, for obtaining reference address from described consistance message, judging described reference address is mirrored between memory field described in whether belonging to, when judged result is for being, notifying described second determining unit;
Wherein, described access message comprises: described consistance message.
7. internal memory monitoring device according to claim 5, it is characterized in that, described setting unit, for being set between the first memory field that first processor loads between memory field by described being mirrored, is set to described mirror memory interval between the second memory field that the second processor loads.
8. internal memory monitoring device according to claim 5, is characterized in that, also comprise:
3rd determining unit, switches with described mirror memory interval described being mirrored between memory field for determining;
To mourn in silence unit, for being silent status by the described Operation system setting being mirrored internal memory place;
Switch unit, interval with described mirror memory for being mirrored described in switching between memory field;
Lifting unit, for removing the silent status of described system.
And/or described switch unit, for being mirrored the address between memory field described in being revised as the address in described mirror memory interval by memory decoder.
9. a system for memory mirror, is characterized in that, comprising:
At least one processor, internal memory monitoring device as described in claim 5-8;
Described internal memory monitoring device is connected with each processor;
Described processor, for sending described access message to described internal memory monitoring device.
10. system according to claim 9, is characterized in that, described internal memory monitoring device is connected by the interconnected QPI bus of express passway with each processor.
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Application publication date: 20150715 |