CN104778027A - Method and apparatus for computing results from dividing dividends by divisors - Google Patents
Method and apparatus for computing results from dividing dividends by divisors Download PDFInfo
- Publication number
- CN104778027A CN104778027A CN201510015444.7A CN201510015444A CN104778027A CN 104778027 A CN104778027 A CN 104778027A CN 201510015444 A CN201510015444 A CN 201510015444A CN 104778027 A CN104778027 A CN 104778027A
- Authority
- CN
- China
- Prior art keywords
- quotient
- value
- remainder values
- division
- divisor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/535—Dividing only
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/535—Indexing scheme relating to groups G06F7/535 - G06F7/5375
- G06F2207/5355—Using iterative approximation not using digit recurrence, e.g. Newton Raphson or Goldschmidt
Abstract
The present invention relates to a method (400) and an apparatus for computing a result (Q) from dividing a dividend (X) by a divisor (D). The method (400) in the present invention includes setting (410) a quotient (Q0, Qi) to an initial value (0) and setting a remainder (r0, ri) to an initial value (0) associated with the dividend (X). In addition, the method of the present invention includes determining (420) a divided result by using the remainder (r0, ri), the divisor (D), and at least one log function. Further, the method of the present invention also includes forming (430) changed quotient (Q1, Qi+1) and changed remainder (r1, ri+1) by using the quotient (Q0, Qi) and the divided result. Finally, the method of the present invention includes computing (440) a result (Q) based on the changed quotient (Q1, Qi+1) provided that the changed remainder (ri, ri+1) and the divisor (D) are placed at a pre-determined relation.
Description
Technical field
The present invention relates to a kind of method of end value of the division for calculating dividend and divisor, a kind of corresponding equipment and a kind of corresponding computer program.
Background technology
In order to calculate division, there is diverse ways.Substantially can distinguish whether calculate division in software or within hardware at this.In the microprocessor can not with the hardware cell for calculating division (namely not having division order) or signal processor, can pass through software, namely by machine instruction sequence (addition, subtraction, jump ...) calculating division, yes for this extremely slowly.The microprocessor had for the hardware cell of division can be extremely more faster calculate division.The example of hardware divider is that so-called recovery divider and non-recovery divider are [for example, see I. Koren, Computer Arithmetic Alorithms, A K Peter, 2001 or B. Parhami, Computer Arithmetic-Algorithms and Hardware Designs. Oxford University Press, 200].
Described divider is very economical about required chip area, but the calculating of division last much longer compared with in divider faster.Recovery or non-recovery divider need n clock in order to calculate binary 2n position word divided by binary n position word.
One class divider is faster so-called Very-High Radix Floating-Point Division Unit, as its in the above documents described by.Described divider is according to exponent number m(m=2
k, such as m=4,8,16 etc.) selection need divided by n position word to calculate 2n position word
individual clock.
Correspondingly, the requirement for chip area is larger compared to recovery/non-recovery divider.According to enforcement, Very-High Radix Floating-Point Division Unit needs additional ROM to calculate division.
Another kind of algorithm for division calculation utilizes the hardware be present in large multimicroprocessor: multiplier or multiply-accumulator (so-called MAC).If described algorithm is implemented within hardware, so this has following advantage: additional hardware spending is little compared to divider fast, but however described algorithm still can realize division calculation extremely fast.Described method is such as carried out division by the normalization of multiplication and formed by inverse carrying out division, as it is such as open in the above documents.These two methods have and restrain extremely fast, but these two methods have following shortcoming: there is no accurately result of calculation (such as according to form 1), but the Residue error of-1 LSB can be there is in the result of business Q, even if it is also like this to implement calculating with not limited word width.
The business Q of form 1 at this illustrate when the number (signed integer) with symbol carries out division and the correct symbol of division remainder R.
If implement described method (such as 2n/n position division, on the multiplier of nn → 2n position) on the multiplier with limited word width, so larger in absolute value Residue error is possible.Described method indirectly provides division remainder, and this division remainder may must calculate dividually.In addition, before can calculating division, must normalization operand in a particular manner.
Summary of the invention
Within this context, by the scheme introduced at this, introducing a kind of method of end value of the division for calculating dividend and divisor according to independent claims, introducing a kind of equipment in addition, described equipment using said method and a kind of corresponding computer program of last introduction.Favourable design proposal from corresponding dependent claims and below description draw.
This programme realizes a kind of method of end value of the division for calculating dividend and divisor, and wherein said method has following step:
-quotient is set on initial value and by remainder values is set on the initial value relevant to dividend;
-utilize described remainder values and divisor, utilize at least one logarithmic function determination division value;
-utilize quotient and division value to form the remainder values of quotient and the change changed;
-when the remainder values changed and divisor are in predetermined relation, the quotient according to changing calculates end value.
Quotient can be understood as the numerical value of division.First quotient can be set on the initial value of such as 0 at this.Remainder values such as can be understood as the numerical value of the difference between the sum of products dividend representing quotient and divisor.At this, when quotient regards as the actual result of the division between dividend and divisor, remainder values can be understood as remaining error.The numerical value that the remainder values changed or the quotient of change are determined before can be understood as utilization upgrades or the remainder values of adaptation or quotient.End value can be understood as the numerical value relevant to the quotient changed.At this, if the remainder values changed and divisor are in predetermined relation, so end value is calculated.
In this scheme proposed based on following knowledge: by adaptive and change quotient and below apply described quotient so that determination result value, can by dividend and divisor very accurately and calculate the result of division rapidly.Especially, by the enforcement of the recurrence of each step under the corresponding adaptation of remainder values and/or quotient, numerically or on circuit engineering division calculation can be performed extremely simply.Also the chip area of the equipment in order to implement the end value being used for the division calculating dividend and divisor can be kept very little in integrated circuits by the scheme introduced at this.In this context, especially effectively can implement filter element especially, described filter element is generally central member in the application of signal transacting.Such filter element provides the advantage that can provide split hair filter result with the extremely short processing time in this case.
Desirably following embodiment of the present invention, wherein when the remainder values changed equals zero and/or when the remainder values changed is greater than zero and the absolute value of the remainder values changed is less than the absolute value of divisor, the quotient calculating change in the step calculated is worth as a result.Such embodiment of the present invention provides following advantage: the quotient not needing process further to change, makes it possible to provide end value with the extremely short processing time.
According to another embodiment of the invention, when the remainder values changed is less than zero and the absolute value of the remainder values changed is less than or equal to the absolute value of divisor, the quotient that can calculate the change reducing numerical value 1 in the step calculated is worth as a result, and/or wherein, when the remainder values changed is greater than zero and the absolute value of the remainder values changed equals the absolute value of divisor, the quotient calculating the change increasing numerical value 1 is worth as a result.Such embodiment of the present invention provides following advantage: the quotient of change only needs to be changed a little on other occasions, can be used as the end value of the division between dividend and divisor.Can advantageously realize the divider of extremely rapid operation to provide end value equally in like fashion.
One embodiment of the present invention are especially accurate, be provided with in this embodiment remainder values remainder values being re-assigned to change numerically and quotient is re-assigned to the step numerically of the quotient of change, after this again implement the step determined and formed.Such embodiment of the present invention especially utilizes the input parameter of the change of described step to realize each step recursively implementing the method introduced at this, makes can realize the precision of result of division or the further improvement of accuracy by this recursion cycle.
In another embodiment of the present invention, when the remainder values changed before the step redistributed is less than zero and the absolute value of remainder values changed is greater than the absolute value of divisor and/or when the remainder values changed before the step redistributed is greater than zero and the absolute value of the remainder values of change is greater than the absolute value of divisor, the step redistributed, determine and formed described in just can performing.Such embodiment of the present invention provides following advantage: the enforcement only just performing the recurrence required for sub-step of the method when it also causes the precision of result of division or accuracy to improve according to predefined condition.
According to an embodiment be especially suitable for of the present invention, the step redistributed, determine and formed repeatedly in turn can be implemented.Can advantageously realize in like fashion: implement circulation by described sub-step each and can improve precision or the accuracy of result of division, until such as obtain the accurate result of division or remaining Residue error is positioned under specific threshold value.
Technically especially effectively, if in the step determined, form difference when forming the logarithm value of the logarithm value of dividend and divisor, wherein division value utilizes this difference to be formed as the index of the truth of a matter, so can realize an embodiment of the invention.Therefore by application logarithmic function division can be reduced to technically can extremely simple realization difference formed.
According to an embodiment of the invention, also can in the step formed, by division value and quotient being added or forming the quotient changed and/or the remainder values wherein being formed change by the product of the quotient and divisor that deduct change from dividend by deducting division value from quotient.Such embodiment of the present invention provides following advantage: numerically or circuit engineering is formed extremely simply the quotient of change, can be used as the basis for calculating end value below described quotient.
In addition, an embodiment of the invention are suitable for the equipment of the end value as the division for calculating dividend and divisor, and wherein said equipment has following unit:
-for quotient being set to the unit be set on initial value and by remainder values on the initial value relevant to dividend;
-for utilizing remainder values and divisor, utilizing the unit of at least one logarithmic function determination division value;
-unit for utilizing quotient and division value to form the remainder values of quotient and the change changed; With
-for calculating the unit of end value according to the quotient changed when the remainder values changed and divisor are in predetermined relation.
Such as, such equipment can be the part of filter element, needs processing signals especially quickly and accurately in this filter element, in particular, is wherein associated as dividend with the other signal as divisor by signal, to obtain the signal filtered.Also can by such embodiment of the present invention effectively and the scheme introduced at this is implemented on cost-effective ground.
Therefore, the scheme introduced at this realizes a kind of equipment, and described equipment is configured to the step of the variations performing or realize the method introduced at this in corresponding device.Also can be come fast by this enforcement variations of the present invention of apparatus-form and effectively solve the present invention based on task.
Currently such equipment can be interpreted as electrical equipment, described electrical equipment processes sensor and/or data-signal and exporting according to it controls and/or data-signal.This equipment can have the interface that can construct with hardware and/or software form.In the structural scheme of hardware mode, interface can be the part comprising the pole difference in functionality of equipment of so-called system ASIC.But also it is possible that interface is intrinsic integrated circuit or is made up of discrete device at least in part.In the structural scheme of software mode, interface can be software module, and described software module is such as present on microcontroller except other software module.
Also advantageously there is the computer program of program code, described program code can be stored in machine-readable carrier, as in semiconductor memory, harddisk memory or optical memory, and when being used to during executive routine product perform the method according to one of above-mentioned embodiment on computing machine or equipment.
Also there is by the scheme introduction introduced at this signal handling equipment of following characteristics:
-for reading the fetch interface of the signal representing physical quantity;
-according to the equipment of variations introduced at this, wherein constructed by this equipment, physical quantity or the numerical value of being derived by physical quantity are treated to dividend and/or are treated to divisor; With
-controlling and/or signal reporting unit, described control and/or signal reporting unit are configured to utilize end value to provide control signal and/or data-signal.
Fetch interface can read by sensor the signal representing physical quantity at this.Physical quantity is current be can be understood as measuring voltage, measurement electric current, measurement pressure, acceleration measurement or can detect and other the amount described with corresponding signal by means of sensor.In an embodiment of the equipment introduced at this, sensor itself also can be the part of signal handling equipment.An embodiment of the invention such as can be considered to use in the microprocessor, and one embodiment of the present invention also may be used for filtering and calculate.Therefore divider can be realized to be used in modern signal processing algorithm (such as Kalman filter).Also can be implemented in microprocessor and use such equipment, described microprocessor has MAC and should in order to specifically apply outfit divider.The embodiment of such example of the present invention provides following advantage equally: can rapidly, on circuit engineering and/or numerically simply and implement signal and/or the data processing of physically based deformation amount simultaneously cost-effective.
Accompanying drawing explanation
Below, the scheme introduced at this is illustratively elaborated with reference to the accompanying drawings.Wherein:
Fig. 1 illustrates the block diagram of the equipment for calculating division according to an embodiment of the invention;
Fig. 2 illustrates the block diagram of another equipment for calculating division according to an embodiment of the invention;
Fig. 3 illustrates the block diagram for implementing the unit for applying Row control in one embodiment of the invention; With
Fig. 4 illustrates the process flow diagram of method according to an embodiment of the invention.
Embodiment
In description below suitable embodiment of the present invention, for illustrate in different figures and play the same or similar Reference numeral of element application of similar effect, wherein abandon element described in repeated description.
Be to provide for utilizing existing MAC unit to calculate the Method and circuits of division fast in the target of this scheme introduced.The result of calculation of X/D is accurate and not only forms by business Q but also by division remainder R, makes to meet equation (1).
If X and D is the integer (signed integer) with symbol, what go out so as illustrated in table 1 defines business Q and division remainder R like that.Be given in table 2 the several examples for different numerical value when having the integer of symbol to carry out division.
Be in the advantage of this scheme introduced: different to two methods calculating division (for example, see above-mentioned document) from use multiplier, accurately result of calculation.In addition, terminate division remainder to store in a register in calculating, therefore described division remainder directly exists as a result.In addition, need not be normalized operand.The quantity of clock for calculating can be affected by the accuracy that Log2 is approximate, and therefore, the speed of division calculation is quick and adjustable.Compared with Very-High Radix Floating-Point Division Unit, little to the demand of additional chip area.
Equation (2) illustrates the known computation rule for logarithm, and described computation rule can be considered for calculating division, namely calculate business Q=X/D(wherein X>0 and D>0).
Division can be calculated with three steps by this computation rule:
1. take the logarithm: the logarithmic function (with 2 end of for) calculating dividend X and divisor D.
2. calculate the poor Diff of logarithm:
.
3. inverse logarithm: the exponential function (with 2 end of for) calculating difference Diff:
.
Logarithmic function and exponential function only can pass through to use method of approximation by providing the realization of the circuit of result in a clock.For calculate the example of the method for approximation of log2 be so-called Michele be similar to.Effectively implementation is existed as combinational circuit for this method of approximation.Due to the error of method of approximation, the business Q calculated by above-mentioned division method is coarse.The use of this division method is hereinafter referred to as logarithm division and by operand Log2-Div(X, D in equation) express
.
The new square ratio juris introduced at this specifies now: by accurately calculating business suitably by business by means of approximate calculating shown logarithm division above and use MAC unit combination.
MAC unit (multiply-accumulator) is arithmetical unit, and described arithmetical unit is the ingredient of common digital signal processor.The multiplication of two numbers (B, C) can be implemented by means of MAC and result can be added to that (in totalizer A) store numerically and usually also can be subtracted (see formula (3)).
Below, new division method is set forth according to the division of two positive several X and D.
By Q
0=0 initial value being chosen as found business Q.Q can be checked by MAC unit
0whether correspond to accurate business, perform in MAC for this reason and calculate X=Q
0d, see formula (4).The result calculated is referred to as remainder r
0and draw the information of the exact value whether finding Q.
If
, so also do not find accurate business, on the contrary, if
, so find business.The meaning of the different numerical value of remainder r is general for the remainder r in calculation procedure i in form 3
iillustrate (at this: i=0).
If also do not find business, so remove remainder r by means of logarithm division D
0and result is added to current business Q
0go up or deduct from it to correct described business.Current remainder r is depended in the decision whether deducted or be added
0symbol.If remainder r
0>0, so this represents: business Q
0also too small, the result by logarithm division is added to Q
0on, if r
0<0, so subtracts each other (see form 3).Therefore calculation procedure is below obtained:
Now, can check whether by MAC again and find business Q, calculate r for this reason
1and compare with the condition in form 3 subsequently.
If also do not find business, so until find business to proceed two calculation procedures.The general formula of two calculation procedures is provided by formula (7) this.Respectively after the calculating of these two steps, check whether by means of the condition in form 3 and find business.
Therefore, calculating alternately passes through current business Q
icorrection (see the Q of formula (7)
i+1calculating) and Q
i+1by remainder r
i+1the inspection subsequently of calculating carry out in MAC.By checking that termination condition (form 3) is determined: the calculating whether completing business Q.Initial value Q is provided by formula (4)
0and r
0.
Fig. 1 illustrates the block diagram for the equipment 100 method introduced at this realized as circuit.At this, the circuit being used for the flow process of the example realizing division (having X>0 and D>0) is described in FIG.Therefore, describe two positive number X and D(according to the circuit in Fig. 1 below and see situation I in form 1) the flow process of example of division.
Start time, register MX with numerical value 0 initialization, register MY with the numerical value initialization of divisor D and register MZ with the numerical value initialization of dividend X.Therefore, register MX comprises the initial value Q of business
0=0 and register MZ comprises the initial value r of remainder
0=X-Q
0d=X.The operation circuit of multiplier and other block is produced by block, Row control AS.In the first clock calculated, multiplier A is in position 0, makes block Log2-Div by means of logarithm division calculation for division
approximate.Block, the positive QK of business school are controlled adder/subtracter or incrementor/demultiplier, namely described piece can according to the operation shown in operation circuit executive table 4.Form 4 sets forth the operation of numerical value on operation circuit and block, the positive QK of business school at this.
Operation circuit has numerical value A in the first clock, namely forms logarithm division
with the numerical value Q be stored in register MX
0=0 and and provide at output.Therefore output valve is the business of the first correction
.The enable input end EN of register MX is arranged to numerical value 1, therefore terminates at the first clock, Q
1be received in register MX.
Check in second clock: the first approximate Q
1whether correspond to found business Q.MAC calculates following operation with controlling to this by the control input end Op of MAC: MZ-MXMY=X-Q
1d.The result of operation is remainder r
1=X-Q
1d, described remainder provides the information (see form 3) whether finding accurate business.If such as there is situation
, so this represents: Q
1also too low.In the 3rd clock, therefore, multiplier A is placed in position 1, namely calculates division by block Log2-Div now
numerical approximation.This result is added to Q
1on, therefore, the operation circuit for block, the positive QK of business school is set to numerical value A(and sees form 4).This result is the second approximate Q of business Q
2and be received in register MX.
Be similar to second clock, check whether in the 4th clock now and find now accurate business Q.Operate MZ-MXMY by MAC again and calculate remainder: r
2=X-Q
2d.Such as there is situation now
, i.e. Q
2reduction 1 LSB(is just in time needed to see form 3) and should be corrected, find accurate business Q thus.
Q
2correction carry out in next clock, this clock be therefore calculate last clock.Operation circuit for block, the positive QK of business school has numerical value I, makes to produce numerical value A+1=Q at output
2+ 1.Described numerical value is received in register MX, and in order to calculate the division remainder of correction, block, remainder correct the numerical value r that RK should correct the output at MAC
2.It is controlled adder/subtracter that block, remainder correct RK, operating in shown in form 5 of described adder/subtracter.At this, form 5 describes the affiliated operation of numerical value on operation circuit and controlled adder/subtracter.
Because business is Q
2improve the numerical value r of 1, MAC output
2=X-Q
2d should reduce the numerical value of divisor D to obtain the division remainder corrected.Therefore the operation circuit that block, remainder correct RK is set as 0 and calculates R=X-Q
2d-D.Multiplier B is in position 1, and the enable input end EN of register MZ is 1 and event memory.Therefore, the business Q of correction to be stored in register MX and the division remainder R corrected is stored in register MZ.
In shown method, depend on the accuracy of logarithm division in order to the quantity calculating rapidity, i.e. clock needed for division and therefore depend on the method for approximation being used to Log2 and Exp2 and calculating.It is possible that the hsrdware requirements of circuit are adapted to the rapidity required for division.
Below, the time flow of division calculation is inquired in detail.In the flow process of the calculating as illustrated above, calculate and be made up of each two steps, described step processes in clock in succession.Business Q is calculated by the positive QK of block, logarithm division and business school in a clock
i+1numerical value.By calculating remainder r in clock subsequently
i+1business Q is checked in MAC
i+1, check interrupt condition by block, Row control AS simultaneously.If also do not satisfied condition, so start other process by two calculation procedures.Form 6 illustrates the time flow of calculating and receives to the numerical value in register.
Below, the scheme described before introduction is for the enforcement of signed integer.Described method is used for integer X and the D(optional sign that two have symbol) division enforcement block diagram in fig. 2 shown in.Be similar to Fig. 1, input register MX 1 and the MY 2 of MAC 3 are shown on right side.These two registers such as have the word length of n position.The output register of MAC is MZ 4 and has the word length of such as 2n position.MAC can control ground implementation and operation MZ-MXMY by control input end Op.Multiplier A in Fig. 1 is illustrated by block 5 in fig. 2.The calculating of logarithm division (the block Log2-Div in Fig. 1) is illustrated by block 6 to 11 in fig. 2.For the situation that input value is negative, block 6 and 7 such as respectively calculates the absolute value of the numerical value being applied to its input end by scale-of-two supplement.Block 8 and 9 calculate be applied on block on the occasion of functional value approximate of Log2 function.The so-called meter Xie Er that can easily realize compared with combinational circuit such as can be used to be similar to this.Block 10 forms the difference of its input end A and B: A-B, such as, by the two's complement of B being added on A.The exponential function (2 that it is the end that block 11 calculates with 2
x) functional value approximate.Input value is the poor Diff calculated by block 10.The calculating operation contrary to this is such as performed in a block 11 according to the method being used to Log2 calculating in block 8 and 9.Block in Fig. 1, the positive QK of business school are illustrated by block 12 to 14 in fig. 2.Block 12 is the constants shown in scale-of-two with numerical value 1 LSB.The input end the B whether output terminal of numerical value 1 LSB or logarithm division (block 6 to 11) being flowed to controlled adder/subtracter 14 selected by multiplier 13.The function of controlled adder/subtracter 14 is shown in form 5.Block in Fig. 1, remainder correct sees form 5 by controlled adder/subtracter 14(in fig. 2) and multiplier 16 realize.Multiplier, adder/subtracter and the control to the numerical value reception in register accept Row control AS 17.Described Row control has four input ends, and described input end is connected with following assembly respectively: the output terminal of register MY 2, register MZ 4, MAC 3 and the output terminal of subtracter 10.The output of Row control AS is control signal s0 ... s7.Shown in the feasible realization of Row control AS block diagram in figure 3.
Produce three M signals by input signal, extremely easily principle of work can be shown by means of described M signal.The title of three M signals is situation, operation and convergence.The binary coding accurately of the state of M signal does not illustrate below, because described M signal is for illustrating the principle of work of Row control and not needing accurately to realize forcibly.Block, situation check that 17a calculates according to the symbol of the dividend X in register MZ 4 and the divisor D in register MY 2, relate to which situation in form 1.The output of block is the signal " situation " that can adopt four different conditions (see form 7).Form 7 is in the function of this description block, situation inspection 17a.
The gap that the output signal of block is surrounded by two-wire in form 7 marks.According to the output valve of MAC and block, situation, block, symbol/zero proof 17b checks that the output of 17a calculates: the remainder r of the current calculating of division
iwhether be less than, be more than or equal to 0 and therefore whether the numerical value of next logarithm division should deduct or be added to this numerically from the numerical value register MX 1, or but whether accurately find business.The output signal of block can adopt three kinds of states and represent to operate, function shown in form 8.Form 8 is in the function of this description block, symbol/zero proof 17b.
The current word be stored in register MX 1 accurately corresponds to the output of inspection by means of the subtracter 10 in signal operation, situation and Diff(Fig. 2 of business Q) check that 17c performs by block, convergence.Therefore signal " convergence " illustrates whether the calculating (after the correction that may terminate) of business terminates, and sees form 9.The function that form 9 checks in this description block, convergence.
Therefore control signal s0 can be realized as follows by means of three signals ... s7.
Control signal s0 controls multiplier 5.In the first clock calculated, the dividend X be stored in MZ 4 is placed on the input end of logarithm division circuit (block 6 to 11).In whole other clocks, respectively the output terminal of MAC is placed on described input end, sees form 10.Form 10 describes the numerical value of the control signal s0 in corresponding clock at this.
By operation circuit s1 select whether in order to the numerical value in correcting register MX 1 should use the output of logarithm division circuit (block 6 to 11) or but constant 1 LSB should be used, see form 11.Form 11 describes the numerical value of control signal s1 and affiliated numerical value Diff at this.
Whether the correction that operation circuit s2 determines the numerical value in register MX 1 by be added or the numerical value subtracted each other on the output terminal of multiplier 13 realizes, is shown in form 12.Form 12 describes the numerical value of control signal s2 at this and operates accordingly.
Operation circuit s3 and s4 is used for correcting division remainder in the last clock calculated.The division remainder (see form 9 and form 13) corrected is selected in the correction of s3 needed for register MX 1.Form 13 describes the numerical value of control signal s3 according to signal operation, situation and Diff at this.
The adder/subtracter 15 that operation circuit s4 is controlled according to the Numerical Control of signal " operation ", is shown in form 14.Form 14 at this illustrate control signal s4 according to the numerical value of selected operation.
The numerical value that operation circuit s5 controls in register MZ 4 receives, and sees form 15.Form 15 at this illustrate control signal s5 according to the numerical value of convergence signal.
If block, convergence check display: found result accurately, so division remainder can be received in register MZ 4, namely operation circuit s5 is identical with convergence signal.The numerical value that operation circuit s6 controls in register MX 1 receives.Every second clock (1,3 ...) in, the numerical value of correction is received in MX 1, also sees form 6.Form 16 illustrates the numerical value of control signal s6 according to clock, operation, signal Diff and situation.
Operation circuit s7 selects the operation of MAC 3 and is therefore constant, because only need to operate MZ-MXMY.If described in operate in should be unavailable in MAC, if namely such as only can calculating operation MZ+MXMY in MAC, so when loading negative dividend-X in register MZ4, however should use the method illustrated.In this case, so can operation-X+Q be passed through
id realizes remainder r
icalculating.
In order to process further by above-mentioned piece, so such as can by scale-of-two supplement to described remainder r
iget negative.Therefore the method also can use in this case.
Can for supplying method in the ASIC with MAC to this in this scheme introduced, so as by little (for logarithm division) add-on module fast and economical ground the calculating of division is solved.Especially in the calculating of the current algorithm to signal transacting, (such as Kalman filter) needs division calculation.
Embodiment that is described and that illustrate in the drawings is only exemplarily selected.Different embodiments can fully or about each feature combination with one another.Embodiment also can be supplemented by the feature of other embodiment.
In addition, the method step introduced at this can be repeated and be implemented with the order different from described order.
If embodiment comprises "and/or" between fisrt feature and second feature and connects, so this can be understood as: this embodiment not only has fisrt feature according to an embodiment but also has second feature and according to another embodiment or only have fisrt feature or only have second feature.
Claims (11)
1., for calculating the method (400) of the end value (Q) of the division of dividend (X) and divisor (D), wherein said method (400) has following step:
-by quotient (Q
0, Q
i) setting (410) is upper and by remainder values (r to initial value (0)
0, r
i) be set on the initial value (X) relevant to dividend (X);
-utilize described remainder values (r
0, r
i) and described divisor (D) and utilize at least one logarithmic function to determine (420) division value;
-utilize described quotient (Q
0, Q
i) and described division value form (430) quotient (Q of changing
1, Q
i+1) and change remainder values (r
1, r
i+1);
-as the remainder values (r of described change
1, r
i+1) with described divisor (D) be in predetermined relation time, according to the quotient (Q of described change
1, Q
i+1) calculate (440) described end value (Q).
2. method according to claim 1 (400), is characterized in that, as the remainder values (r of described change
1, r
i+1) when equalling zero and/or as the remainder values (r of described change
1, r
i+1) be greater than zero and remainder values (the r of described change
1, r
i+1) absolute value when being less than the absolute value of described divisor (D), calculate described quotient (the Q calculating described change in the step of (440)
1, Q
i+1) be worth (Q) as a result.
3. the method (400) according to any one in the claims, is characterized in that, as the remainder values (r of described change
1, r
i+1) be less than zero and remainder values (the r of described change
1, r
i+1) absolute value when being less than or equal to the absolute value of described divisor (D), calculate in the described step calculated reduce numerical value 1 and the quotient (Q that changes
1, Q
i+1) be worth (Q) as a result, and/or wherein, when the remainder values of described change is greater than zero and remainder values (the r of described change
1, r
i+1) absolute value when equaling the absolute value of described divisor (D), calculate increase numerical value 1 and the quotient (Q that changes
1, Q
i+1) be worth as a result.
4. the method (400) according to any one in the claims, is characterized in that, be provided with remainder values (r
i) be re-assigned to the remainder values (r of described change
1, r
i+1) numerically and by quotient (Q
i) be re-assigned to the quotient (Q of described change
1, Q
i+1) step numerically, after this again implement the described step determining (420) and described formation (430).
5. method according to claim 4 (400), is characterized in that, as the remainder values (r of described change before the described step redistributed
1, r
i+1) be less than zero and remainder values (the r of described change
1, r
i+1) absolute value when being greater than the absolute value of described divisor (D) and/or as the remainder values (r of described change before the described step redistributed
1, r
i+1) be greater than zero and remainder values (the r of described change
1, r
i+1) absolute value when being greater than the absolute value of described divisor (D), to redistribute described in just performing, the described step determining (420) and described formation (430).
6., according to the method (400) one of claim 4 or 5 Suo Shu, it is characterized in that, repeatedly in turn implement described in redistribute, the described step determining (420) and described formation (430).
7. the method (400) according to any one in the claims, it is characterized in that, determine in the step of (420) described, forming difference (Diff) when forming logarithm value and the logarithm value of described divisor (D) of described dividend (X), wherein utilizing the described division value of described difference (Diff) to be formed as the index of the truth of a matter.
8. the method (400) according to any one in the claims, is characterized in that, in the step of described formation (430), by by described division value and described quotient (Q
0, Q
1) be added or pass through from described quotient (Q
0, Q
1) in deduct the quotient (Q that described division value forms described change
1, Q
i+1) and/or wherein by deducting the quotient (Q of described change from described dividend (X)
1, Q
i+1) and the product of described divisor (D) form the remainder values (r of described change
1, r
i+1).
9., for calculating the equipment (100) of the end value (Q) of the division of dividend (X) and divisor (D), wherein said equipment (100) has following unit:
-for by quotient (Q
0, Q
1) to be set to initial value (0) upper and by remainder values (r
0, r
1) be set to unit (MX, MY, MZ) on the initial value relevant to dividend (X);
-for utilizing described remainder values (r
0, r
1) and described divisor (D) and utilize the unit (Log2-Diff, 10) of at least one logarithmic function determination division value;
-for utilizing described quotient (Q
0, Q
i) and described division value formed change quotient (Q
1, Q
i+1) and change remainder values (r
1, r
i+1) unit (QK, 14); With
-for the remainder values (r when described change
1, r
i+1) when being in predetermined relation with described divisor (D) according to the quotient (Q of described change
1, Q
i+1) calculate the unit (AS, 17) of described end value.
10. computer program, has the program code for performing the method (400) according to any one in claim 1 to 8 when implementing described program product on equipment (100).
11. signal handling equipments, have following characteristics:
-for reading the fetch interface of the signal representing physical quantity;
-equipment according to claim 9 (100), is wherein constructed by described equipment, described physical quantity or the numerical value of being derived by described physical quantity are treated to dividend (X) and/or are treated to divisor (D); With
-controlling and/or signal reporting unit, described control and/or signal reporting unit are configured to utilize described end value (Q) to provide control signal and/or data-signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102014200493.4A DE102014200493A1 (en) | 2014-01-14 | 2014-01-14 | Method and device for calculating a result value of a division from a dividend and a divisor |
| DE102014200493.4 | 2014-01-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104778027A true CN104778027A (en) | 2015-07-15 |
Family
ID=53484924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510015444.7A Pending CN104778027A (en) | 2014-01-14 | 2015-01-13 | Method and apparatus for computing results from dividing dividends by divisors |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN104778027A (en) |
| DE (1) | DE102014200493A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107992284A (en) * | 2017-11-27 | 2018-05-04 | 中国航空无线电电子研究所 | A kind of division function implementation method of programming device |
| CN111399803A (en) * | 2019-01-03 | 2020-07-10 | 北京小米松果电子有限公司 | Division operation method, device, storage medium and electronic equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1379323A (en) * | 2001-04-11 | 2002-11-13 | 北京国芯安集成电路设计有限公司 | Ultra-long divider with array type combination logic unit |
| US20060117080A1 (en) * | 2004-11-30 | 2006-06-01 | Arm Limited, | Data processing apparatus and method for performing floating point multiplication |
| CN1818852A (en) * | 2005-02-10 | 2006-08-16 | 国际商业机器公司 | System and method for performing decimal division |
| CN101986259A (en) * | 2010-11-25 | 2011-03-16 | 中国人民解放军国防科学技术大学 | Sign-free fixed point division and sign-free fixed point divider |
| CN103914276A (en) * | 2013-01-08 | 2014-07-09 | 美国亚德诺半导体公司 | Fixed point division circuit utilizing floating point architecture |
-
2014
- 2014-01-14 DE DE102014200493.4A patent/DE102014200493A1/en not_active Withdrawn
-
2015
- 2015-01-13 CN CN201510015444.7A patent/CN104778027A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1379323A (en) * | 2001-04-11 | 2002-11-13 | 北京国芯安集成电路设计有限公司 | Ultra-long divider with array type combination logic unit |
| US20060117080A1 (en) * | 2004-11-30 | 2006-06-01 | Arm Limited, | Data processing apparatus and method for performing floating point multiplication |
| CN1818852A (en) * | 2005-02-10 | 2006-08-16 | 国际商业机器公司 | System and method for performing decimal division |
| CN101986259A (en) * | 2010-11-25 | 2011-03-16 | 中国人民解放军国防科学技术大学 | Sign-free fixed point division and sign-free fixed point divider |
| CN103914276A (en) * | 2013-01-08 | 2014-07-09 | 美国亚德诺半导体公司 | Fixed point division circuit utilizing floating point architecture |
Non-Patent Citations (2)
| Title |
|---|
| 何炯: "基于 FPGA 的模糊控制器设计与实现", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
| 尹文佳 等: "绿藻浓度荧光检测系统的研究", 《东北电力大学学报》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107992284A (en) * | 2017-11-27 | 2018-05-04 | 中国航空无线电电子研究所 | A kind of division function implementation method of programming device |
| CN107992284B (en) * | 2017-11-27 | 2022-12-23 | 中国航空无线电电子研究所 | Method for realizing division function of programmable device |
| CN111399803A (en) * | 2019-01-03 | 2020-07-10 | 北京小米松果电子有限公司 | Division operation method, device, storage medium and electronic equipment |
| CN111399803B (en) * | 2019-01-03 | 2022-07-15 | 北京小米松果电子有限公司 | Division operation method, device, storage medium and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| DE102014200493A1 (en) | 2015-07-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104520807B (en) | The micro-architecture of multiplication addition is merged for having the floating-point of index bi-directional scaling | |
| CN107273090A (en) | Towards the approximate floating-point multiplier and floating number multiplication of neural network processor | |
| CN107769791B (en) | Apparatus and method for fixed-to-floating point conversion and negative power detector of 2 | |
| CN102707921A (en) | Leading zero prediction in floating point addition | |
| CN104899004A (en) | Data processing apparatus and method for multiplying floating point operands | |
| CN105468331A (en) | Standalone floating-point conversion unit | |
| JP7115211B2 (en) | Arithmetic processing device and method of controlling arithmetic processing device | |
| KR102200913B1 (en) | High performance floating-point adder with full in-line denormal/subnormal support | |
| KR102318494B1 (en) | Multiply adder | |
| CN101738238B (en) | Liquid level metering device with computer and method for controlling computer. | |
| CN107851007B (en) | Method and apparatus for comparison of wide data types | |
| KR102412746B1 (en) | Apparatus and method for performing floating-point square root operation | |
| CN101650643B (en) | Rounding method for indivisible floating point division radication | |
| CN104778027A (en) | Method and apparatus for computing results from dividing dividends by divisors | |
| CN106250098A (en) | For controlling the device and method rounded off when performing floating-point operation | |
| US10620914B2 (en) | Method and system for performing division/multiplication operations in digital processors, corresponding device and computer program product | |
| US5903486A (en) | Device for digitally carrying out a division operation | |
| CN108334304B (en) | Digital recursive division | |
| JP7036075B2 (en) | Integer divider and motor controller | |
| CN108153513B (en) | Leading zero prediction | |
| US20140351309A1 (en) | Fma unit, in particular for utilization in a model computation unit for purely hardware-based computing of function models | |
| US9836279B2 (en) | Apparatus and method for floating-point multiplication | |
| US9032009B2 (en) | Multiplier circuit | |
| US9594728B2 (en) | Device and method for determining an estimate of the logarithm of an input variable | |
| GB2527125A (en) | Calculation of a number of iterations |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150715 |
|
| WD01 | Invention patent application deemed withdrawn after publication |