CN104769715B - Power in common substrate is put integrated - Google Patents
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- CN104769715B CN104769715B CN201380051393.2A CN201380051393A CN104769715B CN 104769715 B CN104769715 B CN 104769715B CN 201380051393 A CN201380051393 A CN 201380051393A CN 104769715 B CN104769715 B CN 104769715B
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Abstract
The present invention relates to a kind of for promoting the integrated semiconductor structure of the power device in common substrate, it comprises: the first insulating barrier, it is formed on described substrate；And the zone of action, it has the first conductivity-type, be formed at described first insulating barrier at least some of on.The first terminal is formed on the upper face of described structure, and electrically connects with at least one other region with described first conductivity-type being formed in the described zone of action.The embedded trap with the second conductivity-type is formed in the described zone of action and couples with the second terminal on the described upper face being formed at described structure.Described embedded trap forms clamp diode with the described zone of action, and described clamp diode will puncture avalanche region and be positioned between described embedded trap and described the first terminal.The breakdown voltage of at least one in described power device becomes with the characteristic of described embedded trap.
Description
CROSS REFERENCE TO RELATED reference
Present application for patent opinion is the most entitled, and " power in common substrate puts integrated (Power Device
Integration on a Common Substrate) " and the Serial No. 13/939 filed an application on July 11st, 2013,
U.S. patent application case, the U.S. patent application case of Serial No. 13/939,422 and the Serial No. 13/939,490 of 451
The priority of U.S. patent application case, each in described U.S. patent application case is the part of following U.S. patent application case
Continuation application and advocate the priority of following U.S. patent application case: entitled " power in common substrate is put integrated
(Power Device Integration on a Common Substrate) " the sequence filed an application on May 6th, 2013
Row number are 13/887,704 U.S. patent application case, and it advocates again entitled " the power management collection for portable electron device
Become circuit (Power Management Integrated Circuit for Portable Electronic Devices) "
The priority of U.S. Provisional Patent Application case of the Serial No. 61/677,660 filed an application on July 31st, 2012, institute
The disclosure stating each in patent application case is incorporated herein for all purposes and in entirety by reference.
Technical field
The present invention relates generally to electronic circuit, and integrated more particularly to power device.
Background technology
Contemporary portable including but not limited to smart phone, laptop computer and tablet computing device, net book etc.
Electronic installation is battery-operated, and it is (such as (for example) micro-to typically require the subsystem for being stably applied in device
Processor, pictorial displays, memory chip etc.) supply voltage power supply module.Power demand scope is generally about 1
Between watt (W) and about 50W.
Supply of electric power/management assembly is typically divided into some functional devices；I.e. control circuit, driving stage and power switch.
From the position of equipment miniaturization (this is the wanted target of many portable electron devices), by integrated for supply of electric power/management assembly
It is favourable in single integrated circuit (IC) chip.This solution is limited to the pole of hundreds of milliampere (mA) wherein for induced current
Low power consumption product is the most dominant.Fig. 1 is that graphic extension comprises power management control circuit 102, driving stage 104
And the block diagram of the exemplary power stage of power switch 106 and 108, its whole single-chip integration are in single IC 100.
Generally, use metal-oxide semiconductor fieldeffect transistor (MOSFET) device to implement described power to open
Close.Manufacture MOSFET need relatively little of masks (such as, less than about ten mask levels), and the control circuit in IC with
MOSFET device is compared and is typically required the most multiple masks (such as, about 26 to 36 mask levels).Therefore, by big nude film
Differentiation is fitted on power switch and causes high production cost, and this is unacceptable.
Summary of the invention
Embodiments of the invention provide for promoting integrated to circuit and/or assembly (such as, driver and power switch)
In with for implementing the novel semiconductor structure on the silicon substrate that the corresponding control circuit of output control device is identical and technology.For
Realizing this purpose, embodiments of the invention development and implementation is on silicon-on-insulator (SOI) substrate with electrolyte lateral isolation
The feature of BiCMOS IC manufacturing technology.
According to one embodiment of the invention, it is used for the semiconductor structure bag promoting the power device in common substrate integrated
Containing: the first insulating barrier, it is formed on described substrate；And the zone of action, it has the first conductivity-type, is formed at described
One insulating barrier at least some of on.The first terminal is formed on the upper face of described semiconductor structure, and be formed at institute
State at least one other region electrical connection with described first conductivity-type in the zone of action.Described semiconductor structure enters
One step comprises: embedded trap, and it has the second conductivity-type, is formed in the described zone of action, described embedded trap and shape
The second terminal coupling on the described upper face of semiconductor structure described in Cheng Yu.Described embedded trap is configured to together with described
The zone of action forms clamp diode together, and the breakdown voltage of at least one in described power device is with described embedded trap
One or more characteristic and become.The operation of described clamp diode is positioned in described semiconductor structure in institute will puncture avalanche region
State between embedded trap and described the first terminal.
According to another embodiment of the present invention, it is provided that be used for the semiconductor junction promoting the power device in common substrate integrated
Structure, at least one in described power device comprises bipolar junction transistor (BJT).Described semiconductor structure comprises: the first insulation
Layer, it is formed on described substrate；The zone of action, it has the first conductivity-type, is formed at described first insulating barrier extremely
In a few part；And first area, it has described first conductivity-type, is formed in the described zone of action close to described work
With the upper face in region.The collector region with described first conductivity-type is formed at least of described first area
Close to the upper face of described first area in Fen, it is dense that described collector region has higher-doped compared with described first area
Degree.The collector terminal being formed on the upper face of described semiconductor structure electrically connects with described first area.Described quasiconductor
Structure comprises further: embedded trap, and it has the second conductivity-type, is formed in the described zone of action.Described embedded
Trap is configured to form clamp diode together with the described zone of action, and described clamp diode operates will puncture avalanche region
Territory is positioned between described embedded trap and described collector terminal, the breakdown voltage of described BJT with described embedded trap one or
Multiple characteristics and become.The base region with described second conductivity-type is formed in the described zone of action at described embedded
At least some of of trap above and extends transverse to described first area.The emitter region with described first conductivity-type is formed
In the upper face of described base region, described emitter region with on the described upper face being formed at described semiconductor structure
Emitter terminal connect.Base structure is formed on the described upper face of described semiconductor structure in described base region and institute
Stating the face of tying between first area, described base structure electrically connects with described embedded trap and base terminal is formed at described half
On the described upper face of conductor structure.
According to still another embodiment of the invention, the semiconductor structure bag promoting the power device in common substrate integrated it is used for
Containing: the first insulating barrier, it is formed on described substrate；The zone of action, it has the first conductivity-type, is formed at described first
Insulating barrier at least some of on；The first terminal, its be formed on the upper face of described semiconductor structure and be formed at institute
State at least one other region electrical connection with described first conductivity-type in the zone of action；And embedded trap, its tool
There is the second conductivity-type, be formed in the described zone of action.Described embedded trap is configured to together with the described zone of action one
Rising and form clamp diode, the operation of described clamp diode is positioned described embedded trap and described the will to puncture avalanche region
Between one terminal, the breakdown voltage of at least one in described power device with described embedded trap one or more characteristic and
Become.Described semiconductor structure comprises further: grid structure, and it is formed on the described upper face of described semiconductor structure
Described embedded trap at least some of above and close to the upper face of the described zone of action.Described grid structure and described work
With region electric isolution and electrically connect with described embedded trap.
According to one more embodiment of the present invention, the method that one or more power device is integrated in common substrate is comprised with
Lower step: form the first insulating barrier over the substrate；Described first insulating barrier at least some of on formed have first
The active layer of conductivity-type；Through the described active layer at least the first zone of action in described active layer and the second active region
Forming lateral dielectric isolation between territory, described first zone of action and described second zone of action are by described lateral dielectric
Isolation and electrically isolated from one；Close between described active layer and described first insulating barrier in the most described first zone of action
Interface forms at least one embedded trap with the second conductivity-type；In institute on the upper face of described semiconductor structure
At least some of above and close to described first zone of action the upper face stating embedded trap forms grid structure, described grid
Electrode structure electrically insulates with described first zone of action and electrically connects with described embedded trap；In described first zone of action at least
In a part, described upper face close to described first zone of action is formed and has at least the of described first conductivity-type
One region, described first area has the doping content higher than described first zone of action, described grid structure and described first
Interface between the zone of action with described first area is the most overlapping；And the described top table at described semiconductor structure
Forming at least the first terminal and the second terminal on face, described the first terminal electrically connects with described embedded trap, and described second end
Sub and described first area electrically connects；Wherein said embedded trap is configured to form pincers together with described first zone of action
Position diode, the operation of described clamp diode with will puncture avalanche region be positioned described embedded trap and described second terminal it
Between, the breakdown voltage of at least one in described power device becomes with one or more characteristic of described embedded trap.
Described in detail below according to the present invention that will read in conjunction with the accompanying, embodiments of the invention will become aobvious and
It is clear to.
Accompanying drawing explanation
Presenting figures below the most by way of example, and not limitation, wherein similar elements symbol (when deployed) is throughout several
View instruction counter element, and wherein:
Fig. 1 is the exemplary merit that graphic extension comprises the control circuit, driving stage and the power switch that are implemented in single IC
The block diagram of rate management circuit；
Fig. 2 be graphic extension comprise with outside IC discrete power switch couple be implemented in described IC exemplary
The block diagram of the power stage of power management control circuit and driving stage；
Fig. 3 is that graphic extension is suitable for comprising, according to what embodiments of the invention used, be implemented in an IC exemplary
Power management control circuit and be implemented on the driving stage in the 2nd IC coupled with a described IC and the power of power switch
The block diagram of level；
Fig. 4 and 5 is the cross section describing conventional horizontal proliferation Metal-oxide-semicondutor (LDMOS) transistor unit
Figure；
Fig. 6 and 7 is the cross-sectional view of the conventional LDMOS transistor device that description is formed in SOI substrate；
Fig. 8 is at least one of cross section describing the exemplary BiCMOS structure according to one embodiment of the invention
Figure；
Fig. 9 A and 9B is describe the exemplary N-channel ldmos transistor according to one embodiment of the invention at least one
The cross-sectional view divided；
Figure 10 is describe exemplary N-channel ldmos transistor according to another embodiment of the present invention at least some of
Cross-sectional view；
Figure 10 A is describe exemplary N-channel ldmos transistor according to another embodiment of the present invention at least some of
Cross-sectional view；
Figure 11 is describe according to the exemplary low voltage signal MOSFET of one embodiment of the invention at least one of
Cross-sectional view；
Figure 12 A to 12E is describe the most exemplary bipolar junction transistor (BJT) at least one
The cross-sectional view divided；
Figure 13 is at least one of cross-sectional view describing the exemplary PN diode according to one embodiment of the invention；
Figure 13 A is at least one of cross-sectional view of another embodiment describing exemplary PN diode；
Figure 13 B and 13C is the method describing grid is coupled to anode terminal in order to the embodiment according to PN diode
Cross-sectional view；
Figure 14 A is describe exemplary Schottky (Schottky) diode according to one embodiment of the invention at least one
The cross-sectional view of part；
Figure 14 B is at least one of horizontal stroke describing exemplary Schottky diode according to another embodiment of the present invention
Sectional view；
Figure 14 C is at least one of cross-sectional view of the alternate embodiment describing exemplary Schottky diode；
Figure 15 is at least one of horizontal stroke describing exemplary Schottky diode according to the third embodiment of the invention
Sectional view；
Figure 15 A is the cross-sectional view of the gate trench structure describing Figure 15；
Figure 15 B is at least one of cross-sectional view of another embodiment describing exemplary Schottky diode；
Figure 15 C is the graphic extension chart for the change of the conduction electric current of the embodiment of exemplary Schottky diode；
Figure 16 and 17 is to describe according to the one embodiment of the invention exemplary resistor structure in snakelike layout respectively
At least one of plan view from above and cross-sectional view；
Figure 18 is at least one of cross-sectional view describing exemplary capacitor structures according to an embodiment of the invention；
Figure 19 is at least one of cross section describing the exemplary P-channel MOSFET according to one embodiment of the invention
Figure；
Figure 20 A to 20F is the cross-sectional view describing the exemplary BiCMOS process flow according to one embodiment of the invention；
And
Figure 21 A to 21E is to describe according to one embodiment of the invention for two power devices are integrated in same SOI lining
At least one of cross-sectional view of the exemplary BiCMOS process flow at the end；
Figure 22 A to 22C graphic extension Electric Field Distribution between grid and the drain region of various shielding constructions；And
Figure 23 is the cross-sectional view of graphic extension chip size molectron.
It will be appreciated that for the element simply and in the figure of purpose graphic extension clearly.Can not show and may commercially may be used
Useful or required common but understandable element in the embodiment of row, in order to facilitate less being subject to of illustrated embodiment
The view hindered.
Detailed description of the invention
To be used for being formed saying of one or more assembly of being suitable in illustrative management circuit using herein
Embodiments of the invention described in the context of bright property management circuit and method for semiconductor manufacturing.However, it should be understood that this
Bright embodiment is not limited to particular electrical circuit displayed and described herein and/or method.But, embodiments of the invention are wider
Free burial ground for the destitute relates to realize the high-frequency performance of various power management application (such as (for example) DC/DC power converter)
Mode make the technology of integrated circuit, and advantageously reduce the external module can being used together together with embodiments of the invention
The physics size of (such as (for example) output filter) and cost and other benefit.Additionally, the technology people of art
Member by when in view of teachings herein it is clear that the shown embodiment in the range of institute's claimed invention can be made
Numerous amendments.I.e., it is not intended that or should not infer any restriction about embodiment displayed and described herein.
For describing and the purpose of opinion each aspect of the present invention, MOSFET plan broad sense as used herein, the term
Ground is explained to contain any kind of metal-insulator-semiconductor field effect transistor (MISFET).For example, art
Language MOSFET intends to contain to utilize an oxide material as the semiconductor field effect transistor of its gate-dielectric and also
Do not utilize an oxide material as the semiconductor field effect transistor of its gate-dielectric.Although it addition, contracting in initial
Slightly word MOSFET and MISFET mention term " metal ", but MOSFET and/or MISFET be also according to an embodiment of the invention
Intend to contain the semiconductor field effect transistor with the grid formed by nonmetal (such as (for example) polysilicon).
Although embodiment of the present invention described herein can use p-channel MISFET (hereinafter referred to " PMOS "
Or " PFET " device) and n-channel MISFET (hereinafter referred to " NMOS " or " NFET " device) implement, as used
BiCMOS (bipolar complementary metal oxide semiconductor) manufacturing process is formed, it is to be understood that the invention is not restricted to this crystalloid
Pipe device and/or this manufacturing process, and as those skilled in the art will understand when in view of teachings herein, can class
As use other suitable device, Metal-oxide-semicondutor (LDMOS) device of such as (for example) horizontal proliferation,
Bipolar junction transistor (BJT) etc., and/or manufacturing process (the most bipolar, complementary metal-oxide-semiconductor (CMOS) etc.).This
Outward, although embodiments of the invention are to be made in silicon wafer, but embodiments of the invention are also alternatively made in and include it
On the wafer of its material, other material described including but not limited to GaAs (GaAs), gallium nitride (GaN), indium phosphide (InP),
Cadmium selenide (CdSe), cadmium telluride (CdTe), zinc sulfide (ZnS) etc..
As it was earlier mentioned, when device electric current being limited to hundreds of milliampere (that is, rating of set consumption is less than about two watts), say
Bright property power stage can single-chip integration in management circuit framework as show in Figure 1, wherein control circuit 102, drive
Level 104 and power switch 106,108 are all made on same IC chip 100.But, increase above about five in rating of set consumption
Time about Wa Te (such as, greater than about two amperes (A)), the segmentation that substitutes of management circuit is favourable and/or needs.
For example, Fig. 2 is that graphic extension includes the power management control circuit 102 being implemented in an IC 200 and drives
Dynamic level 104 and being implemented on couple with a described IC and in discrete IC devices 202 and 204 through encapsulating individually that it is outside
The block diagram of exemplary power stage of power switch.Unfortunately, although this solution makes it possible to separate with power switch
Ground makes control circuit, and hence benefits from individually optimizing the ability of the manufacturing process of each IC, but and first (control) IC
Cross tie part 206 (such as, printed circuit traces, joint wire, spherical grid battle array between 200 and power switch IC 202 and 204
Row (BGA) etc.) spurious impedance (predominantly stray inductance) that is associated substantially stops the method is used for high frequency applications (example
As, greater than about one megahertz) in.But, the method be generally used between about 5 watts to about 30 watts in the range of merit
Rate is changed.
Fig. 3 is the graphic extension power management control including being implemented in an IC 304 according to one embodiment of the invention
Circuit 302 processed and be implemented on the driving stage 306 in the 2nd IC 312 coupled with a described IC and power switch 308 and
At least one of block diagram of the exemplary power stage 300 of 310.For example, by power stage 300 as show in Figure 3
Segmentation be applied to DC/DC transducer and have greater than about 30 watts power conversion other circuit and subsystem.Particularly
For, power stage 300 is divided into: controlling IC 304, it is with more complicated digital VLSI (great scale is integrated) technology mistake
Journey makes；And power block 312, it being implemented as multi-chip module (MCM), described MCM comprises the driving stage made with analogue technique
306 and the discrete power switch 308 and 310 of the nude film that is integrated in described MCM.
The MCM method of Fig. 3 is for the power management system for high-power applications (such as, for desktop PC).
In this case, described module contains three independent nude films: driver chip and two MOSFET power switch.Portable electric
Sub-device requires the miniaturization (that is, small size) of implemented subsystem consumingly, and requires consumingly to reduce to change rank at power
Produced power loss in Duan.Therefore, each aspect of the present invention provides and allows the single chip integrated of driving stage and power switch
Cost-effective technology, this realizes the double nude film solutions according to splitting scheme demonstrated in Figure 3.That is, can be for electricity
Medium-sized power application required for the portable electron device of pond operation and on same nude film, manufacture driver and FET power open
Close.There is currently no any technology and can realize this System Partition for the power bracket of greater than about five watts.
Generally, to maximize the target of integration density and conversion speed to develop (such as (the act of digital-to-analog process
For example) BiCMOS technology).The optional power switch that existing dopant profiles curve and process steps design can be used the most not
Abundant performance can be realized in power management application.The reduction of transistor energising resistance and the reduction of power switched loss need to mix
The specific optimisation of miscellaneous structure and the use of adjusted process steps sequence.This is only the completeest in the design of discrete power switch
Become.On the other hand, the process that discrete power switchs does not allows for different electronic modules and (comprises NFET, PFET, bipolar junction crystal
Pipe, P-N junction and Schottky diode etc.) single-chip integration.
Power management system (such as, DC/DC transducer) generally uses power switch to perform the altofrequency of input power
Wave chopping and use include that the output voltage under variable load condition stablized by the output filter of inducer and capacitor.Switching
Frequency is the highest, and power conversion performance is the best, and the volume of required output filter and cost the least.Switching frequency is from currently obtaining
It is desirable that about 1 megahertz (MHz) obtained increases to about 5MHz, but due in the power transistor for implementing power switch
(it can be at least partially attributed to device spurious impedance (such as, internal capacitance, inductance and electricity in the power switched that is associated loss
Resistance)) and still can not realize.
Known can improve merit significantly by reducing in inside subject diode the internal capacitance stored and electric charge
The performance of handoffs (for example, with reference to the 7th, 420, No. 247 and the 7th, 842, No. 568 United States Patent (USP)) of rate MOSFET.Fig. 4 and 5 is point
Do not describe discrete horizontal proliferation Metal-oxide-semicondutor (LDMOS) transistor 400 and 500 known in the art
Cross-sectional view.The performance of the design of the power MOSFET on silicon-on-insulator (SOI) substrate usually MOSFET provides notable skill
Art advantage.Fig. 6 and 7 is the ldmos transistor 600 and 700 describing respectively to be formed in SOI substrate known in the art
Cross-sectional view.Oxide is buried in effect soi layer (such as, 702 in 602 and Fig. 7 in Fig. 6) lower section and can reduce output
Electric capacity (Coss) and reduce body diode volume significantly, reduce the stored electricity of diode whereby compared with standard set-up structure
Lotus (Qrr) and the related power loss of (that is, the reverse biased of leap transistor) during commutating.Said two feature reduces phase
The switch cost associated and the increase of the operation frequency realizing device.Although have these technical advantages using SOI substrate, but institute
The transistor proposed not yet is broadly adapted to manufacture discrete and/or integrated power MOSFET owing to the cost of product increases.And
And, by turning in the gate electrode side of grid about the gate oxide caused by hot carrier injection (HCI) under avalanche condition
The problem of the long-term reliability at angle and hinder the acceptance of the method.
Accordingly, it would be desirable to develop the simulation integrating process of a kind of optimal switching performance being absorbed in lateral direction power device, it is permitted
Permitted different types of power switch together with driving stage and (optionally) some supervision and the monolithics of defencive function of being associated
Integrated.The power stage manufactured according to each aspect of the present invention is the input electricity between about a volt (V) and about ten volts (V)
Pressure scope and the output electric current between about an ampere and about five amperes provide the power management solution strengthened.Therefore,
The power delivered will contain scope between three watts and 30 watts roughly, but embodiments of the invention are not limited to
This or any certain power scope.
Explaining the most in detail, embodiments of the invention described herein are based on to having electricity Jie
20 volts of BiCMOS technology that the SOI substrate of matter lateral isolation is implemented.According to embodiments of the invention, by what Fig. 3 was presented
System Partition realizes as double nude film solutions.Chip size molectron (that is, chip size packages (CSP) or wafer scale
Encapsulation (WLP)) preferably avoid volume and cost that the encapsulation with individual elements is associated.In an embodiment of the present invention, logical
The lower cost crossing integrated drive carrys out the higher cost of balanced power switch, and realizes wave filter by increasing operation frequency
The volume of assembly and being obviously reduced of cost.
Fig. 8 is describe to incorporate the demonstrative structure 800 of each side according to one embodiment of the invention at least one
The cross-sectional view divided.Structure 800 can use BiCMOS treatment technology to be made in N-type or P type substrate 801.With reference to Fig. 8, structure
800 combinations comprising the following: embedded trap 802, it is partially implanted at the bottom of active layer 804；And multiple groove
(that is, groove band) 806, it has and is lined with gate oxide 808 or substitutes dielectric sidewall and base wall and be filled with
Polycrystalline silicon material 810 or replacement conductive material.Groove 806 is preferably formed to the group of parallel stripes, and described parallel stripes exists
Electric current flowing (such as, in the situation of FET or Schottky diode embodiment) between it, or its is affected when appropriately being biased
Work to increase the electric capacity (such as, in the situation of capacitor embodiment) of the per unit area of structure.In this example, make
N is formed as with layer 804-Region, and embedded trap 802 is formed as P+Trap, but as those skilled in the art will be in view of this
It is clear that other embodiments may utilize alternative dopings scheme (such as, N during teaching in literary composition-Region and N+Embedded trap, or P-
Region and P+Or N+Embedded trap).
The configuration of structure 800 advantageouslys allow for the integrated of various assembly, such as (for example) FET, BJT, PN diode,
Schottky diode, resistor and capacitor.Each in groove 806 is essentially vertically from the top surface of structure 800
812 extend, through active layer 804, and at least partially in embedded trap 802.In alternative embodiments, groove 806
Can extend across in the oxide skin(coating) 818 that embedded trap 802 enters into embedded.The sidewall of covering groove 806 and base wall
In oxide liner, 808 stop directly electrically connecting between polycrystalline silicon material 810 and the embedded trap 802 filling groove.Polysilicon
Filler 810 preferably acts as gate terminal, and as in (for example) FET and Schottky diode embodiment, it can be by partially
Pressure.
The middle tool of device (such as transistor or diode) of the blocking voltage that embedded trap 802 is applied with maintenance in operation
There is critical function.More particularly, so that substantially fixing (that is, clamp) is formed at upper right (that is, the point of embedded trap
End) and the N of active layer 804-The mode of the breakdown voltage at PN junction between background doped configures the doping of embedded trap 802
Level, doping type and/or position.By optionally controlling one or more characteristic of embedded trap 802, control described device
In Electric Field Distribution.
The groove band 806 with the wall (that is, sidewall and base wall) being lined with gate oxide 808 is positioned over formation
Between the main terminal of power device therein." main terminal " intends to broadly refer to described device as used herein, the term
External connection, such as (for example) source electrode in the situation of mos device and drain terminal, or in the situation of diode
Anode and cathode terminal.In the illustrative embodiment shown in fig. 8, form (example substantially parallel to current path
As, etching) trench-gate band 806.Therefore, in the situation of (for example) lateral direction schottky diode, conduction electric current exists
N between gate trench 806-Active layer 804 flows and applied grid potential can be passed through and control (such as, modulation).?
In the situation of the FET structure that one or more embodiment according to the present invention is formed, trench-gate 806 operates with loss or strengthens grid
Pole/main body interface, thus control the electric current flowing of the inversion channel being formed through in device.
The doped polycrystalline silicon material 810 filling described groove is (the clearest and the most definite along third dimension by area of grid for being formed
Ground is shown) it is connected to the grid bus of gate terminal.For the NFET device formed according to embodiments of the invention, polycrystalline
Silicon materials 810 are preferably doped with phosphorus, and wherein doping content is greater than about 1019/cm3, and for PFET device, polysilicon material
Material is preferably doped with boron, has about 1019/cm3Doping content.The top surface of polycrystalline silicon gate layer 810 is shown as optionally
Ground is covered by the silicide material 814 (such as, titanium silicide (TiSi) or tungsten silicide (WSi)) with low-resistivity, described silication
Thing material can use known silicide deposition process (such as, chemical gaseous phase deposition (CVD), sputter deposition etc.) deposited thereon.
The silicide layer 814 forming polycrystalline silicon (polycide) electrode in device 800 reduces the resistance of described device.
In a preferred embodiment, the path that narrow gate trench 806 flows along the electric current in body region 804 is formed at
Below polycrystalline silicon electrode 814.In this way, groove 806 increases the effective grid width in MOSFET structure 800, and
Other advantage.
It is horizontal that another groove structure 816 deeper formed than groove 806 is preferably used for being formed between integrated package
Area of isolation.Deep groove structure 816 (also referred to as lateral isolation groove) can be by (for example) from described structure
Top surface 812 be etched through active layer 804 and formed to the embedded oxide skin(coating) 818 being formed on substrate 801.Laterally
Isolated groove 816 can be filled with oxide, or the combination of oxide and polysilicon.Cutting (that is, etching) (showing the most clearly)
Substrate contact is can be used as through embedded oxide skin(coating) 818 to the optional deep trench of substrate 801.This optional groove is preferably filled with
There is doped polysilicon or substitute conductive material to guarantee good ohmic (that is, the low resistance) contact of substrate 801.
The most illustrative BiCMOS process flow can be used to form various electronic building brick.Under
Literary composition describes the example of some assemblies formed incorporating each aspect of the present invention with reference to Fig. 9 A to 19.
Fig. 9 A is describe the most exemplary N-channel ldmos transistor 900 at least one of
Cross-sectional view.Compared with standard LDMOS device, at least partially due to the effect of grid cover layer, ldmos transistor 900 has
There is the grid of reduction to capacitance of drain (Cgd).Additionally, at least partially due to the diode storage electric charge reduced, LDMOS crystal
Reversely recovery (the Q to body diode shown by pipe 900rr) little impact.Transistor 900 comprises integrated PN clamp diode (i.e.,
The diode formed by the end of deep trap 902 and drain region) as the ingredient of each action cell, described integrated PN pincers
Avalanche breakdown is fixed as away from gate oxide and close to embedded P by position diode+Turn right angle in the top of trap 902.That is, exist
Under the conditions of obturation, snowslide electron impact ionization is between the tip and the turning of drain contact areas of embedded trap 902, in effect
In the volume of layer and away from top and bottom oxide interface.This makes to increase in the case of not causing any integrity problem
The resistance to avalanche of power transistor.This transistor design minimum heat-transformation carrier is to the injection in oxide, thus improves power and open
The long-term reliability closed.Conduction electric current source region 905 between the wall of trench-gate 906 flow to through lightly doped drain
(LDD) elongated area 908 enters in drain contact 910.The similar trench-gate (cross section is to intercept along groove) formed
Alternative view be shown as in Fig. 9 B the structure 906 described.Fig. 9 B graphic extension is essentially vertically through p-type body region
920 and enter into the embedded P being formed at the bottom of body region+The trench-gate 906 formed in trap 902.Trench gate
Pole 906 has the wall (that is, sidewall and base wall) being lined with gate oxide 922.Fig. 9 B also shows that lateral isolation structure
924, the mode that described lateral isolation structure can be consistent with lateral isolation structure 816 demonstrated in Figure 8 is formed, and it provides collection
Become the isolation between assembly.P during processing, in SOI substrate-Handle wafer is along P-Substrate/embedded oxide interface quilt
Loss, this reduces output capacitance C of MOSFEToss。
It will be appreciated that in the situation of simple mos device, be substantially symmetrical due to mos device, and therefore it is two-way
, therefore the appointment of the source electrode in mos device and drain electrode design is the most arbitrary.Therefore, source electrode and drain region can be divided
The most substantially it is referred to as first and second regions and source/drain, the most in this context " source/drain " mark source region or leakage
Territory, polar region.In the LDMOS device of the most also non-bidirectional, these source electrodes and drain electrode design can the most arbitrarily be assigned.
The obturation that embedded trap 902 (the embedded trap 802 as demonstrated in Figure 8) is especially applied with maintenance in operation
The device (such as, transistor and diode) of voltage has critical function.More particularly, so that substantially clamping formation
The N of the active layer 904 in the upper right and described device of embedded trap-The breakdown voltage at PN junction between background doped
Mode configure the doped level of embedded trap 902, doping type and/or position.By optionally controlling embedded trap
One or more characteristic of 902, controls the Electric Field Distribution in device.Such as, described device can make maximum electricity through advantageously arranging
Field distribution is turned right between angle and the right bottom corners of drain contact areas 910 in the top of embedded trap 902.Joining in this way
When putting, clamp PN diode is integrated in described device, and this makes the hot carrier keeping being produced by snowslide electron impact ionization
Away from top silicon/oxide interface.This feature increases device in the case of making the integrity problem in being formed without device and inhales
Receive the ability of avalanche energy.
When the illustrative SOI LDMOS device 600 and 700 shown in Fig. 6 and 7 is pushed in snowslide respectively, collision
Ionizing will occur at the bottom corners of grid, in cladding system through lightly doped drain (LDD) region, and hot carrier is to institute
The injection stated in the gate oxide in device will typically result in integrity problem, as known in the art.At least go out
In this reason, the conventional LDMOS structure on SOI is not suitable for use in power switch.By providing in order to snowslide is clamped on LDMOS
The ability at desired location in transistor unit, the LDMOS structure formed according to the one or more aspects of the present invention is well
It is suitable in power switching application.
With continued reference to Fig. 9 A and 9B, ldmos transistor 900 comprises shielding field plate 912 or substitutes shielding construction, described shielding
Structure is formed as being lined with the lateral extensions of the conductive layer of source electrode trench contact wall in this embodiment, (such as, many with grid
Crystal silicon structure) 914 overlapping and immediately closely along the oxide interface of N drain extension region (that is, LDD region territory) 908.Described conduction
Layer is preferably deposited as titanium (Ti)/titanium nitride (TiN) stacking, but also can be formed by other material, such as (for example) titanium
(Ti)/tungsten silicide (WSi) film.In this illustrative embodiment, source electrode groove is formed on the left-hand side of ldmos transistor 900,
Have and be lined with grid cover layer 912 and be filled with sidewall and the base wall of top metal.
The effects that shielding 912 mainly plays field plate, lean on most along the edge (such as, bottom, right turning) away from grid 914
It is bordering on top oxide interface distributions (such as, the stretch) Electric Field Distribution at drain electrode, and also serves as the positively biased helping to reduce drain electrode
Grid at pressure is to capacitance of drain Cgd(so-called Miller (Miller) electric capacity, it determines the switch speed of transistor) and further
Improve the shielding of gate oxide reliability.The peak electric field of the drain side corner being revealed in grid 914 turns at grid now
Separate between angle and the end of field plate, thus reduce peak electric field and suppress hot carrier to injecting ahead of time in oxide.Drain electrode and
Source contact 910 and 916 is respectively formed as through metal filled through hole, and it is (the brightest that described through hole accesses patterned top metal level
Really show, but imply) and form drain electrode (D) and source electrode (S) terminal of LDMOS device 900 respectively.Also tactile to be applied to drain electrode
The positive bias of point 910 is lost and additionally aids reduction C through lightly doped drain extension region (908)gd.It is formed at polysilicon gate
In structure 914, the silicide layer 918 that forms multi-crystal silicification nitride layer (the most siliconized polysilicon) whereby leads to for formation
The grid bus positioned along third dimension (be not explicitly shown, but imply) of gate terminal (G).Silicide layer 918 is preferably
Known deposition process (such as, CVD, sputter etc.) is used to be formed.
Figure 10 is describe exemplary N-channel ldmos transistor 1000 according to another embodiment of the present invention at least one
The cross-sectional view of part.This ldmos transistor 1000 is designed as in Fig. 9 A and 9B the simplification of the LDMOS device 900 shown.As
From Figure 10 it is clear that compared with the LDMOS device 900 shown Fig. 9 A and 9B, in the making of LDMOS device 1000
One simplification includes removing gate trench (in Fig. 9 A and 9B 906).Main impact on the performance of MOSFET 1000 is every list
The less grid width that plane is long-pending, this increases the connection resistance R of gained deviceON.This can be by existing with grid polycrystalline silicon because removing
The relevant alignment of overlap above gate trench tail end limits and makes that channel length is shorter to be balanced.MOSFET device 1000
Further feature and characteristic keep the most identical with LDMOS device 900.
The alternate embodiment of the LDMOS device 1000 of Figure 10 A graphic extension Figure 10.Specifically, this embodiment comprise by
Breakdown voltage expands to the amendment higher than 20V.In the LDMOS device 1000A of Figure 10 A, gate terminal and drain terminal it
Between introduce narrow strips relatively thick-oxide 1016.This permission grid cover 1012 forms second order field plate and (that is, adds boosted rank
Part 1014), this improves Electric Field Distribution further.
Figure 22 A to 22C shows Electric Field Distribution between grid and drain region under various configurations.Figure 22 A is illustrated in nothing
Electric Field Distribution between grid and drain region in the case of the impact of field plate.High peak electric field in the corner of grid allows
Being injected in gate oxide by hot carrier, this reduces the reliability of transistor.Figure 22 B show is being designed for what 20V punctured
The field plate formed by grid cover layer in transistor eliminates this critical electric field.In Figure 22 C, show that field plate is at shielding construction
In further improvement, wherein introduce relatively thick-oxide band and realize being forced away from peak value electric field the second order of described gate corners
Field plate profile.As mentioned above, this structure is preferably used for being designed for higher than in the transistor of the breakdown voltage of 20V.
Figure 11 is describe the most exemplary low voltage signal MOSFET 1100 at least some of
Cross-sectional view.As described below in further detail, MOSFET 1100 comprises the P that can be used for being formed other circuit unit
Body region 1102 and N drain region 1104.In this embodiment, P+Embedded trap is the most exemplary
Situation in MOSFET 1000 is directly connected to source terminal, but is connected with independent block (B) terminal.This configuration allows will
The voltage potential being different from the voltage potential being applied to source terminal is applied to embedded trap.By explanation demonstrated in Figure 10
Another simplification of property device 1000 forms MOSFET 1100.Specifically, reduced the pitch of elementary cell, allowed whereby
The higher density of these devices that will be positioned in circuit.Trading off as to higher density, MOSFET 1100 has reduction
High voltage capability and the resistance to avalanche of reduction, but these features are generally even more important for power switching application.
Combining Fig. 9 A to 11 in the specific embodiment of above-described MOSFET, be 12V and 60V by transistor design
Between targeted breakdown voltage specification.In low-voltage power management system, these MOSFET are optimised for as having minimum
The application of the power switch of electric conductivity and power switched loss.The real presently implemented Fig. 3's of embodiment described herein is integrated
During scheme, DC/DC transducer switching frequency from 1.5MHz to 5MHz increases.
With reference now to Figure 12 A, cross-sectional view describes the most exemplary SOI bipolar junction transistor
(BJT) 1200 at least some of.BJT 1200 is formed as the amendment of MOSFET device 1000 demonstrated in Figure 10.Herein,
Previous body region 1102 by the MOSFET 1100 shown in Figure 11 is used as the base region 1201 of BJT 1200.Move
Except source electrode trench contacts.On the contrary, cross over base region 1201 and cut trench contacts 1202 to realize deep P+Layer 1204 and polysilicon
Connection between compound structure (that is, siliconized polysilicon).Figure 12 B describe graphic extension according to embodiments of the invention in order to
Form deep P+A kind of exemplary BJT 1250 of the mode of the connection between layer 1204 and polycrystalline silicon structure.Specifically,
By along finger type layout (such as, between finger piece) interrupt emitter-base bandgap grading contact 1202 and by deep P+Layer 1204 and polycrystalline silicon
If the connection 1252 between structure 1254 is formed as doing (that is, contact).In this embodiment, connect 1252 and be formed as titanium
(Ti) lateral extensions of/titanium nitride (TiN) layer (in the way of being similar to field plate 912 demonstrated in Figure 9) and and polysilicon
Compound structure 1254 is overlapping.These contacts are spaced apart with defined preferably along polycrystalline silicon band and (such as, exist
In the situation of MOSFET, described multi-crystal silicification object area will be the grid being patterned as band, and touches for construction base stage bus
Point), and described multi-crystal silicification nitride layer is for forming the base stage bus with low-resistivity.Described polycrystalline silicon material is used to make
Ensure that low base resistance for base region touches the current bus of base terminal, this improves the performance of handoffs of transistor.
Figure 12 C graphic extension BJT embodiment 1250A, is wherein partially formed in base contact 1256 in the zone of action
Make electrical contact with in the trench region of middle formation and with being connected 1252.
In the partial cross sectional view of Figure 12 D in embodiment illustrated, connect 1252A and be not directly contacted with polycrystalline
Silicide base stage, but spaced away.Button-like contact 1258 is provided and makes it contact the top table of polycrystalline silicon base stage
The upper face of face and articulamentum 1252A (and optionally, side surface) both.One or many person in these push-button contacts 1304 can
Through interval (with the third dimension along base polysilicon compound band, and interlocking with emitter-base bandgap grading contact) to realize there is deep P+ trap
The polycrystalline silicon base structure of 1204 is via contacting between articulamentum 1252A with base contact 1256.
This BJT configuration is used to preserve the initial high voltage ability of MOSFET structure and resistance to avalanche.Will be formed in deep P+
PN junction between tip and the collector region of trap is used as clamp diode.As in the situation of MOSFET, the PN of BJT clamps two poles
The district of avalanche breakdown is fixed in the volume of silicon layer by pipe, thus arrests limit by being produced the snowslide electron impact ionization of this position
Hot carrier.
With reference to Figure 12 A, can be observed, BJT is included in the MOS raceway groove below polycrystalline silicon stacking, described MOS channel shape
Become the MOSFET structure in parallel with bipolar transistor.If applied to the threshold that the positive bias of BJT base terminal is more than MOSFET
Threshold voltage, then increase collected current by flowing through the electronic current of MOS raceway groove, this improves the gain (β) of BJT.
Although not showing, but such as combine the shielding construction that other embodiments described herein discussed and may also be incorporated into
This design in improve BJT device puncture/reliability performance.
As Figure 12 E shows, the polarity of doped region that can be implanted by reversion and will Figure 12 A be shown
NPN BJT transistor arrangement is converted into PNP BJT.
As mentioned above, basic MOSFET structure may be adapted to provide power diode.It is different from VLSI Technology design
Ordinary power PN diode, power P N diode described herein represents resistance to avalanche.Additionally, described basic MOSFET
Structure may be adapted to provide the most not Schottky diode in the VLSI assembly tool case of designer.Disclosed herein
By enforcement, structure is able to maintain that whole executed alive PN and Schottky diode increase the spirit of power management IC design
Activity.The voltage spikes that these diodes are presented in supply Voltage rails drives described circuit to exceed allowed maximum inaccessible electricity
The resistance to avalanche of uniqueness during pressure value.These proposed diodes are compatible with for the process flow disclosed in SOI-MOSFET,
And be the direct amendment of described structure.
Figure 13 is describe according to the exemplary PN diode 1300 of one embodiment of the invention at least one of transversal
Face figure.PN diode 1300 is obtained as the amendment to exemplary MOSFET structure 1000 demonstrated in Figure 10.Herein,
Omit N+ source region, and form the PN for forming diode 1300 by the knot of previous P main body 1102 with N drain electrode 1104
Knot.Formed and there is anode (A) terminal of trench contacts 1302 being applicable to electrically connect with P main body 1102.Negative electrode (C) terminal is suitable to
The electrical connection of the n-quadrant 1104 of offer and diode.Preserve the initial high voltage ability of MOSFET structure and resistance to avalanche.
Figure 13 A is describe the one exemplary embodiment according to the PN diode 1300A of alternate embodiment at least one of
Cross-sectional view.PN diode 1300A and PN diode 1300 is identical, but except modified trench contacts 1302A, described through repairing
The trench contacts changed extends the shielding construction to comprise field plate with gate overlap with offer at least in part, as explained above with Fig. 9 A
And described by 10.The PN diode of Figure 13 A is by making the deep P placed along active layer interface+Trap 1102 aoxidizes towards embedded
Thing preserves the complete voltage occlusive ability of LDMOS structure.Under the conditions of obturation, snowslide electron impact ionization is localized in embedded
Between tip and the turning of cathode contact region of trap 1102, in the volume of active layer and away from top and bottom oxide circle
Face.This minimum heat-transformation carrier of design of diode is to the injection in oxide, thus improves the long-term reliability of power device.Logical
Cross deep P+The end of trap 1102 and cathode zone and the PN junction that formed are used as the composition of each action cell as described diode
The clamp diode of part.The avalanche breakdown defined by this clamp diode is fixed in the volume of silicon materials, thus increases
The resistance to avalanche of power device.Integrated shielding construction reduces the Capacitance Coupled between gate terminal and cathode terminal, and serves as edge
The top oxide interface with Ldd region and stretch out the field plate of described Electric Field Distribution.The cathode side being revealed in gate stack turns
Peak electric field at angle is separated now between gate corners and the end of field plate, thus reduces peak electric field and suppress hot carrier to arrive
Injecting ahead of time in oxide.
In the embodiment of Figure 13 and 13A, polycrystalline silicon grid and deep P+ trap 1102 can be connected to sun along third dimension
Extreme son.As shown in the partial cross sectional view of Figure 13 B, polycrystalline silicon grid can be via extending through conductive layer/grid
The button-like contact 1304 of shielding 1302a is connected to anode and deep P+ trap 1102, and wherein button-like contact 1304 realizes and grid
The polycrystalline silicon of structure and with the electrical contact of conductive layer/grid cover 1302a (such as, by being partially formed in conductive layer
On the top surface of 1302a).One or many person in these push-button contacts 1304 can through interval (along third dimension) with realize along
Polycrystalline silicon band touches gate polycrystalline silicide with defined interval (such as, with finger type layout), rather than by continuously
Contact carrys out interruption masking structure 1302A.Figure 13 C graphic extension in order to be coupled to anode and deep P+ trap by gate polycrystalline silicide
Alternative method.Specifically, anode channels contact 1302B has extension so that gate polycrystalline silicide to be connected to anode and deep P+
The lateral extensions (extension as shown in Figure 12 B) of trap 1102.This extension 1302B also extend with formed have as
Shielding construction above in association with the field plate described by the embodiment of Figure 13 B.In another embodiment, grid bus can be configured into
The terminal separated with anode, and described both can be together at external short circuit.In certain embodiments, the method can provide for relatively
Simple process.
Having been for power MOSFET to observe the single-chip integration of Schottky diode, wherein Schottky diode clamp is whole
Body diode.The method is intended to avoid the stored electric charge during the commutation biased with the drain-to-source at power MOSFET
The power loss that Qrr is relevant.In the 6th, 049, No. 108 and the method for the 6th, 078, No. 090 United States Patent (USP), Schottky diode
Be integrated in groove-MOSFET structure, wherein use two trench walls below schottky contact close to at inaccessible bar
Schottky contacts interface is shielded from the high electric field induced by drain voltage under part.This TMBS structure (groove-MOS-potential barrier-
Schottky) advantage be: the electric screen of schottky contact realizes using in the case of any deterioration of non-blocking ability higher
The quasiconductor (relatively low Vf) of doping.And, the leakage current of TMBS diode has flat voltage characteristic, and described voltage is up to
By breakdown voltage defined in PN junction present in adjacent cells.
No. 7,745,846 United States Patent (USP) discloses the Schottky two of the exclusive unit being integrated in LDMOS transistor structure
Pole is managed.Described structure has the vertical current flow at the rear side of wafer towards drain contact.Be formed at top metal with
The electric screen of the schottky contact between LDD-1 region is realized by grid and the inaccessible impact of P-buffer area.Schottky
The forward direction I-V characteristic of diode can be affected by grid potential.Integrated Schottky diode have and previous generation LDMOS crystal
Manage identical blocking voltage ability.The most do not propose that any comparable Schottky diode is for power management
IC。
Figure 14 A is at least one of horizontal stroke describing the most exemplary Schottky diode 1400
Sectional view.Schottky diode 1400 is formed as the amendment of the PN diode 1300 shown in Figure 13.Specifically, province Lueyang
Pole trench contacts 1302 and P body region 1102 (see Figure 13), thus allow in anode contact (metal) 1402 and N-Effect
Interface between layer 1404 forms Schottky barrier.In an embodiment, by two-step rapid thermal annealing (at 650 DEG C and 820
RTP at DEG C) stablize described Schottky barrier, this causes being formed silicide phases (such as, TiSi at contact interface2)。
Top polysilicon silicide layer 1406 and deep P+Trap 1408 be electrically connected to anode (A) terminal and negative electrode (C) terminal applied close
The contraction of the lower Induced Electric Field distribution of plug bias.By gate stack is positioned over N-At the top in region and by deep P-Trap is positioned over
N-At the bottom in region (this is similar to the action of JFET raceway groove) and this blockage effect of being formed shields described under the conditions of obturation
Schottky contacts interface is from any high electric field.At the gamut of blocking voltage, (such as, about 12 volts are arrived described screen effect
About 20 volts, but the present invention is not limited to any specific voltage or voltage range) the middle leakage current kept in diode 1400
For low.The value of the leakage current in diode is by with the N at schottky contact-The doping characteristic of the zone of action 1404 and become,
As those skilled in the art will know.(for example, with reference to the 5th, 365, No. 102 United States Patent (USP), its disclosure whole in
Appearance is incorporated herein by reference.) shielding of schottky contact realizes quasiconductor higher-doped at schottky interface
(as discussed below in conjunction with Figure 14 B), and improve the electrical property of diode.
Deep P+The connection of trap 1408 and polycrystalline silicon structure 1406 and anode contact 1402 can with Figure 12 B in for saying
The consistent mode of connection 1252 that bright property BJT device 1250 is shown is formed.Specifically, preferably by interrupting along finger-like
The anode contact 1402 of layout and by deep P+Connection between layer 1408 and polycrystalline silicon structure 1406 is formed as point.At this
In embodiment, the lateral extensions that described connection is formed as titanium (Ti)/titanium nitride (TiN) layer (is the most clearly opened up in Figure 14 A
Show, but imply in the way of being similar in Figure 12 B the connection 1252 shown), and make itself and polycrystalline silicon structure 1406 weight
Folded.These contacts preferably along polycrystalline silicon band with defined be spaced apart (such as, in the situation of MOSFET, institute
Stating multi-crystal silicification object area will be the grid being patterned as band), and described multi-crystal silicification nitride layer is used for being formed operation to close
The described schottky contact low-resistivity shielding construction from any high electric field is shielded, as previously mentioned under the conditions of plug.
At least some of of the exemplary Schottky diode 1400A according to alternate embodiment is described in Figure 14 C graphic extension
Cross-sectional view.Schottky diode 1400A is identical with Schottky diode 1400, but comprises shielding construction 1414, described screen
Shield structure serves as both grid cover and the field plate of Schottky diode 1400A.Deep P+Trap 1408 and polycrystalline silicon grid knot
Structure 1406 can be shown for illustrative PN diode apparatus 1300A with the connection of anode contact 1402 in Figure 13 B or 13C
The consistent mode that connects formed, or external connection can be realized as specified by process.In an embodiment, shielding construction 1414 is also
It is incorporated in Figure 14 B in the Schottky diode structure shown.
Owing to maintaining inaccessible electricity by the apparatus structure on the negative electrode of top polysilicon silicon compound electrode (drain electrode previously) side
Pressure, and by deep P+The turn right PN junction at angle (that is, most advanced and sophisticated) place of the top of trap 1408, to clamp avalanche breakdown, therefore preserves MOSFET
The initial high voltage ability of structure and resistance to avalanche.Deep trap 1408 is preferably close to the tool of Si/ embedded oxide interface
There is the implantation trap of maximum dopant concentration.In a preferred embodiment, maximum dopant concentration is at about 5e16cm-3With 5e17cm-3Between
In the range of, and dopant profiles curve is configured to towards surface downward-sloping.It will be appreciated, however, that the present invention is not limited to deeply
The specific doping content of trap 1408 or distribution curve.In this embodiment, PN junction is by the direction of cathode terminal
Deep P+Trap 1408, N-Active layer 1404, n-quadrant 1410 and N+Region 1412 is formed.
Figure 14 B is describe exemplary Schottky diode 1450 according to another embodiment of the present invention at least some of
Cross-sectional view.The Schottky diode 1400 described in Schottky diode 1450 and Figure 14 A is the most identical, but with class
It is similar to the mode of n-quadrant 1410 at N-Close to N in active layer 1404-The upper face of active layer forms extra n-quadrant 1452.With
The Schottky diode 1400 shown in Figure 14 A is compared, and the advantage of Schottky diode 1450 is: can be by increasing close to institute
State the N of schottky contact-Before the doping content of active layer 1404 reduces the Schottky diode 1400 described in Figure 14 A
To voltage drop.In a preferred embodiment, this is by the N implanted region 1410 at the cathode side of multi-crystal silicification object area being extended
Region (being shown as n-quadrant 1452 in Figure 14 B) below anode (A) contact 1402 and realize.
As above together with described by the demonstrative structure described in Figure 10 to 14C, according to the one of the present invention or
The important benefits of multiple embodiments is to comprise deep trap, and described deep trap is configured to clamp described breakdown voltage away from silicon/oxide
Interface.This layout advantageously makes described structure can absorb avalanche energy in the case of not suffering from integrity problem.According to
The supernumerary structure of other embodiments of the invention incorporates the drain region of similar configuration, therefore inherits at (for example) figure
The resistance to avalanche of the previous generation MOSFET design shown in 9A and 9B.
Figure 15 is describe exemplary Schottky diode 1500 according to another embodiment of the present invention at least some of
Cross-sectional view.Repairing of the illustrative Schottky diode 1400 that Schottky diode 1500 is formed in Figure 14 A to be described
Change.Specifically, in the way of consistent with the amendment of MOSFET 900 demonstrated in Figure 9, preferably along being formed at two poles
The N below polycrystalline silicon electrode 1504 on the upper face of the active layer of pipe 1500-Mesa region (that is, active layer) 1404
In current flow path gate trench 1502 is formed in device.Gate trench structure 1502 is improved extraly to Schottky
Contact carries out shielding the screen effect affected against the blocking voltage being applied to negative electrode (C) terminal.At Schottky diode
In 1500, gate electrode is decoupling from anode (A) terminal and can be used for revising the conducting pathway between gate trench 1502 further
Footpath.Described anode terminal is connected to deep P along third dimension+Trap 1408, this shows the most clearly but implies.Schottky two pole
Pipe 1500 can be referred to herein as suitching type Schottky diode and represent the power of new according to an embodiment of the invention type
Device.
Figure 15 A is the cross-sectional view of the groove structure of the suitching type Schottky diode device describing Figure 15 in more detail.
Electric current flow to negative electrode (drain electrode) region from anode (source electrode) contact under conduction condition between gate trench 1502.If ditch
Well width is less than the N between groove 1502-The width of land regions (that is, the zone of action 1404), then increase every action cell
Effective grid width.The increase increasing the mutual conductance corresponding to MOSFET of grid width, and correspond respectively to connecing of transistor
The reduction of energising resistance.As Figure 15 and 15A shows, SOI-Schottky diode structure is implemented gate trench to pass through group
Close N-The vertical loss of layer 1404 and lateral loss further enhance screen effect.Area of grid can be come as the 3rd terminal
Access with by correspondence bias is applied to this electrode is switched on and off lateral loss effect.As explained above with other embodiments
Discussing, anode terminal can be connected to deep P+ trap 1408 along third dimension.Lateral isolation region 1514 (its can include oxide or
Other dielectric substance) it is formed in diode structure 1500 to electrically insulate described diode and other circuit group on nude film
Part.
The alternate embodiment of Figure 15 B graphic extension suitching type Schottky diode 1500A.Suitching type Schottky diode
1500A is the most identical with Schottky diode 1500 depicted in figure 15, but at N in the way of being similar to n-quadrant 1510-
Close to N in active layer 1404-The upper face of active layer forms extra N implanted region 1552.That is, near schottky contact
Active layer is doped to higher N doping content, the doping of the active layer between gate trench 1502 is held in simultaneously original relatively
Low N-At level.Compared with the suitching type Schottky diode 1500 shown in Figure 15, suitching type Schottky diode 1500A
Advantage be: can be by increasing close to the N of described schottky contact-The doping content of active layer 1404 reduces in Figure 15 is retouched
(Vf) drops in the forward voltage of the Schottky diode 1500 painted, and screen effect remains unaffected.In a preferred embodiment, this
Be by the N implanted region 1510 at the cathode side of multi-crystal silicification object area is extended to region below anode (A) contact (
Figure 15 B is shown as n-quadrant 1552) and realize.Although at the known dress disclosed in the such as No. 7,745846 United States Patent (USP)
In putting, forward direction characteristic can be revised to anodic bias by being applied to the grid of gate electrode, but as Figure 15 C schemed explain orally
Bright, the diode structure from Figure 15 B is presented in the change of four orders of magnitude of conduction electric current when being switched on and off grid bias.
This suitching type Schottky diode can be referred to as π switch due to gate trench feature cross-section illustrated for Figure 15 A.Though
So do not show, but the grid cover structure discussed combined other embodiments may also be incorporated in this design with as described in improvement
Device puncture/reliability performance.
Figure 16 and 17 is to describe according to the embodiments of the invention exemplary resistor structure in snakelike layout respectively
At least one of top view of 1600 and cross-sectional view.Resistor paths 1602 is by the N between gate trench 1606-Region
1604 define, described N-Region is connected to N at the two ends of snakelike shape+Contact area 1608 and 1610.Described N+In contact area
One (such as, 1608) cover deep P+Trap 1603 (is shown the most clearly, but is shown as trap in fig. 17
1702) trench contacts 1612.P+Trap 1603 isolates N-Resistor paths 1602 and bottom, such as institute in the cross-sectional view of Figure 17
Show.As Figure 17 shows, embedded P+Deep trap 1702 operates with electric isolution by the N between groove-Region and the electricity that formed
Resistance device.Lateral isolation region 1614 (it can include oxide or other dielectric substance) be formed in resistor structure 1600 with
Electrically insulate described resistor and other circuit unit on nude film.
With reference now to Figure 18, cross-sectional view describes according to an embodiment of the invention that exemplary capacitor structures 1800 is extremely
A few part.Capacitor arrangement 1800 can have the snakelike layout of resistor structure 1600 being similar to be shown in Figure 16, or
It can include the multiple parallel stripes formed by groove 1802.Electrode for capacitors 1802 is filled out by the polysilicon in gate trench
Expect and by the deep N at the bottom of active layer 1806+Trap 1804 is formed.Two regions are all connected to the end at the end of snakelike layout
Son, this shows the most clearly but implies.Lateral isolation region 1808 (it can include oxide or other dielectric substance)
It is formed in capacitor arrangement 1800 to electrically insulate described capacitor and other circuit unit on nude film.
Figure 19 is at least one of horizontal stroke describing the most exemplary P-channel MOSFET 1900
Sectional view.MOSFET 1900 is formed as the amendment of N-channel MOS FET 900 demonstrated in Figure 9, has the most inverted for adulterating
The polarity type of the material of main body (the P main body in Fig. 9) and source electrode and drain region is to form P-channel ldmos transistor.As
It is understood by those skilled in the art that, compared with the process being only used for making N-channel ldmos transistor 900, exclusive for shape
The implant of the P-channel MOSFET becoming to be parallel to described N-channel transistor increases mask count.Such as N-channel ldmos transistor
1000, a simplification in making LDMOS device 1900 includes removing gate trench 1902.To the performance of gained MOSFET
Main impact is the less grid width of per unit area, and this increases the connection resistance R of gained deviceON.This can be by because removing
The alignment relevant with grid polycrystalline silicon overlap above gate trench tail end limits and makes that channel length is shorter to be balanced.
The exemplary electronic components described in Fig. 9 to 19 can be used for construction and comprises power switch, diode and some phases
The BiCMOS circuit of associated circuit.Described BiCMOS process flow comprises and allows to manufacture in Fig. 9 to 17 the basic of the assembly that presents
Mask set, and allow assembly to combine the additional masks subgroup comprising the structure shown in Figure 18 and 19.As made herein
With, phrase " basic mask set " is through broadly defining to refer in order to make based on NFET structure according to an embodiment of the invention
Minimal amount mask level required for one group of device.
With reference now to Figure 20 A to 20F, cross-sectional view jointly describes the most exemplary BiCMOS
Process flow.Described process flow uses basic mask set for amendment based on N-channel LDMOS device demonstrated in Figure 9
Manufacture circuit unit, as described above.Described process is based on having P–Handle wafer and N–The SOI substrate of active layer.
The most by way of example, and not limitation, illustrative process flow process comprises following key step according to an embodiment of the invention:
Use the first masks (LTI mask) by etching groove through active layer 2002 and with oxide or oxide
Combination with polysilicon is filled described groove and is formed lateral dielectric isolation (also known as lateral trench isolation (LTI)), as
Figure 20 A is shown；
Deposition of thick electric field oxide and pattern described thick electric field oxide by active region mask (effect mask)；
The second masks (deep trap mask) is used to be implanted deep into boron or alternative dopings thing to form the deep P in local+Trap 2004 or
The N alternatively become with the alloy used+Trap, wherein close to P+Trap (embedded layer (BL)) 2004 and embedded oxygen
Interface between compound 2006 has peak concentration, as shown in Figure 20 A；
Use the 3rd masks (trench-gate mask) pattern mask to define through active layer 2002 to embedded
The location of one or more gate trench 2008 in trap 2004, as shown in Figure 20 B；Etching has the bottom through cavetto and top
The gate trench at turning, portion, grows hot gate oxide on the sidewall and base wall of described gate trench, and uses polysilicon
2010 fill described grooves, this and be not explicitly shown but in Figure 20 B imply；In alternative embodiments, can omit for shape
Become the step of described gate trench, simplify the NFET structure formed in Fig. 9 whereby to form structure demonstrated in Figure 10.
Carry out DOPOS doped polycrystalline silicon 2010 by phosphor implant or alternative dopings thing and annealing, and silicide layer 2012 is sunk
Amass on top, as Figure 20 B shows；
Use the 4th mask level (polysilicon mask) patterned polysilicon silicide layer 2012 to form grid structure, as figure
20B is shown；
Use the 5th masks (body mask) boron implant to form the edge being self-aligned to multi-crystal silicification nitride layer 2012
Body region 2014.Executive agent diffusion is carried out, as Figure 20 C shows by (for example) exclusive thermal annealing；
The 6th masks (LDD mask) is used to implant phosphor or arsenic or alternative dopings thing with in multi-crystal silicification nitride layer
Formed through lightly doped drain (LDD) extension 2016 at the other edge of 2012, with the edge for forming body region 2014
Relatively, as Figure 20 C shows；
Use the 7th masks (source/drain mask) to be implanted by shallow arsenic and be respectively formed body region 2014 and
In LDD extension 2016 through highly doped source region 218 and drain region 220, as Figure 20 D shows；
Electric field oxide 2022 is deposited on above the top surface of described structure to guarantee that field plate 2024 extends with drain electrode
The predefined spacing on the surface in region 2016, as shown in Figure 20 E；
Use the 8th masks (trench contact mask) etching shallow-source electrode contact trench 2026 and by described trench bottom
Portion implants BF2(connector implantation) is to guarantee main body and deep P+The good ohmic contact in region, as shown in Figure 20 E；
Deposition and sintering lining cutting are in silicide film 2028 (such as, the Ti/WSi of trench contact wallxOr Ti/TiN) to be formed
Electrical short between source region and body region, as shown in Figure 20 E.During sintering process, in Si/Ti interface shape
Become silicide (such as, TiSix).This contact forming method is known to those skilled in the art；
Use the 9th masks (field plate (FPL) mask) to pattern described contact silicide layer, thus allow laterally to prolong
Extending portion with overlapping with grid structure and LDD/ oxide interface close to place formed field plate, as Figure 20 E shows；
Deposit interlayer dielectric film (ILD) 2030 and applied chemistry mechanical polishing step (CMP) or substitutive patterns process,
To realize substantially planar top surface, as Figure 20 F shows；
The tenth masks (via mask) is used to carry out etching vias opening to access source electrode, drain electrode and gate contact region.
Fill through hole with tungsten plug (Ti/TiN/W) or replacement conductive material, and application CMP step is again to planarize described top table
Face, as shown in Figure 20 F；And
Use the 11st masks (metal mask) to be deposited and patterned thick aluminium lamination 2032, to be formed, there is source electrode, leakage
Pole and the top electrodes of gate-bus structures, as shown in Figure 20 F.
As discussed above, in this embodiment, the process of N-channel LDMOS (NFET) transistor needs ten mask layers
Level (that is, step).As mentioned above, if omitting gate trench and processing, then the number of mask level can be reduced to ten.Can
Use optional mask with by etching deep groove through active layer and embedded oxide and with oxide and doped polysilicon
Fill described deep trench and form the electrical contact to substrate.
In order to use same process flow process to form P-channel MOSFET (PFET), need additional masks subgroup.According to the present invention
Illustrative embodiment, use following mask level to carry out exclusive extra implantation: P-BL, P-POLYDOP, P-BODY, P-
LDD, P-S/D and P-CONT, wherein P-BL refers to the p-type doping of embedded layer, and P-POLYDOP refers to realize filling for PFET
The P of the polysilicon put+The mask level of doping.In this case, the N+ doping for the polysilicon of NFET device uses extra
N-POLYDOP mask level.
Therefore, according to embodiments of the invention, the complete mask set during described exemplary BiCMOS comprises most 18
To 20 levels.This process flow allows the design of all exemplary electronic components shown in Fig. 9 to 19, and described design can
For manufacturing Power IC.
Use the process flow manufacturing the basic mask set required for diode power device described herein with upper
The process flow that literary composition is discussed for BiCMOS technology is identical.In the situation of Nch MOSFET, described process is based on having
P-Handle wafer and N-The SOI substrate of active layer.When forming diode structure disclosed herein, this process flow can wrap
Containing following key step:
Through described active layer and fill described with oxide or oxide with the combination of polysilicon by etching groove
Groove and the lateral dielectric isolation (LTI mask) that realizes；
It is implanted deep into boron to be formed at the deep P in the local at embedded oxide interface with peak concentration+(BL covers trap
Mould)；
Pattern mask is to define the position (TRG mask-optional) of gate trench；
Etching has the gate trench of the bottom through cavetto and top corner, grows hot gate oxide, and uses polysilicon
Fill described groove (optionally-for such as the structure only comprising gate trench of Figure 15 to 15B)；
Implanted by phosphor and anneal the described deposited polysilicon that adulterates, and silicide layer is deposited on top
On；
Pattern described multi-crystal silicification nitride layer (POLY mask)；
Boron implant with formed be self-aligned to the edge of the multi-crystal silicification nitride layer for PN diode and be self-aligned to for
Schottky diode is formed the body region of the multi-crystal silicification nitride layer opening of button body contact.Hold by exclusive thermal annealing
Row main diffusion；
Implant phosphor or arsenic to be formed through lightly doped drain extension (referred to as at the other edge of multi-crystal silicification nitride layer
Through lightly doped drain (LDD)) (LDD mask)；
Implanted by shallow arsenic and formed through highly doped cathode zone (S/D mask)；
Deposition field oxide is to guarantee the electric isolution of gate stack structure；
Etch shallow-source electrode (anode) contact trench (CONT mask) and implant BF by channel bottom2(connector implantation) is with really
Protect main body and deep P+The good ohmic contact in region.
Deposit and sinter the lining cutting silicide film (such as, Ti/TiN) in trench contact wall to form anode, main body and deep P+Electrical short between region；
Pattern described contact silicide layer (FPL mask)；
Deposition interlayer dielectric film (ILD) and applied chemistry mechanical polishing step (CMP) are to realize planar top surface；
Etching vias opening is to access anode, negative electrode and gate contact region (via mask).With tungsten plug (Ti/TiN/W)
Fill through hole and application CMP step again to planarize described top surface.
Perform two-step RTP to anneal with stable Schottky contact barrier.
(metal is covered to form the top electrodes with anode, negative electrode and gate-bus structures to be deposited and patterned thick Al layer
Mould).
As discussed above, this technology needs a small amount of mask level.Optional mask can be used to be worn by etching deep groove
Cross active layer and embedded oxide and fill described deep trench with oxide and doped polysilicon and formed substrate
Electrical contact.
Processing details is known to those skilled in the art, and therefore will the most in detail in
Existing.The most by way of example, and not limitation, below for make exemplary 20 volts of N-channel MOS FET situation enumerate for
The illustrative value of specific technical processes parameter:
■SOI substrate:Through lightly doped handle wafer (such as, < 5e14cm-3), the embedded oxide of 0.3 μm, and tool
There is about 1e16cm-30.6 μm effect film of doping.
■The P of embedded + Trap: there is 2e13cm -2Dosage and the boron implant of energy of 180keV.
■Gate trench:0.3 μm width, 0.3 μm is deep, and 0.3 μm is long.
■Multi-crystal silicification nitride layer:0.3 μm polysilicon and 0.1 μm WSi2.Polycrystalline silicon strip width is that 0.45 μm is to cover
Lid gate trench, or the situation for the NFET of non-grid groove is 0.35 μm
■Body region:There is 3e13cm-2Dosage and the boron implant of energy of 30keV, follow-up then have
4e13cm-2Dosage and the second boron implant of energy of 90keV, and annealing in 60 minutes at 1000 DEG C.
■LDD region territory:There is 6e12cm-2Dosage and the phosphor implant of energy of 60keV.
■S/D region:There is 5e15cm-2Dosage and the arsenic implant of energy of 30keV.
■Contact trench:0.4 μm is wide and 0.25 μm is deep.
■Silicide film:Ti (300 angstroms)/TiN (800 angstroms) of annealing at 800 DEG C.
■Connector implant:There is 7e14cm-2Dosage and the BF of energy of 30keV2Implant.
■Top metal:It is patterned with the 0.5 μm metal AlSiCu (1.5 μ m thick) to metal spacing.
Manufacture the basic mask set required for NPN transistor as discussed above can be used for combining Figure 12 A to 12D or
12E (being determined on a case-by-case basis) forms power SOI BJT as described above.Described process is based on having P-Handle wafer and
N-The SOI substrate of active layer, and following key step can be comprised:
Through described active layer and fill described with oxide or oxide with the combination of polysilicon by etching groove
Groove and the lateral dielectric isolation (LTI mask) that realizes；
(BL covers to be formed at the deep P+ trap of the local at embedded oxide interface with peak concentration to be implanted deep into boron
Mould).
Implanted by phosphor and anneal and deposit and doped polysilicon layer.Silicide layer is deposited on top.
Pattern described multi-crystal silicification nitride layer (POLY mask).
Boron implant is to form the base region (BODY mask) at the edge being self-aligned to multi-crystal silicification nitride layer.By exclusive heat
Annealing performs base diffusion (such as, 1000 DEG C reach 60 minutes) to drive implant under the whole length of base stage/grid.
Implant phosphorus or arsenic to be formed through collector extension (LDD that be similar in LDMOS structure) (LDD mask) is lightly doped.
Implanted by shallow arsenic and formed through highly doped emitter-base bandgap grading and collector region (S/D mask).
Etch shallow button contacts groove (CONT mask) and implant BF by channel bottom2(connector implantation) is to guarantee base
The good ohmic contact in pole and deep P+ region.
Deposition and sintering lining cutting are in the silicide film (such as Ti/TiN) of trench contact wall.
Pattern described contact silicide layer, thus allow the little overlapping, with shape of lateral extensions and multi-crystal silicification nitride layer
Become the electrical contact between deep P+ trap and multi-crystal silicification nitride layer.Such as described MOSFET process, this can be used for defining optionally with mask
Field plate extension.
Deposition interlayer dielectric film (ILD) and applied chemistry mechanical polishing step (CMP) are to realize planar top surface.
Etching vias opening is to access emitter-base bandgap grading, collector and base contact regions (via mask).With tungsten plug (Ti/TiN/W)
Fill through hole and application CMP step again to planarize described top surface.
It is deposited and patterned thick Al layer to there is the bus-structured top electrodes of emitter-base bandgap grading, collector and base stage to be formed (metal is covered
Mould).
As discussed above, the process of NPN transistor needs 10 mask levels.Optional mask can be used with by etching
Deep trench passes active layer and embedded oxide and fills described deep trench with oxide and doped polysilicon and formed
Electrical contact to substrate.
In order to form PNP BJT in same process flow process, it is necessary to use modified mask subgroup.Use following mask
Level realize exclusive, additionally implant:
P-BL, P-POLYDOP, P-BODY, P-LDD, P-S/D and P-CONT.
Two kinds of BJT transistor all can be integrated in be had at most as discussed in the disclosure to SOI-BiCMOS
In the SOI-BiCMOS process flow of 18 mask levels.This process flow allows design to can be used for manufacturing the various electricity of Power IC
Sub-component.
Processing details is known to those skilled in the art.Above with respect to the 20V BiCMOS technology as example
Situation enumerates the value of critical technical parameter.
In an embodiment, source electrode and drain bus are positioned at the opposite end of transistance unit, wherein by many
The grid bus that crystal silicon compound layer is formed extends along the center of layout.Described source electrode and drain metal contact have staggered finger-like
Structure, and its pitch equal to as (for example) Fig. 9 A, 10,10A, the pitch of an action cell shown in 11 or 19.
Predefined number action cell is linked together to by bus structures the big grand list of the lateral dimension with hundreds of microns
Unit's (such as 300 × 300 μm).This macroelement method realizes to be scaled to by the repetition of predefined macro unit and connection
Big area (such as 1mm2To 5mm2) transistor layout.For example, in the 7th, 446,375 of issue on November 4th, 2008
The macroelement of a large amount of indivedual action cell (such as, board layout) and those are grand is included for formation described in number United States Patent (USP)
Unit repeated packets together is for use as the various technology of individual device, and the entire content of described United States Patent (USP) is the most also
Enter herein.But, it is different from ' 375 patent describing the device with the vertical current flow to back side electrodes, the present invention
Both the source electrode of LDMOS power device embodiment (it uses transverse current to flow) and drain terminal and source electrode and drain bus
Will be formed in the top side of Semiconductor substrate.It will be appreciated that this macroelement method is applicable to disclosed herein being gained merit
Rate device, comprises MOSFET and BJT transistor and diode.
The feature and the advantage that realize according to embodiments of the invention comprise the one or many person being not limited in the following, but give
Determine embodiment to comprise all these feature or may not only comprise these features:
The unique aspect of ■ exploitation BiCMOS process, as manufactured all integrated powers dress by same group of process steps
Put；
The doping of embedded trap deep for ■ and placement define the breakdown voltage in all SOI power devices and snowslide collision from
The position of sonization；That is, clamp diode is effectively integrated in described device, thereby ensures that high resistance to avalanche；
■ is to minimize the purpose of the SOI-LDMOS power loss in SMPS application to define BiCMOS process flow.Logical
Cross amendment SOI-LDMOS structure and obtain other power device, such as PN diode, Schottky diode and BJT；
■ is by removing N from N-channel LDMOS structure+Source region and obtain PN diode；
■ obtains Schottky diode by removing P body region from PN diode structure；
■ obtains bipolar transistor by the electrical short that removes between source region and body region.By gate stack
It is connected to body region and the construction current bus structure as base terminal；
■ uses chip size packages (CSP) or wafer-class encapsulation (WLP) with on the top surface at the nude film completed
Form current terminal.
In the situation of wiring encapsulation, current bus band leads to terminal pads district.If employing has relatively miscellaneous goods and accounts for
By area and the chip size molectron (CSP or WLP) of the advantage of less parasitic component (such as packaged resistance and inductance), then electricity
(for example, it is (or real at diode or BJT corresponding to grid, drain electrode and source electrode top electrodes 2032 for stream bus structures 2308
Execute other contact in the situation of example)) it is connected to spherical contact 2306 by through hole 2302 and redistributing layer 2304, show as in Figure 23
Meaning property ground is shown.Returning to the previous discussion about macroelement, individual source, drain electrode and grid bus may be connected to multiple similar
Or multiple source electrodes, drain electrode and the gate terminal of same apparatus, allow the plurality of device to operate as single large-scale plant whereby.
Then, multiple macroelement devices can be connected together to be a power dress by the operation of (for example) redistributing layer 2304
Put.That is, individual contacts 2306 can for grid and drain contact 2306 be connected to (for example) multiple source bus line 2308 and
Analog.
As mentioned previously, the important benefits of embodiments of the invention is to readily facilitate power circuit and/or assembly (example
As, driver and power switch) with for implementing the collection on the silicon substrate that the corresponding control circuit of output control device is identical
The ability become.The most by way of example, and not limitation, Figure 21 A to 22E is to describe according to embodiments of the invention for by two
At least one of cross-sectional view of the exemplary BiCMOS handling process that power device is integrated on same substrate.Concrete next
Saying, Figure 21 A to 22E conceptually graphic extension utilizes identical process step with by power N-channel MOS FET and power schottky
Diode is integrated in the example procedure flow process in shared SOI substrate.(citing can be made such as in same process sequence of steps
For) PN diode and other device of BJT.
With reference to Figure 21 A, show at least two zone of action 2102 and 2104.In this embodiment, wherein will be formed some
Each in the zone of action 2102 and 2104 of device includes the corresponding N separated by lateral isolation groove 2108-Active region
Territory 2106, but in other embodiments, the zone of action 2106 is different conductivity-type.Lateral isolation groove 2108 is used for
Separate for forming other of other device and/or structure adjacent to the zone of action 2106.Use previously described process steps,
Sharing and form the zone of action 2106 on embedded oxide skin(coating) 2110, described shared embedded oxide skin(coating) is formed at again N-type or P
On type substrate 2112.The P of embedded+Trap 2114 is formed at corresponding N-In the zone of action 2106, close to embedded oxide skin(coating) 2110
And the interface between the zone of action.
In Figure 21 B, gate oxide level 2120 is formed at the surface of soi structure.Polysilicon layer 2122 is deposited on
In gate oxide level 2120 and be patterned to grid structure.Silicide layer 2124 is optionally deposited on polysilicon gate
In structure 2122.Then pass through the zone of action 2106 of at least some of top of doping embedded trap 2114 to form P main body
Region 2116, the P implant being used in formation P body region whereby is self-aligned to an edge of multi-crystal silicification object area.N district
Territory 2118 is also formed in active layer 2106.In the zone of action 2102, n-quadrant 2118 is formed at the allocated with construction MOSFET
Between the P body region 2116 of structure (NMOS device 1000 such as, shown in Fig. 10).Previously showed in Figure 14 B,
Use identical implantation step to come in the structure of Schottky diode and form n-quadrant 2118.Figure 21 C displaying is formed at P body region
Doped N+ region 2126 in territory 2116 and n-quadrant 2118.Oxide skin(coating) 2128 is formed at the upper face of soi structure extremely
Above a few part.
With reference to Figure 21 D, essentially vertically through oxide skin(coating) 2128, P body region 2116 and contact embedded P+ trap
2114 form groove 2130.Silicide or titanium/titanium nitride layer 2132 are formed in sidewall and the base wall of groove 2130.Lining cutting in
The silicide layer 2132 of groove 2130 contacts the N in P body region 2116+Doped region 2126.Shielding field plate 2134 (its
This embodiment is formed as lining cutting in the lateral extensions of the silicide layer 2132 of groove 2130) overlapping with grid structure and become
Immediately it is bordering on the oxide interface along the N zone of action 2118.Oxide skin(coating) 2136 is subsequently formed the upper face in soi structure
At least some of top.Figure 21 E describes to be etched to form the oxide skin(coating) 2136 of contact trench (that is, through hole), described in connect
Touch groove substance be filled with metal (such as, aluminum) or substitute conducting metal to form device contact 2138.
Can implementing with integrated circuit at least partially of embodiments of the invention.When forming integrated circuit, generally half
Same die is made with repeat patterns on the surface of conductor wafer.Each nude film comprises at least one dress described herein
Put, and other structure and/or circuit can be comprised.From described wafer cutting individual die or individual die is cut into slices, then by institute
State individual die and be packaged into integrated circuit.Those skilled in the art will know how to cut into slices to produce by wafer and encapsulated naked wafers
Raw integrated circuit.The integrated circuit so manufactured is considered as the part of the present invention.
Integrated circuit substantially can be used for wherein can using any of power management techniques according to an embodiment of the invention
In application and/or electronic system.Applicable application and system for implementing technology according to an embodiment of the invention can comprise (but
Be not limited to) mancarried device (comprising smart phone), laptop computer and tablet computing device, net book etc..To incorporate
The system of these integrated circuits is considered as the part of embodiments of the invention.In view of embodiments of the invention presented herein
Teaching, those skilled in the art is by it can be anticipated that other embodiment of technology of embodiments of the invention and application.
The graphic extension plan of embodiments of the invention described herein provides the general of the structure of various embodiments
Understand, and it is not intended to serve as the complete of the equipment of available structure described herein and all elements of system and feature
Whole description.In view of teachings herein, many other embodiments will become apparent to those skilled in the art；Profit
With and be derived from other embodiments so that can make in the case of without departing substantially from the scope of the present invention structure and logic replace and
Change.Described graphic also only representational and not drawn on scale.Therefore, description and graphic being considered as should be had explanation meaning
Justice rather than limiting meaning.
The embodiment of invention subject matter purpose merely for convenience and the most individually and/or jointly by term
" embodiment " refers to, and if in fact have shown that above example or inventive concepts, then be not intended to the application
The scope of case is limited to arbitrary single embodiment or inventive concepts.Therefore, although graphic extension and description spy the most in this article
Determine embodiment, it should be appreciated that available realization replaces, with arranging of purpose, the specific embodiment shown；That is, it is intended that contain
Cover any and all change or the change of various embodiment.In view of teachings herein, the combination of above-described embodiment and this paper
In the other embodiments that do not specifically describes will become apparent to those skilled in the art.
Making a summary through providing to meet 37 C.F.R. § 1.72 (b), it requires reader to be allowed quickly to determine technological invention
The summary of essence.It will be not used in interpretation or limit the scope of claims or contain to submit to this summary to be based on the understanding that
Justice.It addition, in previous embodiment, it can be seen that for simplifying the purpose of the present invention, various features are grouped together
In single embodiment.The inventive method should not be interpreted as reflecting an intention that advocated embodiment to need than each right and want
Seek the middle more feature of feature be expressly recited.
In view of the teaching of embodiments of the invention presented herein, those skilled in the art will it can be anticipated that
Other embodiment of the technology of embodiments of the invention and application.Although being described herein as saying of the present invention with reference to accompanying drawing
Bright property embodiment, it should be appreciated that embodiments of the invention are not limited to those exact embodiment, and those skilled in the art can
In the case of without departing substantially from the scope of the present invention, make various other change and amendment.
Claims (20)
1. the semiconductor junction including at least one metal-oxide semiconductor fieldeffect transistor MOSFET power device
Structure, described semiconductor structure includes:
First insulating barrier, it is formed on substrate；
Active layer, its be formed at described first insulating barrier at least some of on；
Embedded trap, it has the first conductivity-type, is formed in described active layer；
Source region, it has the second conductivity-type, is formed at the upper face close to described active layer in described active layer,
Described source region is electrically connected to described embedded trap,
Drain region, it has described second conductivity-type, and be formed in described active layer close to described active layer is described
Upper face, and spaced with described source region；
Body region, it has described first conductivity-type, is formed in described active layer in described source region with described
Between drain region described embedded trap at least some of on, at least some of horizontal expansion of wherein said source region
In described body region, and described drain region include from described body region extend through lightly doped drain elongated area；
Grid, it is formed at above described active layer, close to the described upper face of described active layer and at least in part in institute
Stating between source region and described drain region, grid structure is electrically insulated with described active layer by gate insulator；
Drain terminal, it is formed on the upper face of active layer and electrically connects with described drain region；
Source terminal, it electrically connects with described source region；
Gate terminal, it electrically connects with described grid；And
Shielding construction, it forms between described grid and described drain region close to the described upper face of described active layer,
Described shielding construction includes that field plate, described field plate are configured to control along top oxide interface, away from described grid
Close to the Electric Field Distribution at the edge of described drain terminal, wherein said top oxide is positioned at described through lightly doped drain extension
On region；
Described embedded trap is configured to form clamp diode together with described active layer, the operation of described clamp diode with
Avalanche region will be punctured be positioned between described embedded trap and described drain terminal, the breakdown potential of described MOSFET power device
Pressure becomes with one or more characteristic of described embedded trap.
Semiconductor structure the most according to claim 1, wherein said embedded trap is close to described first insulating barrier and institute
State the interface between active layer and formed.
Semiconductor structure the most according to claim 1, wherein said shielding construction is at least some of heavy with described grid
Folded, and it is formed to contact the extension of the conductive layer of described source terminal.
Semiconductor structure the most according to claim 3, wherein said shielding construction is electrically connected to described buried at one end
Formula trap and source terminal.
Semiconductor structure the most according to claim 4, it farther includes the source electrode groove being formed in active layer, wherein
Described source terminal is at least partially formed in described source electrode groove, and by described conductive layer electricity in described source electrode groove
It is connected to described embedded trap and source region.
Semiconductor structure the most according to claim 5, wherein said conductive layer includes leading on the wall of described source electrode groove
The lateral extensions of electricity lining.
Semiconductor structure the most according to claim 1, wherein said field plate include described shielding construction close to described leakage
The stepped extension that extreme son is formed.
Semiconductor structure the most according to claim 7, wherein said field plate is formed in insulating barrier, and described field plate includes edge
The described upper face described active layer extends and Part I spaced away, and along described active layer described on
Surface, portion extends and Part II spaced away, and described Part II is closer to described drain electrode end than described Part I
Son, and be spaced apart a distance greater than the described upper face of described Part I with described active layer.
Semiconductor structure the most according to claim 1, wherein said MOSFET power device farther includes described source electrode
Connection between region and described body region, described connection is formed the silicide layer of the wall of lining cutting source contact trenches,
Described source contact trenches etches in described body region through described source region.
Semiconductor structure the most according to claim 1, it farther includes together with described MOSFET power device integrated
Control circuit in common substrate, described control circuit is configured to optionally control the behaviour of described MOSFET power device
Make.
11. semiconductor structures according to claim 1, it farther includes multiple gate trench structure, the plurality of grid
Pole groove structure is formed substantial orthogonality and through described active layer and enters in described embedded trap, described gate trench
Each in structure comprises sidewall and the base wall being formed with insulant on it, each in described gate trench structure
Being filled with conductive material, described gate trench structure is connected with described grid, is wherein applied to the electricity of described gate trench structure
Press operation is to be modulated between described gate trench structure the conduction electric current of flowing, and the amplitude of described conduction electric current is based on described
Applied voltage and be controlled.
12. semiconductor structures according to claim 11, wherein said grid is formed described in described active layer
The extension of the described conductive material filling described groove above upper face.
13. semiconductor structures according to claim 11, wherein said conductive material includes polysilicon.
14. semiconductor structures according to claim 1, wherein said MOSFET device is arranged such that described breakdown voltage
For 12V or bigger.
15. semiconductor structures according to claim 1, at least one MOSFET power device wherein said includes being formed at
Wherein and be organized at least one MOSFET power device multiple described of macroelement, and described semiconductor structure includes being connected to
Together using the multiple described macroelement operated as single MOSFET power device.
16. semiconductor structures according to claim 1, at least one MOSFET power device wherein said includes being formed at
Wherein and link together using the multiple MOSFET power devices operated as single MOSFET power device by bus structures,
Described bus structures include: source bus line, and it is coupled to the described source terminal of the plurality of MOSFET power device；Drain electrode is total
Line, it is coupled to the described drain terminal of the plurality of MOSFET power device；And grid bus, it is coupled to the plurality of
The described gate terminal of MOSFET power device.
17. semiconductor structures according to claim 16, wherein said semiconductor structure is the portion of chip size molectron
Point, described chip size molectron includes being coupled to described bus structures source electrode, drain electrode and the redistribution of gate external contact
Layer.
18. 1 kinds of formation include partly leading of at least one metal-oxide semiconductor fieldeffect transistor MOSFET power device
The method of body structure, said method comprising the steps of:
Substrate is formed the first insulating barrier；
Described first insulating barrier at least some of on formed active layer；
At least one with the first conductivity-type is formed close to the interface between described active layer and described first insulating barrier
Embedded trap；
On the upper face of described semiconductor structure described embedded trap at least some of above and close to active layer
Upper face forms grid structure, and described grid structure is electrically insulated with described active layer by gate insulator；
In active layer, the upper face close to described active layer forms the source region with the second conductivity-type, described source
Territory, polar region is electrically connected to described embedded trap,
Close to described upper face and the landform spaced with described source region of described active layer in described active layer
Become there is the drain region of described second conductivity-type；
In described active layer between described source region and described drain region at least some of at described embedded trap
Upper formation has the body region of described first conductivity-type, extending transverse at least partially of wherein said source region
In described body region, and described drain region include from described body region extend through lightly doped drain elongated area；
Form the source terminal electrically connected with described embedded trap and described source region；And
The drain terminal being formed on the described upper face of described active layer and electrically connect with described drain region；And
Described upper face close to described active layer forms shielding construction between described grid and described drain region, described
Shielding construction include field plate, described field plate be configured to control along top oxide interface away from described grid closest to
The Electric Field Distribution at the edge of described drain terminal, wherein said top oxide is positioned at described through lightly doped drain elongated area
On,
Wherein said embedded trap is configured to form clamp diode together with described active layer, and described clamp diode is grasped
Make to be positioned between described embedded trap and described drain terminal so that avalanche region will be punctured, hitting of described MOSFET power device
Wear voltage to become with one or more characteristic of described embedded trap.
19. methods according to claim 18, it further includes steps of etching source electrode groove, and passes through conduction
Layer contacts described source terminal, source region and embedded trap, and described conductive layer prolongs from described groove and above described grid
Stretch to form described shielding construction.
20. methods according to claim 19, wherein said field plate is formed in insulating barrier, and described field plate includes along institute
The described upper face stating active layer extends and Part I spaced away, and the described top table along described active layer
Face extends and Part II spaced away, and described Part II is closer to described drain terminal than described Part I,
And be spaced apart a distance greater than the described upper face of described Part I with described active layer.
Applications Claiming Priority (11)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261677660P | 2012-07-31 | 2012-07-31 | |
| US61/677,660 | 2012-07-31 | ||
| US13/887,704 | 2013-05-06 | ||
| US13/887,704 US8994105B2 (en) | 2012-07-31 | 2013-05-06 | Power device integration on a common substrate |
| US13/939,490 | 2013-07-11 | ||
| US13/939,422 US8674440B2 (en) | 2012-07-31 | 2013-07-11 | Power device integration on a common substrate |
| US13/939,451 | 2013-07-11 | ||
| US13/939,451 US9412881B2 (en) | 2012-07-31 | 2013-07-11 | Power device integration on a common substrate |
| US13/939,422 | 2013-07-11 | ||
| US13/939,490 US8928116B2 (en) | 2012-07-31 | 2013-07-11 | Power device integration on a common substrate |
| PCT/US2013/050700 WO2014022092A1 (en) | 2012-07-31 | 2013-07-16 | Power device integration on a common substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104769715A CN104769715A (en) | 2015-07-08 |
| CN104769715B true CN104769715B (en) | 2016-11-30 |
Family
ID=
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102097327A (en) * | 2009-12-02 | 2011-06-15 | 万国半导体股份有限公司 | Dual channel trench LDMOS transistors and BCD process with deep trench isolation |
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102097327A (en) * | 2009-12-02 | 2011-06-15 | 万国半导体股份有限公司 | Dual channel trench LDMOS transistors and BCD process with deep trench isolation |
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