CN104765649A - Data storage method, storage and electronic equipment - Google Patents
Data storage method, storage and electronic equipment Download PDFInfo
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- CN104765649A CN104765649A CN201410003115.6A CN201410003115A CN104765649A CN 104765649 A CN104765649 A CN 104765649A CN 201410003115 A CN201410003115 A CN 201410003115A CN 104765649 A CN104765649 A CN 104765649A
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Abstract
The invention relates to the technical field of computer and discloses a data storage method, a storage and electronic equipment. The data storage method, storage and electronic equipment solve the technical problem of complex reading-writing circuit of a storage of the prior art. The data storage method is used for the storage, the storage has N physical pages, wherein the i physical page of the N physical pages is corresponding to the i code error rate of N not identical code error rates, wherein i is any integer of 1 to N; the data storage method includes that confirming M logic pages; dividing the i logic page of the M logic pages into N parts of data of the i logic page, wherein i is any integer of 1 to M; processing the N parts of data of the i logic page, and outputting the i error correction code corresponding to the i logic page and N parts of data of the i logic page; storing the N parts of data of the i logic page in the N physical pages in sequence, and storing the i error correction code in the N physical page of the N physical pages.
Description
Technical field
The present invention relates to field of computer technology, particularly the method, storer and the electronic equipment that store of a kind of data.
Background technology
Along with the fast development of electronic technology, the storage medium of electronic equipment also gets more and more, such as: SLC(Single-Level Cell), also namely: 1bit/cell, the data that storage element (cell) stores a bit (bit) deposited by an one storer; MLC(Multi-Level Cell), also namely: 2bit/cell, the data that storage element (cell) stores two bits (bit) deposited by an one storer; TLC(Triple-Level Cell), also namely: 3bit/cell, an one storer is deposited storage element (cell) and is stored data of three bits (bit) etc.
In TLC-3NAND Flash, due to distribution and the binary-coded specific corresponding relation of physics voltage, make MSB(Most Significant Bit: highest significant position), CSB(Center SignificantBit: middle significance bit), LSB(Least Significant bit: least significant bit (LSB)) Physical Page has different voltage coverages, bit error rate on it also can be different, as shown in table 1, be the memory location of logical page (LPAGE) in prior art in Physical Page:
Table 1
| Memory location | Logical page data |
| MSB | a1,a2,a3,a4,a5,a6…a(N-2),a(N-1),a(N-0) |
| CSB | b1,b2,b3,b4,b5,b6…b(N-2),b(N-1),b(N-0) |
| LSB | c1,c2,c3,c4,c5,c6,…c(N-2),c(N-1),c(N-0) |
As can be seen from Table 1, Physical Page different in prior art can store different logical page data, and under normal circumstances, the error rate of MSB Physical Page group is the highest, if logically page and Physical Page one to one mode store, so will the error rate of the logical page (LPAGE) be stored on MSB Physical Page be caused higher, and then cause data hold time shorter, prior to the alarm threshold of two other logical page (LPAGE) close to error correcting code (ECC), trigger data refresh scheme starts data copy, causes extra to write amplification.
In prior art, in order to solve the problem, following scheme can be adopted:
For different Physical Page, the ECC coding circuit of different error correction intensity is adopted to carry out Error Correction of Coding, such as: because the error rate of MSB Physical Page group is the highest, so adopt the highest ECC coding circuit of error correction intensity to carry out Error Correction of Coding to it, and for CSB and LSB Physical Page, then the lower ECC coding circuit of error correction intensity can be adopted to carry out Error Correction of Coding etc. to it.
Present invention applicant finds at least there is following technical matters in prior art:
Due in prior art, the ECC coding circuit of different error correction intensity is adopted to carry out Error Correction of Coding for different Physical Page, and the error correction intensity of ECC coding circuit is higher, its code efficiency is lower, when code efficiency is lower, then cause the storage space shared by redundant data comparatively large, even exceed the redundant storage space reserved by chip production manufacturer in NAND Flash.At this moment, the valid data of a logical page (LPAGE) and coded data will exceed the border of Physical Page, cause a logical page (LPAGE) to take more than one Physical Page and store.The logical page (LPAGE) that code efficiency is low can take the redundant physical storage space that the high logical page (LPAGE) of code efficiency is not used.At this moment, although the total amount of data of three logical page (LPAGE)s can take the total volume space of three Physical Page jointly, but the logical page (LPAGE) that code efficiency is low is deposited across Physical Page border, so cause logical page (LPAGE) on Physical Page deposit can not with the boundary alignment of Physical Page, and then read/write circuit can be caused complicated.
Summary of the invention
A kind of method that the embodiment of the present invention provides data to store and electronic equipment, to solve the technical matters of the read/write circuit complexity of storer in prior art.
According to a first aspect of the invention, a kind of method that data store is provided, be applied to a storer, described storer has N number of Physical Page, and N is positive integer, wherein, i-th Physical Page in described N number of Physical Page is corresponding with i-th code error rate in N number of incomplete same code error rate, and wherein, i is arbitrary integer between 1 to N, described method comprises: determine M logical page (LPAGE), wherein M be more than or equal to 1 integer; I-th logical page (LPAGE) in a described M logical page (LPAGE) is divided into N part i-th logical page data, and i is arbitrary integer of 1 to M; Described N part i-th logical page data is processed, exports i-th Error Correction of Coding corresponding with described i-th logical page (LPAGE) and described N part i-th logical page data; Described N part i-th logical page data is stored in described N number of Physical Page successively, and described i-th Error Correction of Coding is stored in the N number of Physical Page in described N number of Physical Page.
In conjunction with first aspect, in the implementation that the first is possible, described i-th logical page (LPAGE) in a described M logical page (LPAGE) is divided into N part i-th logical page data, is specially: i-th logical page (LPAGE) in a described M logical page (LPAGE) is on average divided into described N part i-th logical page data.
In conjunction with first aspect, in the implementation that the second is possible, described described N part i-th logical page data to be processed, export i-th Error Correction of Coding corresponding with described i-th logical page (LPAGE) and described N part i-th logical page data, specifically comprise: getting j is successively 1 to N, jth part i-th logical page data in described N part i-th logical page data is inputted at least one error correcting code circuitry successively; Described jth part i-th logical page data is stored at least one error correcting code circuitry described; And export described jth part i-th logical page data successively; When storing the total data of described N part i-th logical page data at least one error correcting code circuitry described, by at least one error correcting code circuitry described, Error Correction of Coding process is carried out to described i-th N partial data, and then obtain described i-th Error Correction of Coding.
In conjunction with the implementation that the second of first aspect is possible, in the 3rd possible implementation, when at least one error correcting code circuitry described is M error correcting code circuitry, jth part i-th logical page data in described N part i-th logical page data is inputted at least one error correcting code circuitry successively, be specially: at synchronization, the N part of the jth in a described M logical page (LPAGE) i-th logical page data inputted the jth error correcting code circuitry in a described M error correcting code circuitry; Describedly by described error correcting code circuitry, Error Correction of Coding process is carried out to described i-th N partial data, and then obtain described i-th Error Correction of Coding, specifically comprise: by a described M error correcting code circuitry is parallel, described N part i-th logical page data is processed, and then export i-th Error Correction of Coding corresponding with described i-th logical page (LPAGE) respectively.
In conjunction with the implementation that the second of first aspect is possible, in the 4th possible implementation, when at least one error correcting code circuitry described is the first error correcting code circuitry, described jth part i-th logical page data in described N part i-th logical page data is inputted at least one error correcting code circuitry successively, be specially: be specially: get the integer that j is 1 to N successively, the jth partial data of each logical page (LPAGE) of a described M logical page (LPAGE) is inputted described first error correcting code circuitry successively; Describedly by described error correcting code circuitry, Error Correction of Coding process is carried out to described i-th N partial data, and then obtain described i-th Error Correction of Coding, be specially: by described first error correcting code circuitry, serial processing is carried out to described N part i-th logical page data, and then export described i-th Error Correction of Coding and described N part i-th logical page data successively.
In conjunction with first aspect, in the 5th kind of possible implementation, described described N part i-th logical page data to be processed, export i-th Error Correction of Coding corresponding with described i-th logical page (LPAGE) and described N part i-th logical page data, specifically comprise: get the integer that j is 1 to N successively, by the second error correcting code circuitry, Error Correction of Coding is carried out to jth part i-th logical page data in described N part i-th logical page data, and then obtain the sub-Error Correction of Coding of the i-th logical page (LPAGE) jth; The sub-Error Correction of Coding of the i-th logical page (LPAGE) jth described in buffer memory in described second error correcting code circuitry also exports described jth part i-th logical page data by described second error correcting code circuitry; When j is N, obtain the sub-Error Correction of Coding of the i-th logical page (LPAGE) 1 to j as described i-th Error Correction of Coding, and export described i-th Error Correction of Coding by described second error correcting code circuitry.
In conjunction with the 5th kind of possible implementation of first aspect, in the 6th kind of possible implementation, describedly by the second error correcting code circuitry, Error Correction of Coding is carried out to jth part i-th logical page data in described N part i-th logical page data, and then obtain the sub-Error Correction of Coding of the i-th logical page (LPAGE) jth, specifically comprise: get the integer that i is 1 to M successively, by described second error correcting code circuitry of jth part i-th logical page data input in described N part i-th logical page data; By described second error correcting code circuitry, Error Correction of Coding process is carried out to described jth part i-th logical page data, and then obtain the sub-Error Correction of Coding of the i-th logical page (LPAGE) jth described in the.
According to a second aspect of the invention, a kind of storer is provided, comprise: storage unit, described storage unit has N number of Physical Page, N is positive integer, and wherein, i-th Physical Page in described N number of Physical Page is corresponding with i-th code error rate in N number of incomplete same code error rate, wherein, i is arbitrary integer between 1 to N; Control circuit, is connected to described storage unit, and for obtaining M logical page (LPAGE), wherein, i-th logical page (LPAGE) in a described M logical page (LPAGE) is divided into N part i-th logical page data, and i is the integer of 1 to M; And described N part i-th logical page data is processed, exports i-th Error Correction of Coding corresponding with described i-th logical page (LPAGE) and described N part i-th logical page data; And described N part i-th logical page data is stored in described N number of Physical Page successively, and described i-th Error Correction of Coding is stored in the N number of Physical Page in described N number of Physical Page.
In conjunction with second aspect, in the implementation that the first is possible, described i-th logical page (LPAGE) is on average divided into described N part i-th logical page data.
In conjunction with second aspect, in the implementation that the second is possible, described control circuit, is specially: at least one error correcting code circuitry; At least one error correcting code circuitry described, specifically for: getting j is successively 1 to N, obtains jth part i-th logical page data in described N part i-th logical page data; And store described jth part i-th logical page data; And the jth Physical Page described jth part i-th logical page data be stored in described N number of Physical Page; And when storing the total data of described N part i-th logical page data, by described error correcting code circuitry, Error Correction of Coding process being carried out to described i-th N partial data, and then obtaining described i-th Error Correction of Coding.
In conjunction with the implementation that the second of second aspect is possible, in the implementation that the third is possible, at least one error correcting code circuitry described is specially: M error correcting code circuitry; A described M error correcting code circuitry, specifically for: at synchronization, the jth error correcting code circuitry in a described M error correcting code circuitry obtains a jth N part i-th logical page data in a described M logical page (LPAGE); And by a described M error correcting code circuitry is parallel, described N part i-th logical page data is processed, and then export i-th Error Correction of Coding corresponding with described i-th logical page (LPAGE) respectively.
In conjunction with the implementation that the second of second aspect is possible, in the 4th kind of possible implementation, at least one error correcting code circuitry described is specially: the first error correcting code circuitry; Described first error correcting code circuitry, is specially: get the integer that j is 1 to N successively, obtains the jth partial data of each logical page (LPAGE) of a described M logical page (LPAGE); And serial processing is carried out to described N part i-th logical page data, and then export described i-th Error Correction of Coding and described N part i-th logical page data successively.
In conjunction with second aspect, in the 5th kind of possible implementation, described control circuit, is specially: the second error correcting code circuitry; Described second error correcting code circuitry, specifically for: get the integer that j is 1 to N successively, Error Correction of Coding is carried out to jth part i-th logical page data in described N part i-th logical page data, and then obtain the sub-Error Correction of Coding of the i-th logical page (LPAGE) jth; And the sub-Error Correction of Coding of the i-th logical page (LPAGE) jth described in buffer memory export described jth part i-th logical page data; And when j is N, obtains the sub-Error Correction of Coding of the i-th logical page (LPAGE) 1 to j as described i-th Error Correction of Coding, and export described i-th Error Correction of Coding.
In conjunction with the 5th kind of possible implementation of second aspect, in the 6th kind of possible implementation, described second error correcting code circuitry, specifically for: get the integer that i is 1 to M successively, obtain jth part i-th logical page data in described N part i-th logical page data; And Error Correction of Coding process is carried out to described jth part i-th logical page data, and then obtain the sub-Error Correction of Coding of the i-th logical page (LPAGE) jth described in the.
According to a third aspect of the invention we, a kind of electronic equipment is provided, comprises: shell; The storer that any embodiment of the present invention is introduced, is arranged at described enclosure; Processor, is connected to described storer, processes for the data stored described storer.
Beneficial effect of the present invention is as follows:
Due in embodiments of the present invention, each logical page (LPAGE) in M logical page (LPAGE) is divided into N part, and this N part is processed respectively, thus obtain the Error Correction of Coding of each logical page (LPAGE) of this M logical page (LPAGE), finally every part of each logical page (LPAGE) in this M logical page (LPAGE) is stored in N number of Physical Page successively and the Error Correction of Coding of its correspondence is stored in last Physical Page, in other words same logical page (LPAGE) can be divided into N part and be stored in N number of Physical Page, thus when storing multiple logical page (LPAGE) in multiple Physical Page, can ensure that the length shared by Error Correction of Coding between this multiple logical page (LPAGE) is all comparatively average, so when depositing logical page (LPAGE) in Physical Page, the space that each logical page (LPAGE) takies is more or less the same, and then can align store when storing, to make read-write convenient, thus reach the technique effect of the complexity reducing read/write circuit.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of date storage method in the embodiment of the present invention;
Fig. 2 is the process flow diagram to the first processing mode that N part i-th logical page data processes in embodiment of the present invention date storage method;
Fig. 3 is the structural drawing of the first error correcting code circuitry in embodiment of the present invention date storage method;
Fig. 4 is the process flow diagram to the second processing mode that N part i-th logical page data processes in embodiment of the present invention date storage method;
Fig. 5 is the structural drawing of the second error correcting code circuitry in embodiment of the present invention date storage method;
Fig. 6 is the schematic diagram being carried out Error Correction of Coding process in this inventive embodiments date storage method by the second error correcting code circuitry 3 logical page (LPAGE)s;
Fig. 7 is the structural drawing of storer in the embodiment of the present invention;
Fig. 8 is the structural drawing of electronic equipment in the embodiment of the present invention.
Embodiment
Method, storer and electronic equipment that the embodiment of the present invention provides a kind of data to store, for solving the technical matters of the read/write circuit complexity of storer in prior art.
Technical scheme in the embodiment of the present invention is solve above-mentioned technical matters, and general thought is as follows:
A kind of method that data store is provided, be applied to a storer, storer has N number of Physical Page, N is positive integer, and wherein, i-th Physical Page in N number of Physical Page is corresponding with i-th code error rate in N number of incomplete same code error rate, wherein, i is arbitrary integer between 1 to N, and method comprises: determine M logical page (LPAGE), wherein M be more than or equal to 1 integer; I-th logical page (LPAGE) in M logical page (LPAGE) is divided into N part i-th logical page data, and i is arbitrary integer of 1 to M; N part i-th logical page data is processed, exports i-th Error Correction of Coding corresponding with i-th logical page (LPAGE) and N part i-th logical page data; N part i-th logical page data is stored in N number of Physical Page successively, and i-th Error Correction of Coding is stored in the N number of Physical Page in N number of Physical Page.
Due in such scheme, when the data of logical page (LPAGE) are stored in storer, same logical page (LPAGE) can be divided into N part and be stored in N number of Physical Page, thus when storing multiple logical page (LPAGE) in multiple Physical Page, can ensure that the length shared by Error Correction of Coding between this multiple logical page (LPAGE) is all comparatively average, so when depositing logical page (LPAGE) in Physical Page, the space parallax that each logical page (LPAGE) takies is few, and then can align store when storing, to make read-write convenient, thus reach the technique effect of the complexity reducing read/write circuit.
In order to better understand technique scheme, below by accompanying drawing and specific embodiment, technical solution of the present invention is described in detail, the specific features being to be understood that in the embodiment of the present invention and embodiment is the detailed description to technical solution of the present invention, instead of the restriction to technical solution of the present invention, when not conflicting, the technical characteristic in the embodiment of the present invention and embodiment can combine mutually.
First aspect, a kind of method that the embodiment of the present invention provides data to store, be applied to a storer, storer has N number of Physical Page, and N is positive integer, wherein, i-th Physical Page in N number of Physical Page is corresponding with i-th code error rate in N number of incomplete same code error rate, and wherein, i is arbitrary integer between 1 to N, wherein, storer is such as: TLC-3NAND Flash; N number of Physical Page is such as: MSB, CSB, LSB etc.
Please refer to Fig. 1, the method specifically comprises the following steps:
Step S101: determine M logical page (LPAGE), wherein M be more than or equal to 1 integer;
Step S102: i-th logical page (LPAGE) in M logical page (LPAGE) is divided into N part i-th logical page data, i is arbitrary integer of 1 to M;
Step S103: process N part i-th logical page data, exports i-th Error Correction of Coding corresponding with i-th logical page (LPAGE) and N part i-th logical page data;
Step S104: N part i-th logical page data is stored in N number of Physical Page successively, and i-th Error Correction of Coding is stored in the N number of Physical Page in N number of Physical Page.
In specific implementation process, in step S101, M logical page (LPAGE) can be the logical page (LPAGE) identical with N number of Physical Page quantity, that is to say that M and N is identical; M logical page (LPAGE) also can be the logical page (LPAGE) different from N number of Physical Page quantity, and also namely M and N is different value, and the embodiment of the present invention is not restricted.
In specific implementation process, in step S102, i-th logical page (LPAGE) in M logical page (LPAGE) is divided into N part i-th logical page data, is specially:
I-th logical page (LPAGE) in M logical page (LPAGE) is on average divided into N part i-th logical page data.
In this case, the storage space of M logical page (LPAGE) shared by each Physical Page is identical, and then can ensure that the Error Correction of Coding length of this M logical page (LPAGE) is identical, store so can further ensure can align when storing, thus further reduce the complexity of read/write circuit.
In specific implementation process, in step S103, N part i-th logical page data is processed, and then obtain i-th Error Correction of Coding corresponding with i-th logical page (LPAGE) and N part i-th logical page data can have multiple processing procedure, two kinds of enumerating below are wherein introduced, certainly, in specific implementation process, be not limited to following two kinds of situations.
The first, please refer to Fig. 2, processes N part i-th logical page data, exports i-th Error Correction of Coding corresponding with i-th logical page (LPAGE) and N part i-th logical page data specifically comprises the following steps:
Step S201: getting j is successively 1 to N, inputs at least one error correcting code circuitry successively by jth part i-th logical page data in N part i-th logical page data;
Step S202: store jth part i-th logical page data at least one error correcting code circuitry; And export jth part i-th logical page data successively;
Step S203: when storing the total data of N part i-th logical page data at least one error correcting code circuitry, carries out Error Correction of Coding process by least one error correcting code circuitry to i-th N partial data, and then obtains the i-th Error Correction of Coding.
In specific implementation process, at least one error correcting code circuitry of step S201 can be a road error correcting code circuitry, also can be multichannel error correcting code circuitry, wherein based on the difference of at least one error correcting code circuitry, and then mode jth part i-th logical page data in N part i-th logical page data being inputted successively at least one error correcting code circuitry is also different, two kinds of enumerating below are wherein introduced, certainly, in specific implementation process, be not limited to following two kinds of situations.
1. when at least one error correcting code circuitry is M error correcting code circuitry, jth part i-th logical page data in N part i-th logical page data is inputted at least one error correcting code circuitry successively, be specially: at synchronization, by the jth error correcting code circuitry in the N part of the jth in M logical page (LPAGE) i-th logical page data input M error correcting code circuitry.
Specifically, namely adopt different error correcting code circuitries to process respectively for this M logical page (LPAGE), the N partial data of each logical page (LPAGE) of such M logical page (LPAGE) can to walk abreast the error correcting code circuitry inputted successively corresponding to it at synchronization.
2. when at least one error correcting code circuitry is the first error correcting code circuitry, jth part i-th logical page data in N part i-th logical page data is inputted at least one error correcting code circuitry successively, be specially: be specially: get the integer that j is 1 to N successively, the jth partial data of each logical page (LPAGE) of M logical page (LPAGE) is inputted the first error correcting code circuitry successively, as shown in Figure 3, be the schematic diagram of the first error correcting code circuitry, the first error correcting code circuitry specifically comprises:
Data input pin 30;
Error correction circuit 31, is connected to data input pin 30;
Data output end 32, is connected to data input pin 30 and error correction circuit 31, and jth part i-th logical page data wherein inputting data input pin 30 was both directly exported by data output end 32, and then was stored in a jth logical page (LPAGE); Be stored in again error correction circuit 31, after making storing N part i-th logical page data in error correction circuit 31, can be processed by error correction circuit 31 pairs of N parts i-th logical page data, and then obtain the i-th Error Correction of Coding.
Wherein, owing to only there is an error correcting code circuitry, Error Correction of Coding process is carried out to this M logical page (LPAGE); so jth partial data serial input first error correcting code circuitry of each logical page (LPAGE) of this M logical page (LPAGE); in this situation; usually first the jth partial data of each logical page (LPAGE) can be inputted the first error correcting code circuitry, and then jth+1 partial data of each logical page (LPAGE) is inputted error correcting code circuitry.Such as, if there are 3 logical page (LPAGE)s, so first, the Part I data of first logical page (LPAGE) in 3 logical page (LPAGE)s are inputted the first error correcting code circuitry, then the Part I data of second logical page (LPAGE) in 3 logical page (LPAGE)s are inputted the first error correcting code circuitry, then the Part I data of the logical page (LPAGE) of the 3rd in 3 logical page (LPAGE)s are inputted the first error correcting code circuitry; Then the Part II data of first logical page (LPAGE) in 3 logical page (LPAGE)s are inputted the first error correcting code circuitry ..., the like.
Wherein, in step S202, during owing to needing to store the total data of i-th logical page (LPAGE) at least one error correcting code circuitry, Error Correction of Coding process can be carried out to i-th logical page data by least one error correcting code circuitry, so after jth part i-th logical page data is inputted at least one error correcting code circuitry, just at least one error correcting code circuitry can be stored in; And export jth part i-th logical page data successively;
In specific implementation process, in step S203, when jth part i-th logical page data being stored in the Physical Page of the jth in N number of Physical Page, can after jth part i-th logical page data be inputted at least one error correcting code circuitry, just exported by least one error correcting code circuitry, and then be stored in the jth Physical Page in N number of Physical Page; Also can be stored at least one error correcting code circuitry N part i-th logical page data total data and after Error Correction of Coding process is carried out to total data, again jth part i-th logical page data is stored in a jth Physical Page, opportunity jth part i-th logical page data is stored in a jth Physical Page at which kind of, the embodiment of the present invention is not restricted.
In step S203, based on the difference of at least one error correcting code circuitry, and then it is also different to carry out the process of Error Correction of Coding process to i-th N partial data, below two kinds that enumerate wherein are introduced respectively, certainly, in specific implementation process, be not limited to following two kinds of situations.
1. when at least one error correcting code circuitry is M error correcting code circuitry, in step S204, by error correcting code circuitry, Error Correction of Coding process is carried out to i-th N partial data, and then obtains the i-th Error Correction of Coding, specifically comprise:
By M error correcting code circuitry is parallel, N part i-th logical page data is processed, and then export i-th Error Correction of Coding corresponding with i-th logical page (LPAGE) respectively.
Owing to including M error correcting code circuitry, this M error correcting code circuitry can carry out error correcting code circuitry process to the Different Logic page data of M logical page (LPAGE) respectively, so parallel processing can be carried out by M the logical page data that this M error correcting code circuitry is corresponding to this M logical page (LPAGE), and then can improve processing speed.
2. when at least one error correcting code circuitry is the first error correcting code circuitry, in step S204, by error correcting code circuitry, Error Correction of Coding process is carried out to i-th N partial data, and then obtains the i-th Error Correction of Coding, be specially:
By the first error correcting code circuitry, serial processing is carried out to N part i-th logical page data, and then export i-th Error Correction of Coding and N part i-th logical page data successively.
Carry out being the first error correcting code circuitry due at least one error correcting code circuitry, so can only process for the data of a logical page (LPAGE) at every turn, because of but serial processing, in this case, owing to only needing an error correcting code circuitry, so have the technique effect reduced costs.
The second, please refer to Fig. 4, processes N part i-th logical page data, exports i-th Error Correction of Coding corresponding with i-th logical page (LPAGE) and N part i-th logical page data, specifically comprises:
Step S401: get the integer that j is 1 to N successively, carries out Error Correction of Coding by the second error correcting code circuitry to jth part i-th logical page data in N part i-th logical page data, and then obtains the sub-Error Correction of Coding of the i-th logical page (LPAGE) jth;
Step S402: the sub-Error Correction of Coding of buffer memory i-th logical page (LPAGE) jth in the second error correcting code circuitry also exports jth part i-th logical page data by the second error correcting code circuitry;
Step S403: when j is N, obtains the sub-Error Correction of Coding of the i-th logical page (LPAGE) 1 to j as the i-th Error Correction of Coding, and exports the i-th Error Correction of Coding by the second error correcting code circuitry.
As shown in Figure 5, be the structural drawing of the second error correcting code circuitry, the second error correcting code circuitry specifically comprises:
Data Input Interface 50, for inputting jth part i-th logical page data in N part i-th logical page data;
Error correction circuit 51, for carrying out Error Correction of Coding to jth part i-th logical page data in N part i-th logical page data, and then obtains the sub-Error Correction of Coding of the i-th logical page (LPAGE) jth;
M cache register group 52, i-th buffer group wherein in M cache register group 52 is for storing the N number of sub-Error Correction of Coding corresponding to the i-th logical page (LPAGE);
Switch unit 53 between page, being connected to error correction circuit 51 and M cache register group 52, for receiving the sub-Error Correction of Coding of the i-th logical page (LPAGE) jth of error correction circuit 51, M cache register group 52 being switched to i-th cache register group;
Data output interface 54, is connected to Data Input Interface 50 and M cache register group 52, for exporting jth part i-th logical page data and the i-th Error Correction of Coding.
In specific implementation process, in step S401, obtain jth part i-th logical page data in N part i-th logical page data in the second error correcting code circuitry after, just Error Correction of Coding is carried out to it and obtain the sub-Error Correction of Coding of the i-thth logical page (LPAGE) jth, and do not need to wait for that N part i-th logical page data just carries out Error Correction of Coding after all inputting the second error correcting code circuitry.
Further, in step S401, by the second error correcting code circuitry, Error Correction of Coding is carried out to jth part i-th logical page data in N part i-th logical page data, and then obtains the sub-Error Correction of Coding of the i-th logical page (LPAGE) jth, specifically comprise:
Get the integer that i is 1 to M successively, jth part i-th logical page data in N part i-th logical page data is inputted the second error correcting code circuitry;
By the second error correcting code circuitry, Error Correction of Coding process is carried out to jth part i-th logical page data, and then obtain the sub-Error Correction of Coding of the i-thth logical page (LPAGE) jth.
Specifically, namely by by the second error correcting code circuitry, Error Correction of Coding is being carried out to jth part i-th logical page data in N part i-th logical page data, first the Part I data of this M logical page (LPAGE) input the second error correcting code circuitry successively, and then carry out Error Correction of Coding process by the partial data of the second error correcting code circuitry to this M logical page (LPAGE), obtain the first sub-error correcting code circuitry of each logical page (LPAGE) of this M logical page (LPAGE); And then the Part II data of each logical page (LPAGE) of this M logical page (LPAGE) are inputted the second error correcting code circuitry ..., the like.Or to comprise 3 logical page (LPAGE)s, and these 3 logical page (LPAGE)s are stored in 3 Physical Page is example, and please refer to table 2, these 3 logical page (LPAGE)s specifically comprise following data:
Table 2
As shown in Figure 6, for carrying out the schematic diagram of Error Correction of Coding to these 3 logical page data:
Wherein, first by 1/3 of P1 input the second error correcting code circuitry, then Error Correction of Coding is carried out by 1/3 data of error correction circuit 51 couples of P1, and then the sub-Error Correction of Coding of front 1/3 of acquisition P1, then be stored in first buffer Parasites Fauna in M cache register group 52, and 1/3 data before P1 are stored in first Physical Page; Then the second buffer Parasites Fauna is switched to by switch unit between page 53, and then by 1/3 carrying out Error Correction of Coding before error correction circuit 53 couples of P2, thus obtain the sub-Error Correction of Coding of front 1/3 of P2, and be stored in the second buffer Parasites Fauna, and 1/3 data before P2 are stored in first Physical Page and before being stored in P1 after 1/3 data; Then the 3rd buffer Parasites Fauna is switched to by switch unit between page 53, and then by 1/3 carrying out Error Correction of Coding before error correction circuit 53 couples of P3, thus obtain the sub-Error Correction of Coding of front 1/3 of P3, and be stored in the 3rd buffer Parasites Fauna, and 1/3 data before P3 are stored in first Physical Page and before being stored in P2 after 1/3 data; And then switch to the first buffer Parasites Fauna by switch unit between page 53, thus carry out Error Correction of Coding by centre 2/3 data of error correction wing 53 couples of P1, thus obtain the sub-Error Correction of Coding of the centre 2/3 of P1, and be stored in the first buffer Parasites Fauna, and centre 1/3 data of P2 are stored in second Physical Page etc.
And after P1, P2, P3 Error Correction of Coding completes, in M buffer Parasites Fauna 52, then store P1, P2, P3 Error Correction of Coding successively, then it is exported by data output interface 54, and be stored in the 3rd Physical Page respectively; After wherein the Error Correction of Coding of P1 is stored in 3/3 data of P1; After the Error Correction of Coding of P2 is stored in 3/3 data of P2; After the Error Correction of Coding of P3 is stored in 3/3 data of P3.
In step S402, second Error Correction of Coding is after carrying out Error Correction of Coding to jth part i-th logical page data, just directly export jth part i-th logical page data and be stored in jth Physical Page, and without the need to waiting for that the second error correcting code circuitry just stores after obtaining the total data of the i-th logical page (LPAGE).
In step S403, the Error Correction of Coding of each partial data of buffer memory i-th logical page (LPAGE) in the second error correcting code circuitry, such as: be stored in i-th cache register group in this M cache register group 52, and then in the second error correcting code circuitry input i-th logical page (LPAGE) total data after, namely can obtain the sub-Error Correction of Coding of the i-th logical page (LPAGE) 1 to j, be also the i-th Error Correction of Coding.
Due in such scheme, only need the Error Correction of Coding of each logical page (LPAGE) of a store M logical page (LPAGE) in the second error correcting code circuitry, and Error Correction of Coding is for the data of logical page (LPAGE), its data volume is less, so reach the technique effect of the storage burden of reduction by second error correcting code circuitry.
In specific implementation process, in step S104, N part i-th logical page data is stored in N number of Physical Page successively, and i-th Error Correction of Coding is stored in the N number of Physical Page in N number of Physical Page, specifically comprise the following steps:
After jth part i-th logical page data in N part i-th logical page data is processed, export jth part i-th logical page data and be stored in a jth Physical Page;
After acquisition i-th Error Correction of Coding, export the i-th Error Correction of Coding and after the i-th Error Correction of Coding being stored in N part i-th logical page data in N part i-th logical page data.
In specific implementation process, based on the difference of the error correcting code circuitry processed jth part i-th logical page data, and then the opportunity exporting jth part i-th logical page data is also different, two kinds of enumerating below are wherein introduced, certainly, in specific implementation process, be not limited to following two kinds of situations.
The first, error correcting code circuitry is at least one error correcting code circuitry, namely at least one error correcting code circuitry, there is jth part i-th logical page data, in this case, after by jth part i-th logical page data, just can export jth part i-th logical page data, and be stored in a jth Physical Page, also after Error Correction of Coding is carried out to a N part jth logical page data, just can export jth part i-th logical page data, this embodiment of the present invention be not restricted.
The second, error correcting code circuitry is the second error correcting code circuitry, owing to not storing jth part i-th logical page data in the second error correcting code circuitry, so after carrying out correction process by the second error correcting code circuitry to jth part i-th logical page data and export jth part i-th logical page data, be just stored in a jth logical page (LPAGE).
As shown in table 3, the Error Correction of Coding (being assumed to be E1, E2, E3) for P1, P2, P3 of storing in three Physical Page and its correspondence:
Table 3
As can be seen from Table 3, the storage space of every partial data in the N partial data of each logical page (LPAGE) shared by N number of Physical Page is identical, so identical in the write starting point of every partial data in each Physical Page of each logical page (LPAGE), store so just can align when storing, and then all more convenient when writing and read every partial data, also namely read/write circuit is more simple.
Second aspect, the embodiment of the present invention provides a kind of storer, please refer to Fig. 7, specifically comprises:
Storage unit 70, storage unit 70 has N number of Physical Page, and N is positive integer, and wherein, i-th Physical Page in N number of Physical Page is corresponding with i-th code error rate in N number of incomplete same code error rate, and wherein, i is arbitrary integer between 1 to N;
Control circuit 71, is connected to storage unit 70, and for obtaining M logical page (LPAGE), wherein, i-th logical page (LPAGE) in M logical page (LPAGE) is divided into N part i-th logical page data, and i is the integer of 1 to M; And N part i-th logical page data is processed, exports i-th Error Correction of Coding corresponding with i-th logical page (LPAGE) and N part i-th logical page data; And N part i-th logical page data is stored in N number of Physical Page successively, and i-th Error Correction of Coding is stored in the N number of Physical Page in N number of Physical Page.
Wherein control circuit 71 comprises again: logical page data interface 71a, error correcting code circuitry 71b and Physical Page data-interface 71c; Wherein logical page data interface 71a is such as main frame, by the data write storage unit 70 of logical page (LPAGE), or can read data from storage unit 70 by logical page data interface 71a; Error correcting code circuitry 71b is such as: ECC coding circuit, can realize carrying out Error Correction of Coding to logical page data by this error correcting code circuitry 71b, then by Physical Page data-interface 71c write storage unit 70; And in control circuit 71, also comprise decoding circuit, such as: ECC decoding circuit, after by the data in Physical Page data-interface 71c reading cells 70, decoding process can be carried out by decoding circuit to it, then be exported by logical page data interface 71a.
Further, i-th logical page (LPAGE) is on average divided into N part i-th logical page data.
Further, control circuit 71, is specially: at least one error correcting code circuitry;
At least one error correcting code circuitry, specifically for: getting j is successively 1 to N, obtains jth part i-th logical page data in N part i-th logical page data; And
Store jth part i-th logical page data; And
Export jth part i-th logical page data successively; And
When storing the total data of N part i-th logical page data, by error correcting code circuitry, Error Correction of Coding process is carried out to i-th N partial data, and then obtain the i-th Error Correction of Coding.
Further, at least one error correcting code circuitry is specially: M error correcting code circuitry;
M error correcting code circuitry, specifically for:
At synchronization, the jth error correcting code circuitry in M error correcting code circuitry obtains a jth N part i-th logical page data in M logical page (LPAGE); And
By M error correcting code circuitry is parallel, N part i-th logical page data is processed, and then export i-th Error Correction of Coding corresponding with i-th logical page (LPAGE) respectively.
Further, at least one error correcting code circuitry is specially: the first error correcting code circuitry;
First error correcting code circuitry, is specially: get the integer that j is 1 to N successively, obtains the jth partial data of each logical page (LPAGE) of M logical page (LPAGE); And
Serial processing is carried out to N part i-th logical page data, and then exports i-th Error Correction of Coding and N part i-th logical page data successively.
Further, control circuit 71, is specially: the second error correcting code circuitry;
Second error correcting code circuitry, specifically for: get the integer that j is 1 to N successively, Error Correction of Coding is carried out to jth part i-th logical page data in N part i-th logical page data, and then obtain the sub-Error Correction of Coding of the i-th logical page (LPAGE) jth; And
The sub-Error Correction of Coding of buffer memory i-th logical page (LPAGE) jth also exports jth part i-th logical page data; And
When j is N, obtains the sub-Error Correction of Coding of the i-th logical page (LPAGE) 1 to j as the i-th Error Correction of Coding, and export the i-th Error Correction of Coding.
Further, the second error correcting code circuitry, specifically for:
Get the integer that i is 1 to M successively, obtain jth part i-th logical page data in N part i-th logical page data; And
Error Correction of Coding process is carried out to jth part i-th logical page data, and then obtains the sub-Error Correction of Coding of the i-thth logical page (LPAGE) jth.
Due to the storer that the embodiment of the present invention is introduced, the storer that the date storage method introduced for implementing the embodiment of the present invention adopts, so based on the date storage method that the embodiment of the present invention is introduced, those skilled in the art can understand structure and the distortion of the storer that the embodiment of the present invention is introduced, so do not repeat them here.
The third aspect, the embodiment of the present invention provides a kind of electronic equipment, please refer to Fig. 8, specifically comprises:
Shell 80;
The storer 81 that any embodiment of the present invention is introduced, is arranged at shell 80 inner;
Processor 82, is connected to storer 81, processes for the data stored storer 81.
Due to the electronic equipment that the embodiment of the present invention is introduced, for being provided with the electronic equipment of the storer implementing the date storage method that the embodiment of the present invention is introduced, so based on the date storage method that the embodiment of the present invention is introduced, those skilled in the art can understand structure and the distortion of the electronic equipment that the embodiment of the present invention is introduced, so do not repeat them here.
One or more technical schemes that the application provides, at least have following technique effect or advantage:
Due in embodiments of the present invention, each logical page (LPAGE) in M logical page (LPAGE) is divided into N part, and this N part is processed respectively, thus obtain the Error Correction of Coding of each logical page (LPAGE) of this M logical page (LPAGE), finally every part of each logical page (LPAGE) in this M logical page (LPAGE) is stored in N number of Physical Page successively and the Error Correction of Coding of its correspondence is stored in last Physical Page, in other words same logical page (LPAGE) can be divided into N part and be stored in N number of Physical Page, thus when storing multiple logical page (LPAGE) in multiple Physical Page, can ensure that the length shared by Error Correction of Coding between this multiple logical page (LPAGE) is all comparatively average, so when depositing logical page (LPAGE) in Physical Page, the space parallax that each logical page (LPAGE) takies is few, and then can align store when storing, so reach the technique effect of the complexity reducing read/write circuit.
Those skilled in the art should understand, embodiments of the invention can be provided as method, system or computer program.Therefore, the present invention can adopt the form of complete hardware embodiment, completely software implementation or the embodiment in conjunction with software and hardware aspect.And the present invention can adopt in one or more form wherein including the upper computer program implemented of computer-usable storage medium (including but not limited to magnetic disk memory, CD-ROM, optical memory etc.) of computer usable program code.
The present invention describes with reference to according to the process flow diagram of the method for the embodiment of the present invention, equipment (system) and computer program and/or block scheme.Should understand can by the combination of the flow process in each flow process in computer program instructions realization flow figure and/or block scheme and/or square frame and process flow diagram and/or block scheme and/or square frame.These computer program instructions can being provided to the processor of multi-purpose computer, special purpose computer, Embedded Processor or other programmable data processing device to produce a machine, making the instruction performed by the processor of computing machine or other programmable data processing device produce device for realizing the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.
These computer program instructions also can be stored in can in the computer-readable memory that works in a specific way of vectoring computer or other programmable data processing device, the instruction making to be stored in this computer-readable memory produces the manufacture comprising command device, and this command device realizes the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.
These computer program instructions also can be loaded in computing machine or other programmable data processing device, make on computing machine or other programmable devices, to perform sequence of operations step to produce computer implemented process, thus the instruction performed on computing machine or other programmable devices is provided for the step realizing the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.
Although describe the preferred embodiments of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various change and modification to the embodiment of the present invention and not depart from the spirit and scope of the embodiment of the present invention.Like this, if these amendments of the embodiment of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (15)
1. the method for a data storage, be applied to a storer, described storer has N number of Physical Page, N is positive integer, and wherein, i-th Physical Page in described N number of Physical Page is corresponding with i-th code error rate in N number of incomplete same code error rate, wherein, i is arbitrary integer between 1 to N, it is characterized in that, described method comprises:
Determine M logical page (LPAGE), wherein M be more than or equal to 1 integer;
I-th logical page (LPAGE) in a described M logical page (LPAGE) is divided into N part i-th logical page data, and i is arbitrary integer of 1 to M;
Described N part i-th logical page data is processed, exports i-th Error Correction of Coding corresponding with described i-th logical page (LPAGE) and described N part i-th logical page data;
Described N part i-th logical page data is stored in described N number of Physical Page successively, and described i-th Error Correction of Coding is stored in the N number of Physical Page in described N number of Physical Page.
2. the method for claim 1, is characterized in that, described i-th logical page (LPAGE) in a described M logical page (LPAGE) is divided into N part i-th logical page data, is specially:
I-th logical page (LPAGE) in a described M logical page (LPAGE) is on average divided into described N part i-th logical page data.
3. the method for claim 1, is characterized in that, describedly processes described N part i-th logical page data, exports i-th Error Correction of Coding corresponding with described i-th logical page (LPAGE) and described N part i-th logical page data, specifically comprises:
Getting j is successively 1 to N, and jth part i-th logical page data in described N part i-th logical page data is inputted at least one error correcting code circuitry successively;
Described jth part i-th logical page data is stored at least one error correcting code circuitry described; And export described jth part i-th logical page data successively;
When storing the total data of described N part i-th logical page data at least one error correcting code circuitry described, by at least one error correcting code circuitry described, Error Correction of Coding process is carried out to described i-th N partial data, and then obtain described i-th Error Correction of Coding.
4. method as claimed in claim 3, it is characterized in that, when at least one error correcting code circuitry described is M error correcting code circuitry, jth part i-th logical page data in described N part i-th logical page data is inputted at least one error correcting code circuitry successively, be specially: at synchronization, the N part of the jth in a described M logical page (LPAGE) i-th logical page data inputted the jth error correcting code circuitry in a described M error correcting code circuitry;
Describedly by described error correcting code circuitry, Error Correction of Coding process is carried out to described i-th N partial data, and then obtains described i-th Error Correction of Coding, specifically comprise:
By a described M error correcting code circuitry is parallel, described N part i-th logical page data is processed, and then export i-th Error Correction of Coding corresponding with described i-th logical page (LPAGE) respectively.
5. method as claimed in claim 3, it is characterized in that, when at least one error correcting code circuitry described is the first error correcting code circuitry, described jth part i-th logical page data in described N part i-th logical page data is inputted at least one error correcting code circuitry successively, be specially: be specially: get the integer that j is 1 to N successively, the jth partial data of each logical page (LPAGE) of a described M logical page (LPAGE) is inputted described first error correcting code circuitry successively;
Describedly by described error correcting code circuitry, Error Correction of Coding process is carried out to described i-th N partial data, and then obtains described i-th Error Correction of Coding, be specially:
By described first error correcting code circuitry, serial processing is carried out to described N part i-th logical page data, and then export described i-th Error Correction of Coding and described N part i-th logical page data successively.
6. the method for claim 1, is characterized in that, describedly processes described N part i-th logical page data, exports i-th Error Correction of Coding corresponding with described i-th logical page (LPAGE) and described N part i-th logical page data, specifically comprises:
Get the integer that j is 1 to N successively, by the second error correcting code circuitry, Error Correction of Coding is carried out to jth part i-th logical page data in described N part i-th logical page data, and then obtain the sub-Error Correction of Coding of the i-th logical page (LPAGE) jth;
The sub-Error Correction of Coding of the i-th logical page (LPAGE) jth described in buffer memory in described second error correcting code circuitry also exports described jth part i-th logical page data by described second error correcting code circuitry;
When j is N, obtain the sub-Error Correction of Coding of the i-th logical page (LPAGE) 1 to j as described i-th Error Correction of Coding, and export described i-th Error Correction of Coding by described second error correcting code circuitry.
7. method as claimed in claim 6, it is characterized in that, describedly by the second error correcting code circuitry, Error Correction of Coding is carried out to jth part i-th logical page data in described N part i-th logical page data, and then obtains the sub-Error Correction of Coding of the i-th logical page (LPAGE) jth, specifically comprise:
Get the integer that i is 1 to M successively, by described second error correcting code circuitry of jth part i-th logical page data input in described N part i-th logical page data;
By described second error correcting code circuitry, Error Correction of Coding process is carried out to described jth part i-th logical page data, and then obtain the sub-Error Correction of Coding of the i-th logical page (LPAGE) jth described in the.
8. a storer, is characterized in that, comprising:
Storage unit, described storage unit has N number of Physical Page, and N is positive integer, and wherein, i-th Physical Page in described N number of Physical Page is corresponding with i-th code error rate in N number of incomplete same code error rate, and wherein, i is arbitrary integer between 1 to N;
Control circuit, is connected to described storage unit, and for obtaining M logical page (LPAGE), wherein, i-th logical page (LPAGE) in a described M logical page (LPAGE) is divided into N part i-th logical page data, and i is the integer of 1 to M; And described N part i-th logical page data is processed, exports i-th Error Correction of Coding corresponding with described i-th logical page (LPAGE) and described N part i-th logical page data; And described N part i-th logical page data is stored in described N number of Physical Page successively, and described i-th Error Correction of Coding is stored in the N number of Physical Page in described N number of Physical Page.
9. storer as claimed in claim 8, it is characterized in that, described i-th logical page (LPAGE) is on average divided into described N part i-th logical page data.
10. storer as claimed in claim 8, it is characterized in that, described control circuit, is specially: at least one error correcting code circuitry;
At least one error correcting code circuitry described, specifically for: getting j is successively 1 to N, obtains jth part i-th logical page data in described N part i-th logical page data; And
Store described jth part i-th logical page data; And
Export described jth part i-th logical page data successively; And
When storing the total data of described N part i-th logical page data, by described error correcting code circuitry, Error Correction of Coding process being carried out to described i-th N partial data, and then obtaining described i-th Error Correction of Coding.
11. storeies as claimed in claim 10, it is characterized in that, at least one error correcting code circuitry described is specially: M error correcting code circuitry;
A described M error correcting code circuitry, specifically for:
At synchronization, the jth error correcting code circuitry in a described M error correcting code circuitry obtains a jth N part i-th logical page data in a described M logical page (LPAGE); And
By a described M error correcting code circuitry is parallel, described N part i-th logical page data is processed, and then export i-th Error Correction of Coding corresponding with described i-th logical page (LPAGE) respectively.
12. storeies as claimed in claim 10, it is characterized in that, at least one error correcting code circuitry described is specially: the first error correcting code circuitry;
Described first error correcting code circuitry, is specially: get the integer that j is 1 to N successively, obtains the jth partial data of each logical page (LPAGE) of a described M logical page (LPAGE); And
Serial processing is carried out to described N part i-th logical page data, and then exports described i-th Error Correction of Coding and described N part i-th logical page data successively.
13. storeies as claimed in claim 8, it is characterized in that, described control circuit, is specially: the second error correcting code circuitry;
Described second error correcting code circuitry, specifically for: get the integer that j is 1 to N successively, Error Correction of Coding is carried out to jth part i-th logical page data in described N part i-th logical page data, and then obtain the sub-Error Correction of Coding of the i-th logical page (LPAGE) jth; And
The sub-Error Correction of Coding of i-th logical page (LPAGE) jth described in buffer memory also exports described jth part i-th logical page data; And
When j is N, obtains the sub-Error Correction of Coding of the i-th logical page (LPAGE) 1 to j as described i-th Error Correction of Coding, and export described i-th Error Correction of Coding.
14. storeies as claimed in claim 13, is characterized in that, described second error correcting code circuitry, specifically for:
Get the integer that i is 1 to M successively, obtain jth part i-th logical page data in described N part i-th logical page data; And
Error Correction of Coding process is carried out to described jth part i-th logical page data, and then obtains the sub-Error Correction of Coding of the i-th logical page (LPAGE) jth described in the.
15. 1 kinds of electronic equipments, is characterized in that, comprising:
Shell;
Storer as described in claim as arbitrary in claim 8-14, is arranged at described enclosure;
Processor, is connected to described storer, processes for the data stored described storer.
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