CN104754256B - CMOS circuit of focal plane readout and signal read control method - Google Patents
CMOS circuit of focal plane readout and signal read control method Download PDFInfo
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- CN104754256B CN104754256B CN201510174770.2A CN201510174770A CN104754256B CN 104754256 B CN104754256 B CN 104754256B CN 201510174770 A CN201510174770 A CN 201510174770A CN 104754256 B CN104754256 B CN 104754256B
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Abstract
A kind of CMOS circuit of focal plane readout, its innovation is：Mark Celln, the m expression of position of a certain pixel in two-dimensional focal plane array, wherein, n represents pixel line number residing in two-dimensional focal plane array, and m represents pixel columns residing in two-dimensional focal plane array；Celln is then labeled as, the output end of m pixel by four connecting wires and is labeled as Celln 1, m, Celln+1 respectively, m, Celln, the output end electrical connection of m 1 and Celln, m+1 four pixels；Connecting valve is provided with the connecting wire.The method have the benefit that：It can realize that pixel exports photogenerated current and flowed into the selectivity of sampling unit by switching, improve the sensitivity of focal plane imaging system, extend its dynamic range.
Description
Technical field
The present invention relates to a kind of CMOS focal planes sensing technique, more particularly to a kind of CMOS circuit of focal plane readout and signal
Read control method.
Background technology
Focal plane imaging system includes focal plane imaging device (i.e. focal plane arrays (FPA)) and circuit of focal plane readout two parts
Constitute.Its general principle is：The photogenerated current that pixel is produced on focal plane arrays (FPA) is conducted to the sampling of reading circuit by indium post
Unit, the sampled unit of photogenerated current signal is sampled, after Integral Processing, is converted into corresponding voltage signal, then pass through
Thereafter row level process circuit buffering reads and is ultimately imaged；Sampling unit common in the art such as capacitive feedback is put across resistance
Big device (CTIA) sampling unit, to be directly injected into type (DI) sampling unit, source follower type (SFD) sampling unit, feedback enhancing direct
The types such as injection type (FEDI) sampling unit, electric current grid of mirrors modulation type (CM) sampling unit.
The problem of prior art is present be：In existing focal plane imaging system, multiple pixels in focal plane arrays (FPA) with
Sampling unit is handled using the output signal of the pixel of one-to-one connected mode, i.e., one by a sampling unit；Some
Occasion, it is possible that pixel output photogenerated signals more faint situation, at this moment, faint photogenerated signals may be submerged in
Among device noise so that sampling unit is difficult to carry out sampling output to it.
The content of the invention
The problem of in background technology, the present invention proposes a kind of CMOS circuit of focal plane readout, including by multiple pictures
The two-dimensional focal plane array of member composition and the CMOS circuit of focal plane readout being made up of multiple sampling units；The sampling unit with
Pixel is corresponded, and is electrically connected between sampling unit input and pixel output end by sampling channel；The sampling channel
On be provided with input switch；Its innovation is：Position of a certain pixel in two-dimensional focal plane array mark Celln, m tables
Reach, wherein, n represents pixel line number residing in two-dimensional focal plane array, and m represents the pixel in two-dimensional focal plane array
Residing columns；Celln is then labeled as, the output end of m pixel by four connecting wires and is labeled as Celln-1 respectively,
The output end electrical connection of m, Celln+1, m, Celln, m-1 and Celln, m+1 four pixels；Set in the connecting wire
There is connecting valve.
The signal processing mode (specific signal processing mode is depending on sampling unit type) and sensing principle of the present invention
Identical with existing CMOS focal planes technology, innovative point of the invention is in two-dimensional focal plane array by connecting wire
The output ends of all pixels all connect, after so doing, we just can be by controlling connecting valve and input switch
Closure/disconnection come realize pixel export selectivity from photogenerated current to sampling unit flow into, such as it is more micro- in photogenerated current
When weak, the photogenerated current that we can just control adjacent multiple pixels to export is injected into same sampling unit, so as to increase
Strong signal intensity, it is to avoid signal is flooded by noise, improves the sensitivity of focal plane imaging system, extends its dynamic range.
Based on aforementioned hardware scheme, the invention also provides a kind of CMOS circuit of focal plane readout signal reads controlling party
Method, involved hardware is as previously described；Specifically control method is：Adjacent multiple pixels are designated as a probe unit, two
The multiple pixels tieed up on focal plane arrays (FPA) are to form several probe units, and each pixel only corresponds to a probe unit, adheres to separately
The connecting valve in connecting wire between two pixels of different probe units is in normally open；Then pixel is single to sampling
During member output photoproduction current signal, the corresponding multiple connecting valves of all pixels in single probe unit are all closed, meanwhile,
Only have an input switch closure, remaining input switch in the corresponding multiple input switches of all pixels in single probe unit
Disconnect.
As it was previously stated, after using control method of the invention, we can set the division side of probe unit as needed
Formula (is such as divided) by square or rectangular, while can also control which the photogenerated current of multiple pixels is specifically injected into
In sampling unit, plurality of optional scheme is provided for later stage signal transacting, allows the self-defined signal playback mode of user.
Preferably, the pixel quantity included in each probe unit is identical.
Preferably, the pixel quantity included in each probe unit is 2 or more than 2.
The method have the benefit that：It can realize that pixel exports choosing of the photogenerated current to sampling unit by switching
Selecting property is flowed into, and is improved the sensitivity of focal plane imaging system, is extended its dynamic range.
Brief description of the drawings
Fig. 1, the principle schematic of the present invention (illustrate only a pixel and four pixels around it and corresponding adopt in figure
Electrical relation between sample unit)；
Electrical relation schematic diagram on Fig. 2, two-dimensional focal plane array between multiple pixels；
In Fig. 3, two-dimensional focal plane array, the square that is enclosed with four adjacent picture dots divides electricity during probe unit
Gas relation schematic diagram；
In Fig. 4, two-dimensional focal plane array, electrical relation signal during probe unit is divided with two adjacent picture dots
Figure；
The corresponding title of the mark of each in figure is respectively：Sampling unit 1, pixel 2, input switch 3, connecting valve 4.
Embodiment
A kind of CMOS circuit of focal plane readout, including the two-dimensional focal plane array that is made up of multiple pixels and by multiple samplings
The CMOS circuit of focal plane readout of unit composition；The sampling unit is corresponded with pixel, sampling unit input and pixel
It is electrically connected between output end by sampling channel；Input switch is provided with the sampling channel；Its innovation is：
Mark Celln, the m expression of position of a certain pixel in two-dimensional focal plane array, wherein, n represents that the pixel exists
Residing line number in two-dimensional focal plane array, m represents pixel columns residing in two-dimensional focal plane array；Then it is labeled as
The output end of Celln, m pixel is respectively by four connecting wires with being labeled as Celln-1, m, Celln+1, m, Celln, m-
1 and Celln, m+1 four pixels output end electrical connection；Connecting valve is provided with the connecting wire.
The connecting wire and connecting valve use the CMOS technology system compatible with focal plane imaging system manufacture craft
Make；
A kind of CMOS circuit of focal plane readout signal reads control method, and involved hardware includes：By multiple pixel groups
Into two-dimensional focal plane array and the CMOS circuit of focal plane readout that is made up of multiple sampling units；The sampling unit and pixel
Correspond, be electrically connected between sampling unit input and pixel output end by sampling channel；Set on the sampling channel
It is equipped with input switch；Mark Celln, the m expression of position of a certain pixel in two-dimensional focal plane array, wherein, n represents the picture
Member line number residing in two-dimensional focal plane array, m represents pixel columns residing in two-dimensional focal plane array；Then mark
For Celln, the output end of m pixel by four connecting wires and is labeled as Celln-1, m, Celln+1 respectively, m, Celln,
The output end electrical connection of m-1 and Celln, m+1 four pixels；Connecting valve is provided with the connecting wire；It is innovated
It is：
Multiple pixels that adjacent multiple pixels are designated as in a probe unit, two-dimensional focal plane array are to form some
Individual probe unit, each pixel only corresponds to a probe unit, the connection belonged between two pixels of different probe units
Connecting valve on wire is in normally open；When then pixel is to sampling unit output photoproduction current signal, single probe unit
The corresponding multiple connecting valves of interior all pixels are all closed, meanwhile, all pixels in single probe unit are corresponding more
Only has an input switch closure in individual input switch, remaining input switch disconnects.
Further, the pixel quantity included in each probe unit is identical.
Further, the pixel quantity included in each probe unit is 2 or more than 2.
Referring to Fig. 3, by taking the probe unit of 2 × 2 forms as an example, by the present invention program by the first row first row pixel Cell1,
1st, the first row secondary series pixel Cell1,2, the second row first row pixel Cell2,1 and the second row secondary series pixel Cell2,2 tetra-
The connecting valve between remaining pixel beyond connecting valve closure between individual pixel, this four pixels and the probe unit breaks
Open, now, only close Cell1,1 corresponding input switch disconnects other three input switches, then four corresponding to four pixels
Four photogenerated current signals produced by a photogenerated current path, therefore four pixels are only left in individual sampling unit will be all
Correspondence Cell1 is flowed into, in 1 sampling unit, if Cell1,1, Cell1,2, Cell2,1, Cell2,2 corresponding photogenerated currents are big
Small is Idet1、Idet2、Idet3、Idet4, then means are read compared to existing signal, after being handled through the present invention program, Cell1,
1 equivalent photogenerated current size is Idet1+Idet2+Idet3+Idet4, when photogenerated signals are less, Idet1、Idet2、Idet3、
Idet4It can may be submerged among noise so that sampling unit is difficult that sampling output is carried out to it, but after the use present invention,
Equivalent photogenerated current is changed into four electric current sums, and the scope that sampling unit can sample expands, and the sensitivity of reading circuit is with moving
State scope is improved；The like, other probe units in focal plane arrays (FPA) are attached switch in the way of 2 × 2
With the closure and opening operation of input switch, coordinate the circuits such as row choosing, the column selection of reading circuit, complete the reading of whole array,
Compared with prior art, the readout time of whole array will be reduced, and frame frequency is significantly improved.
Claims (4)
1. a kind of CMOS circuit of focal plane readout, including the two-dimensional focal plane array that is made up of multiple pixels and single by multiple samplings
The CMOS circuit of focal plane readout of member composition；The sampling unit is corresponded with pixel, and sampling unit input and pixel are defeated
Go out between holding and be electrically connected by sampling channel；Input switch is provided with the sampling channel；It is characterized in that：
Mark Celln, the m expression of position of a certain pixel in two-dimensional focal plane array, wherein, n represents the pixel in two dimension
Residing line number in focal plane arrays (FPA), m represents pixel columns residing in two-dimensional focal plane array；Celln is then labeled as,
The output end of m pixel respectively by four connecting wires with labeled as Celln-1, m, Celln+1, m, Celln, m-1 and
The output end electrical connection of Celln, m+1 four pixels；Connecting valve is provided with the connecting wire；
Multiple pixels that adjacent multiple pixels are designated as in a probe unit, two-dimensional focal plane array are to form several spies
Unit is surveyed, each pixel only corresponds to a probe unit, the connecting wire belonged between two pixels of different probe units
On connecting valve be in normally open.
2. a kind of CMOS circuit of focal plane readout signal reads control method, involved hardware includes：It is made up of multiple pixels
Two-dimensional focal plane array and the CMOS circuit of focal plane readout that is made up of multiple sampling units；The sampling unit and pixel one
One correspondence, is electrically connected between sampling unit input and pixel output end by sampling channel；Set on the sampling channel
There is input switch；Mark Celln, the m expression of position of a certain pixel in two-dimensional focal plane array, wherein, n represents the pixel
The residing line number in two-dimensional focal plane array, m represents pixel columns residing in two-dimensional focal plane array；Then it is labeled as
The output end of Celln, m pixel is respectively by four connecting wires with being labeled as Celln-1, m, Celln+1, m, Celln, m-
1 and Celln, m+1 four pixels output end electrical connection；Connecting valve is provided with the connecting wire；Its feature exists
In：
Multiple pixels that adjacent multiple pixels are designated as in a probe unit, two-dimensional focal plane array are to form several spies
Unit is surveyed, each pixel only corresponds to a probe unit, the connecting wire belonged between two pixels of different probe units
On connecting valve be in normally open；When then pixel is to sampling unit output photoproduction current signal, in single probe unit
The corresponding multiple connecting valves of all pixels are all closed, meanwhile, all pixels in single probe unit are corresponding multiple defeated
Enter only one input switch closure in switch, remaining input switch disconnects.
3. CMOS circuit of focal plane readout signal according to claim 2 reads control method, it is characterised in that：It is each to visit
Survey the pixel quantity included in unit identical.
4. CMOS circuit of focal plane readout signal according to claim 2 reads control method, it is characterised in that：It is each to visit
It is 2 or more than 2 to survey the pixel quantity included in unit.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103439645A (en) * | 2013-09-05 | 2013-12-11 | 中国电子科技集团公司第四十四研究所 | CTIA-type CMOS focal plane reading circuit and testing method |
| CN104270586A (en) * | 2014-10-14 | 2015-01-07 | 中国电子科技集团公司第四十四研究所 | Focal plane reading circuit in optional line-by-line or interlacing reading mode |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7477306B2 (en) * | 2004-08-27 | 2009-01-13 | Micron Technology, Inc. | Method and apparatus for improving pixel output swing in imager sensors |
| US20090021623A1 (en) * | 2007-07-18 | 2009-01-22 | Micron Technology, Inc. | Systems, methods and devices for a CMOS imager having a pixel output clamp |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103439645A (en) * | 2013-09-05 | 2013-12-11 | 中国电子科技集团公司第四十四研究所 | CTIA-type CMOS focal plane reading circuit and testing method |
| CN104270586A (en) * | 2014-10-14 | 2015-01-07 | 中国电子科技集团公司第四十四研究所 | Focal plane reading circuit in optional line-by-line or interlacing reading mode |
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