CN104753684A - Digital signature and signature verification method - Google Patents
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Abstract
The invention discloses a digital signature and signature verification method, and belongs to the field of information safety. The digital signature and signature verification method includes enabling a CPU (central processing unit) to carry out modular operation on Hash results and data in first preset memories and storing results in third registers; carrying out operation on data in first random number memories, fourth registers, fifth registers and the first preset memories and storing results in seventh registers; processing data in read signature private keys, the seventh registers, the third registers and the first random number memories and storing results in eighth registers; outputting data in the seventh registers and the eighth registers as signature results. According to the technical scheme, the digital signature and signature verification method has the advantages that identities can be authenticated, the data integrity and non-repudiation can be guaranteed, modular operation parameters and elliptic curve parameters are initiated, and accordingly the operation efficiency can be improved; public keys are verified in signature verification procedures, and accordingly the safety of the signature can be effectively improved.
Description
Technical field
The present invention relates to information security field, particularly relate to a kind of method realizing digital signature and sign test.
Background technology
Digital signature is some data be attached in data cell or the password change done data cell; this data or change only allow the recipient of data cell in order to the integrality in the source and data cell that confirm data cell, and protected data prevents from being forged by other people.Digital signature realizes based on public-key cryptosystem and Private key encryption system.
Summary of the invention
The invention provides a kind of method realizing digital signature and sign test, the technical scheme of employing is: a kind of method realizing digital signature, comprising:
Step S1:CPU reads Hash result, and reads the data in the first preset memory, the data in described Hash result and described first preset memory is carried out modular arithmetic, result is saved in the second register;
Step S2:CPU reads the data in the first random number memories, the second preset memory and the 3rd preset memory, data in data in described first random asccess memory and described second preset memory and described 3rd preset memory are carried out point multiplication operation, operation result is saved in the 3rd register;
Data in described 3rd register and the data in described first preset memory are carried out modular arithmetic by step S3:CPU, result are saved in the 4th register;
Step S4:CPU reads signature private key, carries out default computing, result be saved in the 5th register to the data in the data in described signature private key, described second register, described 4th register and the data in described first random asccess memory;
Data in data in described 4th register and described 5th register export as signature result by step S5:CPU.
Also comprise before described step S1: CPU receives the outside data to be signed imported into, carries out default Hash operation to described data to be signed, and Hash result computing obtained is preserved.
Also comprise before described step S1: modular arithmetic optimum configurations is the first preset value by CPU, and be saved in described first preset memory, be the second preset value and the 3rd preset value by elliptic curve optimum configurations, second preset value is saved in described second preset memory, the 3rd preset value is saved in described 3rd preset memory.
Also comprise between described step S1 and described step S2: CPU judges whether the data in described second register are the 4th preset value, if, then the data in described second register are set to the 5th preset value, perform step S2, otherwise directly perform step S2.
Also comprise before described step S2:
Step a:CPU generates random number, judges whether described random number is greater than the 4th preset value and is less than the first preset value, if so, then described random number is saved in described first random number memories, performs step S2, otherwise continues to perform step a.
Between described step S3 and described step S4, also comprise: judge whether the data in described 4th register are the 4th preset value, if so, then perform step S4, otherwise return step a.
In described step S4, described default computing is carried out to the data in the data in described signature private key, described second register, described 4th register and the data in described first random asccess memory, result is saved in the 5th register, is specially:
Data in described 4th register and described signature private key are done multiplication by step a1:CPU, result is saved in the first median memory, data in data in described first random asccess memory and described second register are done multiplication, result is saved in the second median memory;
Data in described first median memory are added with the data in described second median memory by step a2:CPU, result are saved in the 3rd median memory;
Data in described 3rd median memory and the data in described first preset memory are done modular arithmetic by step a3:CPU, result are saved in described 5th register.
Between described step S4 and described step S5, also comprise: CPU judges whether the data in described 5th register are the 4th preset value, if so, then return and perform step a, otherwise perform step S5.
Described step S5, is specially: the data in the data in described 4th register and described 5th register combine by CPU, and export.
Described data in data in described 4th register and described 5th register to be combined, obtain result of signing, be specially: the data in the data in described 4th register and described 5th register are spliced, obtain signature result.
Realize a method for digital sign test, comprising:
Step T1:CPU reads signature result, described signature result is processed, obtain two results is saved to respectively in the 8th register and the 9th register, read data to be signed, Hash calculation is carried out to described data to be signed, result is saved in the tenth register;
Step T2:CPU reads the data in the first preset memory, the data in described tenth register and the data in the first preset memory is carried out modular arithmetic, result is saved in the 11 register;
Step T3:CPU calculates the inverse element of the data in described 11 register and the data delivery in described first preset memory, result is saved in the 12 register;
Step T4:CPU processes the data in described 9th register, the data in described 12 register and the data in described first preset memory, result is saved in the 13 register, data in described 8th register, the data in described 12 register and the data in described first preset memory are processed, result is saved in the 14 register;
Step T5:CPU reads public signature key, carries out default computing, result be saved in the 15 register to the data in described 13 register, the data in described 14 register and described public signature key;
Data in described 15 register and the data in described first preset memory are carried out modular arithmetic by step T6:CPU, result are saved in the 16 register;
Step T7:CPU judges that whether the data in described 16 register are equal with the data in described 8th register, if so, then exports sign test successful information, otherwise exports sign test failure information.
Also comprise before described step T2: modular arithmetic optimum configurations is the first preset value by CPU, and be saved in described first preset memory; Elliptic curve optimum configurations is the second preset value and the 3rd preset value by CPU, is saved to by described second preset value in described second preset memory, is saved in described 3rd preset memory by described 3rd preset value.
Between described step T1 and described step T2, also comprise: CPU judges whether the data in described 8th register and the data in described 9th register are all greater than the 4th preset value and are less than the first preset value, if so, then perform step T2, otherwise report an error, terminate.
Between described step T2 and described step T3, also comprise: CPU judges whether the data in described 11 register are the 4th preset value, if so, then the data in described 11 register are set to the 5th preset value, perform step T3, otherwise directly perform step T3.
In described step T4, described data in described 9th register, the data in described 12 register and the data in described first preset memory to be processed, result is saved in the 13 register, be specially: CPU calculates the product of the data in described 9th register and the data in described 12 register, data in result of product and described first preset memory are carried out modular arithmetic, modular arithmetic result is saved in described 13 register.
In described step T4, described data in described 8th register, the data in described 12 register and the data in described first preset memory to be processed, result is saved in the 14 register, be specially: CPU calculates the product of the data in described 8th register and the data in described 12 register, data in result of product and described first preset memory are carried out modular arithmetic, modular arithmetic result is saved in described 14 register.
Described step T5, specifically comprises:
Step b1:CPU reads the data in the second preset memory and the 3rd preset memory, and reads public signature key;
Data in data in described 13 register and the data in described second preset memory and described 3rd preset memory are carried out point multiplication operation by step b2:CPU, and two results computing obtained are saved in the 4th median memory and the 5th median memory respectively;
Data in described 14 register and described public signature key are done multiplication by step b3:CPU, and two results computing obtained are saved in the 6th median memory and the 7th median memory respectively;
Step b4:CPU calculates the data in described 4th median memory, described 5th median memory, described 6th median memory and described 7th median memory, result of calculation is saved in described 15 register.
The beneficial effect that the present invention obtains is: adopt technical scheme of the present invention, authentication can be realized, ensure integrality and the non repudiation of data, and initialization is carried out to modular arithmetic parameter and elliptic curve parameter, improve operation efficiency, to the checking of PKI in the process of sign test, more improve the fail safe of signature.
Accompanying drawing explanation
In order to the clearer explanation embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of method flow diagram realizing digital signature that the embodiment of the present invention 1 provides;
Fig. 2 is a kind of method flow diagram realizing digital signature that the embodiment of the present invention 2 provides;
Fig. 3 is a kind of method flow diagram realizing digital sign test that the embodiment of the present invention 3 provides
Fig. 4 is a kind of method flow diagram realizing digital sign test that the embodiment of the present invention 4 provides.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment 1
The embodiment of the present invention 1 provides a kind of method realizing digital signature, as shown in Figure 1, comprising:
Step S1:CPU reads Hash result, and reads the data in the first preset memory, and the data in Hash result and the first preset memory are carried out modular arithmetic, result is saved in the second register;
Step S2:CPU reads the data in the first random number memories, the second preset memory and the 3rd preset memory, data in data in first random asccess memory and the second preset memory and the 3rd preset memory are carried out point multiplication operation, operation result is saved in the 3rd register;
Data in 3rd register and the data in the first preset memory are carried out modular arithmetic by step S3:CPU, result are saved in the 4th register;
Step S4:CPU reads signature private key, carries out default computing to the data in signature private key, the 4th register, the data in the second register and the data in the first random asccess memory, result is saved in the 5th register;
Data in data in 4th register and the 5th register export as signature result by step S5:CPU.
Embodiment 2
The embodiment of the present invention 2 provides a kind of method realizing digital signature, as shown in Figure 2, comprising:
Step 101:CPU reads the Hash result in the first register;
In the present embodiment, CPU carries out default Hash operation to the data to be signed that outside is imported into, obtains Hash result, is saved in the first register;
Such as, data to be signed are 0x499602D2;
The first hash in the first register obtained after default Hash operation is:
0x1785EC310767F81A8D9FD076D39074261C13EA788B9311DEE3CAFF2ECF00670D；
Step 102:CPU initialization modular arithmetic parameter, be the first preset value by modular arithmetic optimum configurations, and be saved in the first preset memory, be the second preset value and the 3rd preset value by elliptic curve optimum configurations, second preset value is saved in the second preset memory, the 3rd preset value is saved in the 3rd preset memory;
In the present embodiment, preferably, the first preset value is:
0x8000000000000000000000000000000150FE8A1892976154C59CFC193ACCF5B3；
Step 103:CPU reads the data in the first preset memory, and the first preset value in the Hash result in the first register and the first preset memory is carried out modular arithmetic, modular arithmetic result is saved in the second register;
Such as, hash 0x1785EC310767F81A8D9FD076D39074261C13EA788B9311DEE3CAFF 2ECF00670D in first register and the first preset value 0x8000000000000000000000000000000150FE8A1892976154C59CFC 193ACCF5B3 is carried out modular arithmetic by CPU, and the result obtained is:
These data are stored in the second register by 0x2DFBC1B372D89A1188C09C52E0EEC61FCE52032AB1022E8E67ECE6 672B043EE5;
Step 104:CPU judges whether the data in the second register are the 4th preset value, if so, then the data in the second register are set to the 5th preset value, performs step 105, otherwise directly performs step 105;
Preferably, the 4th preset value is the 0, five preset value is 1;
Step 105:CPU generates random number and is saved in the first random asccess memory, judges whether the random number in the first random asccess memory is greater than the 4th preset value and is less than the first preset value, if so, then performs step 106, otherwise continues to perform step 105;
Such as, the random number that CPU generates, the data namely in the first random asccess memory are:
0x77105C9B20BCD3122823C8CF6FCC7B956DE33814E95B7FE64FED92 4594DCEAB3; Meet and be greater than the 4th preset value and be less than the first preset value, perform step 106;
Step 106:CPU reads the data in the first random number memories, the second preset memory and the 3rd preset memory, data in data in first random asccess memory and the second preset memory and the 3rd preset memory are carried out point multiplication operation, operation result is saved in the 3rd register;
Preferably, the data in the second preset memory are: 0x2
Data in 3rd preset memory are:
0x8E2A8A0E65147D4BD6316030E16D19C85C97F0A9CA267122B96ABBCEA7E8FC8；
Data in first random asccess memory are:
0x77105C9B20BCD3122823C8CF6FCC7B956DE33814E95B7FE64FED924594DCEAB3；
Data in data in first random asccess memory and the second preset memory and the 3rd preset memory are carried out point multiplication operation by CPU, and the operation result obtained is:
These data are saved in the 3rd register by 0x41AA28D2F1AB148280CD9ED56FEDA41974053554A42767B83AD043 FD39DC0493.
Data in 3rd register and the data in the first preset memory are carried out modular arithmetic by step 107:CPU, result are saved in the 4th register;
Such as, the data in the 3rd register are:
0x41AA28D2F1AB148280CD9ED56FEDA41974053554A42767B83AD043FD39DC0493；
Data in 3rd register and the data in the first preset memory are carried out modular arithmetic by CPU, and the data calculated are:
These data are saved in the 4th register by 0x41AA28D2F1AB148280CD9ED56FEDA41974053554A42767B83AD043 FD39DC0493;
Step 108:CPU judges whether the data in the 4th register are the 4th preset value, if so, then returns and performs step 105, otherwise perform step 109;
Preferably, the 4th preset value is 0;
Step 109:CPU reads signature private key, data in 4th register and signature private key are done multiplication, result is saved in the first median memory, the data in the data in the first random asccess memory and the second register are done multiplication, result is saved to the second median memory;
Such as, the signature private key read is:
0x7A929ADE789BB9BE10ED359DD39A72C11B60961F49397EEE1D19CE9891EC3B28；
The data that data in 4th register and signature private key are done in the first median memory that multiplication calculates by CPU are:
0x1F70B2393C875C74B1A479D9F7971E8DA54B116F1A1D872B5E15035BC1DE2B9EF18B59F89A2CE73B4E87980453EEB0084809CEE08C64296CCB18F29A39F297F8；
Random number 0x77105C9B20BCD3122823C8CF6FCC7B956DE33814E95B7FE64FED92 4594DCEAB3 in first random asccess memory and the data 0x2DFBC1B372D89A1188C09C52E0EEC61FCE52032AB1022E8E67ECE6 672B043EE5 in the second register is done multiplication by CPU, and the data in the second median memory calculated are:
0x1562F768DC86051699E15ED2B82E87498C7035EE2FAA123ED4B2D512D4E848270A434EC3C8B6DBC95A088D4F9ADE41B1E36C0B2EE5002CC6C3CB613066414C1F；
Data in first median memory are added with the data in the second median memory by step 110:CPU, result is saved in the 3rd median memory, data in 3rd median memory and the data in the first preset memory are done modular arithmetic, result is kept in the 5th register;
Such as, the data in the first median memory are added the data in the 3rd median memory obtained and are by CPU with the data in the second median memory:
0x34D3A9A2190D618B4B85D8ACAFC5A5D731BB475D49C7996A32C7D86E96C673C5FBCEA8BC62E3C304A8902553EECCF1BA2B75DA0F716456338EE453CAA033E417；
The data that data in 3rd median memory and the data in the first preset memory are done in the 5th register that modular arithmetic obtains by CPU are:
0x1456C64BA4642A1653C235A98A60249BCD6D3F746B631DF928014F6C5BF9C40；
Step 111:CPU judges whether the data in the 5th register are the 4th preset value, if so, then returns and performs step 105, otherwise perform step 112;
Data in data in 4th register and the 5th register export as signature result by step 112:CPU;
In the present embodiment, preferably, the data in the data in the 4th register and the 5th register are spliced, obtain result of signing;
Such as, data 0x1456C64BA4642A1653C235A98A60249BCD6D3F746B631D F928014F6C5BF9C40 in data 0x41AA28D2F1AB148280CD9ED56FEDA41974053554A42767B83AD043 FD39DC0493 in 4th register and the 5th register splices by CPU, and the signature result obtained is:
0x41AA28D2F1AB148280CD9ED56FEDA41974053554A42767B83AD043FD39DC04931456C64BA4642A1653C235A98A60249BCD6D3F746B631DF928014F6C5BF9C40。
Embodiment 3
The embodiment of the present invention 3 provides a kind of method realizing digital sign test, as shown in Figure 3, comprising:
Step T1:CPU reads signature result, processes, result is saved in the 8th register and the 9th register, read data to be signed, carry out Hash calculation, result be saved in the tenth register to data to be signed signature result;
Step T2:CPU reads the data in the first preset memory, the data in the tenth register and the data in the first preset memory is carried out modular arithmetic, result is saved in the 11 register;
Step T3:CPU calculates the inverse element of the data in the 11 register and the data delivery in the first preset memory, result is saved in the 12 register;
Step T4:CPU processes the data in the 9th register, the data in the 12 register and the data in the first preset memory, result is saved in the 13 register, data in 8th register, the data in the 12 register and the data in the first preset memory are processed, result is saved in the 14 register;
Step T5:CPU reads public signature key, carries out default computing to the data in the 13 register, the data in the 14 register and public signature key, result is saved in the 15 register;
Data in 15 register and the data in the first preset memory are carried out modular arithmetic by step T6:CPU, result are saved in the 16 register;
Step T7:CPU judges that whether the data in the 16 register are equal with the data in the 8th register, if so, then exports sign test successful information, otherwise exports sign test failure information.
Embodiment 4
The embodiment of the present invention 4 provides a kind of method realizing digital sign test, as shown in Figure 4, when receiving the signature result and data to be signed that need sign test, signature result is saved in the 6th register, be saved to by data to be signed in the 7th register, CPU performs following operation:
Step 201:CPU initialization elliptic curve parameter, be the first preset value by modular arithmetic optimum configurations, and be saved in the first preset memory, be the second preset value and the 3rd preset value by elliptic curve optimum configurations, second preset value is saved in the second preset memory, the 3rd preset value is saved in the 3rd preset memory;
In the present embodiment, the first preset value in the first preset memory is:
0x8000000000000000000000000000000150FE8A1892976154C59CFC193ACCF5B3；
The second preset value in second preset memory is:
0x41AA28D2F1AB148280CD9ED56FEDA41974053554A42767B83AD043FD39DC0493；
The 3rd preset value in 3rd preset memory is:
0x489C375A9941A3049E33B34361DD204172AD98C3E5916DE27695D22A61FAE46E；
Step 202:CPU obtains the second data and the 3rd data from the 6th register, the second data is saved in the 8th register, the 3rd data is saved in the 9th register;
Such as, the second data that CPU gets from signature result, the data be namely saved in the 8th register are:
0x41AA28D2F1AB148280CD9ED56FEDA41974053554A42767B83AD043FD39DC0493；
The 3rd data that CPU gets from signature result, the data be namely saved in the 9th register are:
0x1456C64BA4642A1653C235A98A60249BCD6D3F746B631DF928014F6C5BF9C40；
Step 203:CPU judges whether the data in the 8th register and the data in the 9th register are all greater than the 4th preset value and are less than the first preset value, if so, then performs step 204, otherwise reports an error, terminate;
Preferably, the 4th preset value is 0;
Step 204:CPU reads the data to be signed in the 7th register, carries out Hash calculation, obtains Hash result, Hash result be saved in the tenth register to the data to be signed in the 7th register;
In the present embodiment, CPU carries out default Hash operation to the data to be signed received, and obtains Hash result;
Such as, the data to be signed that CPU receives are 0x499602D2, and the Hash result obtained after carrying out Hash calculation to these data to be signed is:
0x2DFBC1B372D89A1188C09C52E0EEC61FCE52032AB1022E8E67ECE6672B043EE5；
Step 205:CPU reads the data in the first preset memory, the Hash result in the tenth register and the first preset value in the first preset memory is carried out modular arithmetic, result is saved to the 11 register;
Such as, Hash result and the first preset value are carried out modular arithmetic by CPU, and the data in the 11 register calculated are:
0x2DFBC1B372D89A1188C09C52E0EEC61FCE52032AB1022E8E67ECE6672B043EE5；
Step 206:CPU judges whether the data in the 11 register are the 4th preset value, if so, then the data in the 11 register are set to the 5th preset value, performs step 207, otherwise directly performs step 207;
Preferably, the 4th preset value is the 0, five preset value is 1;
Step 207:CPU calculates the inverse element of the data in the 11 register and the first preset value delivery in the first preset memory, result is saved to the 12 register;
Such as, the data in the 12 register that calculates of CPU are:
0x271A4EE429F84EBC423E388964555BB29D3BA53C7BF945E5FAC8F381706354C2；
Step 208:CPU calculates the product of the data in the 9th register and the data in the 12 register, and the first preset value in result and the first preset memory is carried out modular arithmetic, and the result obtained is saved in the 13 register;
In the present embodiment, the data in the 13 register that CPU calculates are:
0x5358F8FFB38F7C09ABC782A2DF2A3927DA4077D07205F763682F3A76C9019B4F；
Step 209:CPU calculates the product of the data in the 8th register and the data in the 12 register, the first preset value in result and the first preset memory is carried out modular arithmetic, result is saved in the 14 register;
In the present embodiment, the data in the 14 register that CPU calculates are:
0x3221B4FBBF6D101074EC14AFAC2D4F7EFAC4CF9FEC1ED11BAE336D27D527665；
In the present embodiment, step 208 and step 209, without sequencing, can perform simultaneously;
Step 210:CPU reads the data in the second preset memory and the 3rd preset memory, the 3rd preset value in data in 13 register and the second preset value in the second preset memory and the 3rd preset memory is carried out point multiplication operation, obtain two results is saved to respectively in the 4th median memory and the 5th median memory;
Such as, CPU carries out point multiplication operation, and the data in the 4th median memory obtained are:
0xCA4036F2B1EC00E1D9E4F789EE594C83F22987A2D9FD7844572ECB443F676E67；
Meanwhile, the data in the 5th median memory that obtains of CPU are:
0x55E6DD8D570DD7CE2E1C8E2DE340E2F9785E94E257E3530C074510E46CE50464；
Step 211:CPU reads public signature key, and the data in the 14 register and public signature key are done multiplication, and two results computing obtained are saved in the 6th median memory and the 7th median memory respectively;
Such as, the public signature key that CPU gets is:
(0x7F2B49E270DB6D90D8595BEC458B50C58585BA1D4E9B788F6689DBD8E56FD80B，0x26F1B489D6701DD185C8413A977B3CBBAF64D1C593D26627DFFB101A87FF77DA)；
The data that data in 14 register and public signature key are done in the 6th median memory that multiplication obtains by CPU are:
0x64A4B968FFEE6A93EC23445E47129E087F1517FA6152DD5DABC2ADBA527191DC；
Meanwhile, the data in the 7th median memory that obtains of CPU are:
0x1CA5EE5FC1BFC27EFC8B4E260F8FD17593A5E4E42821045B546A3DC2E2B8A290；
In the present embodiment, step 210 and step 211, without sequencing, can perform simultaneously;
Step 212:CPU calculates the data in the 4th median memory, the 5th median memory, the 6th median memory and the 7th median memory, result of calculation is saved in the 15 register;
Such as, the data in the 15 register that calculates of CPU are:
0x41AA28D2F1AB148280CD9ED56FEDA41974053554A42767B83AD043FD39DC0493；
Data in 15 register and the first preset value in the first preset memory are carried out modular arithmetic by step 213:CPU, result are saved in the 16 register;
Such as, the data in the 16 register that calculates of CPU are:
0x41AA28D2F1AB148280CD9ED56FEDA41974053554A42767B83AD043FD39DC0493；
Step 214:CPU judges that whether the data in the 16 register are equal with the data in the 8th register, if so, then exports sign test successful information, otherwise exports sign test failure information;
In the present embodiment, the data in the 8th register that CPU gets from the signature result received are identical with the data in the 16 register, sign test success.
The above; be only the present invention's preferably embodiment, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in technical scope disclosed by the invention; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (17)
1. realize a method for digital signature, it is characterized in that, comprising:
Step S1:CPU reads Hash result, and reads the data in the first preset memory, the data in described Hash result and described first preset memory is carried out modular arithmetic, result is saved in the second register;
Step S2:CPU reads the data in the first random number memories, the second preset memory and the 3rd preset memory, data in data in described first random asccess memory and described second preset memory and described 3rd preset memory are carried out point multiplication operation, operation result is saved in the 3rd register;
Data in described 3rd register and the data in described first preset memory are carried out modular arithmetic by step S3:CPU, result are saved in the 4th register;
Step S4:CPU reads signature private key, carries out default computing, result be saved in the 5th register to the data in the data in described signature private key, described second register, described 4th register and the data in described first random asccess memory;
Data in data in described 4th register and described 5th register export as signature result by step S5:CPU.
2. method according to claim 1, is characterized in that, also comprises before described step S1: CPU receives the outside data to be signed imported into, carries out default Hash operation to described data to be signed, and Hash result computing obtained is preserved.
3. method according to claim 1, it is characterized in that, also comprise before described step S1: modular arithmetic optimum configurations is the first preset value by CPU, and be saved in described first preset memory, be the second preset value and the 3rd preset value by elliptic curve optimum configurations, second preset value is saved in described second preset memory, the 3rd preset value is saved in described 3rd preset memory.
4. method according to claim 1, it is characterized in that, also comprise between described step S1 and described step S2: CPU judges whether the data in described second register are the 4th preset value, if, then the data in described second register are set to the 5th preset value, perform step S2, otherwise directly perform step S2.
5. method according to claim 1, is characterized in that, also comprises before described step S2:
Step a:CPU generates random number, judges whether described random number is greater than the 4th preset value and is less than the first preset value, if so, then described random number is saved in described first random number memories, performs step S2, otherwise continues to perform step a.
6. method according to claim 5, is characterized in that, between described step S3 and described step S4, also comprises: judge whether the data in described 4th register are the 4th preset value, if so, then performs step S4, otherwise returns step a.
7. method according to claim 1, it is characterized in that, in described step S4, described default computing is carried out to the data in the data in described signature private key, described second register, described 4th register and the data in described first random asccess memory, result is saved in the 5th register, is specially:
Data in described 4th register and described signature private key are done multiplication by step a1:CPU, result is saved in the first median memory, data in data in described first random asccess memory and described second register are done multiplication, result is saved in the second median memory;
Data in described first median memory are added with the data in described second median memory by step a2:CPU, result are saved in the 3rd median memory;
Data in described 3rd median memory and the data in described first preset memory are done modular arithmetic by step a3:CPU, result are saved in described 5th register.
8. method according to claim 5, is characterized in that, between described step S4 and described step S5, also comprises: CPU judges whether the data in described 5th register are the 4th preset value, if so, then returns and performs step a, otherwise perform step S5.
9. method according to claim 1, is characterized in that, described step S5, is specially: the data in the data in described 4th register and described 5th register combine by CPU, and export.
10. method according to claim 9, it is characterized in that, described data in data in described 4th register and described 5th register to be combined, obtain result of signing, be specially: the data in the data in described 4th register and described 5th register are spliced, obtain result of signing.
11. 1 kinds of methods realizing digital sign test, is characterized in that, comprising:
Step T1:CPU reads signature result, described signature result is processed, obtain two results is saved to respectively in the 8th register and the 9th register, read data to be signed, Hash calculation is carried out to described data to be signed, result is saved in the tenth register;
Step T2:CPU reads the data in the first preset memory, the data in described tenth register and the data in the first preset memory is carried out modular arithmetic, result is saved in the 11 register;
Step T3:CPU calculates the inverse element of the data in described 11 register and the data delivery in described first preset memory, result is saved in the 12 register;
Step T4:CPU processes the data in described 9th register, the data in described 12 register and the data in described first preset memory, result is saved in the 13 register, data in described 8th register, the data in described 12 register and the data in described first preset memory are processed, result is saved in the 14 register;
Step T5:CPU reads public signature key, carries out default computing, result be saved in the 15 register to the data in described 13 register, the data in described 14 register and described public signature key;
Data in described 15 register and the data in described first preset memory are carried out modular arithmetic by step T6:CPU, result are saved in the 16 register;
Step T7:CPU judges that whether the data in described 16 register are equal with the data in described 8th register, if so, then exports sign test successful information, otherwise exports sign test failure information.
12. methods according to claim 11, is characterized in that, also comprise before described step T2: modular arithmetic optimum configurations is the first preset value by CPU, and are saved in described first preset memory; Elliptic curve optimum configurations is the second preset value and the 3rd preset value by CPU, is saved to by described second preset value in described second preset memory, is saved in described 3rd preset memory by described 3rd preset value.
13. methods according to claim 11, it is characterized in that, between described step T1 and described step T2, also comprise: CPU judges whether the data in described 8th register and the data in described 9th register are all greater than the 4th preset value and are less than the first preset value, if, then perform step T2, otherwise report an error, terminate.
14. methods according to claim 11, it is characterized in that, between described step T2 and described step T3, also comprise: CPU judges whether the data in described 11 register are the 4th preset value, if, then the data in described 11 register are set to the 5th preset value, perform step T3, otherwise directly perform step T3.
15. methods according to claim 11, it is characterized in that, in described step T4, described data in described 9th register, the data in described 12 register and the data in described first preset memory to be processed, result is saved in the 13 register, be specially: CPU calculates the product of the data in described 9th register and the data in described 12 register, data in result of product and described first preset memory are carried out modular arithmetic, modular arithmetic result is saved in described 13 register.
16. methods according to claim 11, it is characterized in that, in described step T4, described data in described 8th register, the data in described 12 register and the data in described first preset memory to be processed, result is saved in the 14 register, be specially: CPU calculates the product of the data in described 8th register and the data in described 12 register, data in result of product and described first preset memory are carried out modular arithmetic, modular arithmetic result is saved in described 14 register.
17. methods according to claim 11, is characterized in that, described step T5, specifically comprises:
Step b1:CPU reads the data in the second preset memory and the 3rd preset memory, and reads public signature key;
Data in data in described 13 register and the data in described second preset memory and described 3rd preset memory are carried out point multiplication operation by step b2:CPU, and two results computing obtained are saved in the 4th median memory and the 5th median memory respectively;
Data in described 14 register and described public signature key are done multiplication by step b3:CPU, and two results computing obtained are saved in the 6th median memory and the 7th median memory respectively;
Step b4:CPU calculates the data in described 4th median memory, described 5th median memory, described 6th median memory and described 7th median memory, result of calculation is saved in described 15 register.
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| CN108259184A (en) * | 2018-01-16 | 2018-07-06 | 飞天诚信科技股份有限公司 | A kind of digital signature based on user identifier, sign test method and device |
| CN109064170A (en) * | 2018-07-23 | 2018-12-21 | 西安电子科技大学 | Group signature method without trusted party |
| CN111143893A (en) * | 2019-12-17 | 2020-05-12 | 北京宏思电子技术有限责任公司 | Secure implementation method and device for Hash grouping calculation |
| CN112100644A (en) * | 2020-11-19 | 2020-12-18 | 飞天诚信科技股份有限公司 | Method and device for generating data signature |
| CN113676335A (en) * | 2021-10-21 | 2021-11-19 | 飞天诚信科技股份有限公司 | Method and device for realizing signature in security chip |
| CN114844650A (en) * | 2022-05-24 | 2022-08-02 | 北京宏思电子技术有限责任公司 | Equipment signature method and system |
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| CN108259184A (en) * | 2018-01-16 | 2018-07-06 | 飞天诚信科技股份有限公司 | A kind of digital signature based on user identifier, sign test method and device |
| CN109064170A (en) * | 2018-07-23 | 2018-12-21 | 西安电子科技大学 | Group signature method without trusted party |
| CN109064170B (en) * | 2018-07-23 | 2021-10-22 | 西安电子科技大学 | Group signature method without trusted center |
| CN111143893A (en) * | 2019-12-17 | 2020-05-12 | 北京宏思电子技术有限责任公司 | Secure implementation method and device for Hash grouping calculation |
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| CN112100644A (en) * | 2020-11-19 | 2020-12-18 | 飞天诚信科技股份有限公司 | Method and device for generating data signature |
| CN112100644B (en) * | 2020-11-19 | 2021-03-16 | 飞天诚信科技股份有限公司 | Method and device for generating data signature |
| CN113676335A (en) * | 2021-10-21 | 2021-11-19 | 飞天诚信科技股份有限公司 | Method and device for realizing signature in security chip |
| CN113676335B (en) * | 2021-10-21 | 2021-12-28 | 飞天诚信科技股份有限公司 | Method and device for realizing signature in security chip |
| CN114844650A (en) * | 2022-05-24 | 2022-08-02 | 北京宏思电子技术有限责任公司 | Equipment signature method and system |
| CN114844650B (en) * | 2022-05-24 | 2023-12-01 | 北京宏思电子技术有限责任公司 | Equipment signature method and system |
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