CN104753605A - Optical line terminal - Google Patents
Optical line terminal Download PDFInfo
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- CN104753605A CN104753605A CN201310740635.0A CN201310740635A CN104753605A CN 104753605 A CN104753605 A CN 104753605A CN 201310740635 A CN201310740635 A CN 201310740635A CN 104753605 A CN104753605 A CN 104753605A
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Abstract
The invention discloses an optical line terminal, so as to solve the problem that a next-time sampling processing result is influenced as a result of discharging of an RC circuit in a sampling holding circuit after sampling processing at the time. The optical line terminal comprises a light receiving assembly APD, a mirror image current source connected with the output end of the APD, the sampling holding circuit connected with the output end of the mirror image current source, and a MCU (Microprogrammed Control Unit) connected with the output end of the sampling holding circuit. The optical line terminal also comprises a control circuit. The control circuit is connected with the input end of the sampling holding circuit, and/or the control circuit is connected with the output end of the sampling holding circuit. After the sampling holding circuit completes sampling, the control circuit carries out zero cleaning on sampling voltage in the sampling holding circuit, the next-time sampling processing result can be prevented from being influenced, and accuracy and precision of an RSSI (Received Signal Strength Indication) reporting value can be enhanced.
Description
Technical field
The present invention relates to technical field of photo communication, particularly a kind of optical line terminal.
Background technology
Along with the demand and high speed Internet access etc. of the Video Applications such as MMS (Multimedia Message Service), high-resolution video monitoring is from the demand of business aspect, the diversification of broadband services application and improving constantly of bandwidth demand, the requirement of Access Network to bandwidth promotes rapidly, and intelligent acess becomes best selection.Gigabit Passive Optical Network (Gigabit-capable passive optical networks, GPON) be one most effective in all Optical Access Networks, GPON is owing to can provide the key advantages such as higher speed, higher access performance and network efficiency, stronger flexibility and scalability, so the network insertion that more can meet broadband is applied.
In GPON system, generally include optical line terminal (the Optical LineTerminal that is positioned at local side, and multiple optical network unit (Optical Network Unit being positioned at user side OLT), ONU), wherein, connected by Optical Distribution Network (Optical Distribution Network, ODN) between OLT and ONU.The light signal that optical module in the olt sends for receiving ONU, and realize burst reception signal strength signal intensity instruction (Received Signal Strength Indication, RSSI) report, the structure of the optical module of existing OLT is shown in Figure 1, comprise: optical fiber receive module (APD), mirror current source, sampling resistor, sampling hold circuit and microprogram control unit (Microprogrammed Control Unit, MCU) (modulus switching device (Analog Digital Convertor, ADC) in this MCU, is comprised).OLT reports the process of RSSI value as follows:
1, under the effect of the high-voltage signal of high-tension circuit output, the light signal that ONU sends by APD converts photogenerated current I to;
2, photogenerated current I is through mirror current source, forms sample rate current;
3, sample rate current is by sampling resistor, forms sampled voltage V;
4, sampled voltage transfers to MCU process via sampling hold circuit, obtains RSSI and reports value.
In GPON system, because the distance between ONU and OLT is different, the intensity of the light signal that OLT receives is also different, and such as, if the close together between certain ONU and OLT, then OLT can receive the light signal (being referred to as large light) of a high strength; If distant between certain ONU and OLT, then OLT can receive a low intensive light signal (being referred to as little light).In GPON system, because the light inter-packet gap time is very short, generally only have 25.6 nanoseconds (ns).If after OLT receives a large light signal, and then have received again the light signal that certain remote ONU sends, when carrying out sampling processing to little light, due to phase shift (the resistor – capacitor in sampling hold circuit, RC) circuit still stores certain electric charge, can discharge, thus the RSSI that can affect little light reports value, therefore, little broadband cannot be met, requirement that little luminous power reports.
Summary of the invention
The RSSI embodiments providing a kind of optical line terminal and this optical line terminal reports the defining method of value, affects the problem of next sampling processing result after solving this sampling processing due to the electric discharge of the RC circuit in sampling hold circuit.
First aspect, provide a kind of optical line terminal, the microprogram control unit MCU comprising optical fiber receive module APD, the mirror current source be connected with the output of described APD, the sampling hold circuit be connected with the output of described mirror current source and be connected with the output of described sampling hold circuit, wherein:
Described optical line terminal also comprises control circuit, and described control circuit is connected with the input of described sampling hold circuit, and/or described control circuit is connected with the output of described sampling hold circuit;
Wherein, after described sampling hold circuit completes sampling, the sampled voltage in described sampling hold circuit resets by described control circuit.
In the embodiment of the present invention, due to the effect of control circuit, make sampling hold circuit after completing sampling processing, RC circuit in sampling hold circuit can discharge in time, namely mirror current source exports almost nil, thus the impact avoided sampling processing result next time, improve accuracy and precision that RSSI reports value, achieve less, the more accurate luminous power of optical line terminal and report.
In conjunction with first aspect, in the implementation that the first is possible, described control circuit and sampling resistor are connected in parallel, and wherein, one end of described sampling resistor is connected with the output of described mirror current source, and the other end ground connection of described sampling resistor.
In conjunction with first aspect or the first the possible implementation in conjunction with first aspect, in the implementation that the second is possible, for the first triggering signal of triggering described sampling hold circuit with for triggering the second triggering signal reverse signal each other of described control circuit.
In conjunction with first aspect or in conjunction with the first possible implementation of first aspect or in conjunction with the possible implementation of the second of second aspect, in the implementation that the third is possible, described control circuit comprises a control switch, wherein, one end of described control switch is connected with the input of described sampling hold circuit or output, the other end ground connection of described control switch.
In conjunction with first aspect or in conjunction with the first possible implementation of first aspect or in conjunction with the possible implementation of the second of second aspect or the third the possible implementation in conjunction with second aspect, in the 4th kind of possible implementation, when described sampling hold circuit is sampled, the sampled voltage that described sampling hold circuit exports to be transferred to the AD conversion unit in described MCU by described MCU by the I/O port that is connected with described sampling hold circuit; And after described sampling hold circuit completes sampling, described I/O port is set to low level by described MCU, reset to make the sampled voltage in described sampling hold circuit.
Under which, after sampling hold circuit completes sampling, this I/O port is set to low level by this MCU, and its effect is equal to the output head grounding of this sampling hold circuit, thus the sampled voltage realized in sampling hold circuit resets.
Second aspect, provide another kind of optical line terminal, the microprogram control unit MCU comprising optical fiber receive module APD, the mirror current source be connected with the output of described APD, the sampling hold circuit be connected with the output of described mirror current source and be connected with the output of described sampling hold circuit, wherein:
When described sampling hold circuit is sampled, the sampled voltage that described sampling hold circuit exports to be transferred to the AD conversion unit in described MCU by described MCU by the I/O port that is connected with described sampling hold circuit; And,
After described sampling hold circuit completes sampling, described I/O port is set to low level by described MCU, resets to make the sampled voltage in described sampling hold circuit.
In the embodiment of the present invention, after sampling hold circuit completes sampling, this I/O port is set to low level by this MCU, its effect is equal to the output head grounding of this sampling hold circuit, thus the sampled voltage realized in sampling hold circuit resets, avoid the impact on sampling processing result next time, improve accuracy and precision that RSSI reports value, achieve less, the more accurate luminous power of optical line terminal and report.
In conjunction with second aspect, in the implementation that the first is possible, described optical line terminal also comprises control circuit, and described control circuit is connected with the input of described sampling hold circuit, and/or described control circuit is connected with the output of described sampling hold circuit;
Wherein, after described sampling hold circuit completes sampling, the sampled voltage in described sampling hold circuit resets by described control circuit.
Under which, due to the effect of control circuit, make sampling hold circuit after completing sampling processing, RC circuit in sampling hold circuit can discharge in time, namely mirror current source exports almost nil, thus the impact avoided sampling processing result next time, improve accuracy and precision that RSSI reports value, achieve less, the more accurate luminous power of optical line terminal and report.
In conjunction with the first possible implementation of second aspect, in the implementation that the second is possible, described control circuit and sampling resistor are connected in parallel, wherein, one end of described sampling resistor is connected with the output of described mirror current source, and the other end ground connection of described sampling resistor.
In conjunction with the first possible implementation of second aspect or in conjunction with the possible implementation of the second of second aspect, in the implementation that the third is possible, for the first triggering signal of triggering described sampling hold circuit with for triggering the second triggering signal reverse signal each other of described control circuit.
In conjunction with the first possible implementation of second aspect or in conjunction with the possible implementation of the second of second aspect or the third the possible implementation in conjunction with second aspect, in the 4th kind of possible implementation, described control circuit comprises a control switch, wherein, one end of described control switch is connected with the input of described sampling hold circuit, the other end ground connection of described control switch.
Accompanying drawing explanation
Fig. 1 is the structural representation of optical line terminal in prior art;
The structural representation of the first optical line terminal that Fig. 2 provides for the embodiment of the present invention;
The sequential chart of the triggering signal of the optical line terminal that Fig. 3 provides for the embodiment of the present invention;
The structural representation of the second optical line terminal that Fig. 4 provides for the embodiment of the present invention;
The structural representation of the third optical line terminal that Fig. 5 provides for the embodiment of the present invention.
Embodiment
The optical line terminal of the embodiment of the present invention passes through control circuit, after sampling hold circuit completes sampling, sampling hold circuit output under the effect of control circuit is reset, thus after avoiding this sampling processing, affects the problem of next sampling processing result due to the electric discharge of the RC circuit in sampling hold circuit.
Below in conjunction with Figure of description, the embodiment of the present invention is described in further detail.Should be appreciated that embodiment described herein is only for instruction and explanation of the present invention, is not intended to limit the present invention.
Embodiments provide a kind of optical line terminal, this optical line terminal comprises: APD, the mirror current source be connected with the output of this APD, the sampling hold circuit be connected with the output of this mirror current source and the MCU be connected with the output of this sampling hold circuit, wherein:
This optical line terminal also comprises control circuit, and this control circuit is connected with the input of sampling hold circuit, and/or this control circuit is connected with the output of sampling hold circuit; Wherein:
After sampling hold circuit completes sampling, the sampled voltage in this sampling hold circuit resets by the control circuit be connected with this sampling hold circuit.
Above-mentioned optical line terminal carries out RSSI gives the correct time at needs, sampling hold circuit is under the triggering of the first triggering signal, carry out sampling processing, sampled voltage is inputed to MCU process, value is reported to obtain RSSI, wherein, the sample rate current that mirror current source exports, under sampling resistor effect, forms sampled voltage;
And when sampling hold circuit completes sampling, the sampled voltage in sampling hold circuit resets by control circuit under the triggering of the second triggering signal, and now, this image current source output terminal does not have voltage to export.
In the embodiment of the present invention, optical line terminal also comprises control circuit, this control circuit is connected with the input of sampling hold circuit, and/or, this control circuit is connected with the output of sampling hold circuit, when sampling hold circuit completes sampling, the sampled voltage in sampling hold circuit resets by control circuit under the triggering of the second triggering signal.Due to the effect of control circuit, make sampling hold circuit after completing sampling processing, RC circuit in sampling hold circuit can discharge in time, namely mirror current source exports almost nil, thus the impact avoided sampling processing result next time, improve accuracy and precision that RSSI reports value, achieve less, the more accurate luminous power of optical line terminal and report.
In the embodiment of the present invention, optical line terminal only can comprise a control circuit, and input or the output of this control circuit and sampling hold circuit are connected; This optical line terminal also can comprise two control circuits, and the input of each control circuit difference sampling hold circuit is connected with output.
In force, controlled the operating state of sampling hold circuit by the first triggering signal, specific as follows:
If the first trigger message number is high level signal, then sampling hold circuit enters operating state (now, the input of sampling hold circuit is connected with the output of mirror current source), and sampled voltage is input to MCU process, value is reported to obtain RSSI, in this process, control circuit is inoperative in the low level triggering of the second triggering signal;
If the first trigger message number is low level signal, then this sampling processing terminates (now, disconnecting between sampling hold circuit and mirror current source), now, sampled voltage in sampling hold circuit, under the high level of the second triggering signal triggers, resets by control circuit.
In force, sampling resistor one end of this optical line terminal is connected with the output of mirror current source, and other end ground connection.Preferably, control circuit and the sampling resistor of the embodiment of the present invention are connected in parallel, and namely this control circuit is connected with the output of mirror current source, and this control circuit other end ground connection.
In force, the first triggering signal and the second triggering signal reverse signal each other, be specially:
When the first triggering signal is high level signal, the second triggering signal is low level signal, now, is connection status, and is off state between control circuit and sampling hold circuit between sampling hold circuit and mirror current source;
When the first triggering signal is low level signal, the second triggering signal is high level signal, now, is off stateful connection between sampling hold circuit and mirror current source, and is connection status between control circuit and sampling hold circuit.
Based on above-mentioned any embodiment, in force, preferably, adopt control switch formation control circuit, wherein, one end of this control switch is connected with the input of sampling hold circuit or output, and the other end ground connection of this control switch.
Below for control switch formation control circuit, in conjunction with several specific embodiment, the structure and working principle of the optical line terminal that the embodiment of the present invention provides is described.
Embodiment one, shown in Figure 2, optical line terminal comprises:
APD21, the mirror current source 22 be connected with this APD21 output, the sampling hold circuit 23 be connected with the output of this mirror current source 22 and sampling resistor R, the MCU24 be connected with the output of this sampling hold circuit 23 and the control switch K be connected in parallel with sampling resistor R, wherein, the other end ground connection of sampling resistor R.
The operation principle of this optical line terminal is as follows:
In first time period, first triggering signal is low level signal and the second triggering signal is high level signal, in this time period, open circuit between sampling hold circuit and mirror current source, sampling hold circuit does not work, and control switch K is in closure state under the control of high level signal, in sampling hold circuit, there is no sampled voltage;
In second time period, first triggering signal is high level signal and the second triggering signal is low level signal, in this time period, sampling hold circuit enters RSSI and interrupts, sampled voltage inputs in MCU and processes by sampling hold circuit, report value to obtain RSSI, and control switch K is in off-state under the control of low level signal;
In 3rd time period, first triggering signal has recovered low level signal (sampling hold circuit terminates sampling processing), and the second triggering signal has recovered high level signal, in this time period, control switch K is in closure state, due to control switch K ground connection, sampling resistor R is shorted, the electric charge that RC circuit in sampling hold circuit stores can be timely released, and the sampled voltage in sampling hold circuit is reset.
In said process, the sequential chart of the output of the first triggering signal, the second triggering signal and mirror current source is shown in Figure 3, the first triggering signal and the second triggering signal reverse signal each other.
Embodiment two, shown in Figure 4, optical line terminal comprises:
APD21, the mirror current source 22 be connected with this APD21 output, the sampling hold circuit 23 be connected with the output of this mirror current source 22 and sampling resistor R, the MCU24 be connected with the output of this sampling hold circuit 23 and the control switch K be connected with the output of sampling hold circuit 23, wherein, the other end ground connection of this control switch K, the other end ground connection of sampling resistor R.
The operation principle of this optical line terminal is as follows:
In first time period, first triggering signal is low level signal and the second triggering signal is high level signal, in this time period, open circuit between sampling hold circuit and mirror current source, sampling hold circuit does not work, and control switch K is in closure state under the control of high level signal, in sampling hold circuit, there is no sampled voltage;
In second time period, first triggering signal is high level signal and the second triggering signal is low level signal, in this time period, sampling hold circuit enters RSSI and interrupts, sampled voltage inputs in MCU and processes by sampling hold circuit, report value to obtain RSSI, and control switch K is in off-state under the control of low level signal;
In 3rd time period, first triggering signal has recovered low level signal (sampling hold circuit terminates sampling processing), and the second triggering signal has recovered high level signal, in this time period, control switch K is in closure state, due to control switch K ground connection, the electric charge that the RC circuit in sampling hold circuit stores can be timely released, and the sampled voltage in sampling hold circuit is reset.
In said process, the sequential chart of the output of the first triggering signal, the second triggering signal and mirror current source is still shown in Figure 3, the first triggering signal and the second triggering signal reverse signal each other.
Embodiment three, shown in Figure 5, optical line terminal comprises:
APD21, the mirror current source 22 be connected with this APD21 output, the sampling hold circuit 23 be connected with the output of this mirror current source 22 and sampling resistor R, the MCU24 be connected with the output of this sampling hold circuit 23, the control switch K1 be connected in parallel with sampling resistor R and the control switch K2 be connected with the output of sampling hold circuit 23, wherein, the other end ground connection of this control switch K2, the other end ground connection of sampling resistor R.
The operation principle of this optical line terminal is as follows:
In first time period, first triggering signal is low level signal and the second triggering signal is high level signal, in this time period, open circuit between sampling hold circuit and mirror current source, sampling hold circuit does not work, and control switch K1 and K2 is in closure state under the control of high level signal, in sampling hold circuit, there is no sampled voltage;
In second time period, first triggering signal is high level signal and the second triggering signal is low level signal, in this time period, sampling hold circuit enters RSSI and interrupts, sampled voltage inputs in MCU and processes by sampling hold circuit, report value to obtain RSSI, and control switch K1 and K2 is in off-state under the control of low level signal;
In 3rd time period, first triggering signal has recovered low level signal (sampling hold circuit terminates sampling processing), and the second triggering signal has recovered high level signal, in this time period, control switch K1 and K2 is all in closure state, due to the equal ground connection of control switch K1 and K2, the electric charge that the RC circuit in sampling hold circuit stores can be timely released, and the sampled voltage in sampling hold circuit is reset.
In said process, the sequential chart of the output of the first triggering signal, the second triggering signal and mirror current source is still shown in Figure 3, the first triggering signal and the second triggering signal reverse signal each other.
Above embodiment realizes after sampling hold circuit completes sampling from hardware circuit, the sampled voltage of sampling hold circuit is reset, the embodiment of the present invention additionally provides and realizes after sampling hold circuit completes sampling, resetting the sampled voltage of sampling hold circuit from MCU software.
Based on above any embodiment, further, the optical line terminal of the embodiment of the present invention can also make the sampled voltage in sampling hold circuit reset in the following ways, specific as follows:
When sampling hold circuit is sampled, the sampled voltage that sampling hold circuit exports to be transferred to the AD conversion unit in this MCU by MCU by the I/O port that is connected with sampling hold circuit;
After sampling hold circuit completes sampling, this I/O port is set to low level by this MCU, resets to make the sampled voltage in sampling hold circuit.
It should be noted that, after sampling hold circuit completes sampling, this I/O port is set to low level by this MCU, and its effect is equal to the output head grounding of this sampling hold circuit, thus the sampled voltage realized in sampling hold circuit resets.
Under which, after sampling hold circuit completes sampling, the I/O port be connected with sampling hold circuit is set to low level by MCU, thus realize resetting the sampled voltage of sampling hold circuit on software, thus the impact avoided sampling processing result next time, improve accuracy and precision that RSSI reports value, achieve less, the more accurate luminous power of optical line terminal and report.
Under which, operationally, when the first triggering signal is low level signal, the I/O port be connected with sampling hold circuit in MCU, as AD passage, is namely connected with the ADC of MCU optical line terminal, waits for the arrival of the high level signal of the first triggering signal; When the first triggering signal is high level signal, MCU carries out RSSI interruption, and now, sampling hold circuit is sampled to the sampled voltage received, and carries out analog-to-digital conversion process by the ADC that sampled voltage to be inputed to MCU by I/O port; When saltus step is low level signal to the first triggering signal again, sampling hold circuit completes sampling, now, I/O port is set to output port by MCU, and is set to low level, because I/O port is low level, thus the electric charge that the RC circuit in sampling hold circuit stores is timely released, sampled voltage in sampling hold circuit is reset, and meanwhile, the sampled voltage in sampling hold circuit also can reset by control circuit under the triggering of the second triggering signal; Afterwards, MCU exits RSSI and interrupts, and this I/O port is re-set as AD passage, waits for the next high level signal of the first triggering signal.
The embodiment of the present invention additionally provides a kind of optical line terminal, the MCU comprising APD, the mirror current source be connected with the output of this APD, the sampling hold circuit be connected with the output of this mirror current source and be connected with the output of this sampling hold circuit, wherein:
When sampling hold circuit is sampled, the sampled voltage that sampling hold circuit exports to be transferred to the AD conversion unit in this MCU by MCU by the I/O port that is connected with sampling hold circuit; After sampling hold circuit completes sampling, this I/O port is set to low level by this MCU, resets to make the sampled voltage in sampling hold circuit.
In the embodiment of the present invention, after sampling hold circuit completes sampling, the I/O port be connected with sampling hold circuit is set to low level by MCU, its effect is equal to the output head grounding of this sampling hold circuit, thus by software simulating, the sampled voltage of sampling hold circuit is reset, thus the impact avoided sampling processing result next time, improve accuracy and precision that RSSI reports value, achieve less, the more accurate luminous power of optical line terminal and report.
Operationally, when the first triggering signal is low level signal, the I/O port be connected with sampling hold circuit in MCU, as AD passage, is namely connected with the ADC of MCU this optical line terminal, waits for the arrival of the high level signal of the first triggering signal; When the first triggering signal is high level signal, MCU carries out RSSI interruption, and now, sampling hold circuit is sampled to the sampled voltage received, and carries out analog-to-digital conversion process by the ADC that sampled voltage to be inputed to MCU by I/O port; When saltus step is low level signal to the first triggering signal again, sampling hold circuit completes sampling, now, I/O port is set to output port by MCU, and be set to low level, because I/O port is low level, thus the electric charge that the RC circuit in sampling hold circuit stores is timely released, the sampled voltage in sampling hold circuit is reset; Afterwards, MCU exits RSSI and interrupts, and this I/O port is re-set as AD passage, waits for the next high level signal of the first triggering signal.
Based on above-described embodiment, further, this optical line terminal also comprises control circuit, and this control circuit is connected with the input of sampling hold circuit, and/or this control circuit is connected with the output of sampling hold circuit; Wherein:
After sampling hold circuit completes sampling, the sampled voltage in this sampling hold circuit resets by the control circuit be connected with this sampling hold circuit.
Under which, due to the effect of control circuit, make sampling hold circuit after completing sampling processing, RC circuit in sampling hold circuit can discharge in time, namely mirror current source exports almost nil, avoid the impact on sampling processing result next time, improve accuracy and precision that RSSI reports value, achieve less, the more accurate luminous power of optical line terminal and report.
In force, one end of the sampling resistor of this optical line terminal is connected with the output of mirror current source, and the other end ground connection of this sampling resistor.Preferably, control circuit and the sampling resistor of the embodiment of the present invention are connected in parallel, and namely this control circuit is connected with the output of mirror current source, and the other end ground connection of this control circuit.
In force, for triggering the first triggering signal of sampling hold circuit and the second triggering signal reverse signal each other for trigger control circuit.
As the preferred implementation of one, control circuit comprises a control switch, and wherein, one end of this control switch is connected with the input of sampling hold circuit, the other end ground connection of this control switch.
Based on above-mentioned any embodiment, this optical line terminal can adopt arbitrary structure of embodiment one ~ embodiment three on hardware, and, the technical scheme that this optical line terminal resets in conjunction with the sampled voltage on software, realize after sampling hold circuit completes sampling, resetting the sampled voltage of sampling hold circuit.
Below the course of work of the optical line terminal that the embodiment of the present invention provides is described.Operationally, when the first triggering signal is low level signal, the I/O port be connected with sampling hold circuit in MCU, as AD passage, is namely connected with the ADC of MCU, waits for the arrival of the high level signal of the first triggering signal; When the first triggering signal is high level signal, MCU carries out RSSI interruption, and now, sampling hold circuit is sampled to the sampled voltage received, and carries out analog-to-digital conversion process by the ADC that sampled voltage to be inputed to MCU by I/O port; When saltus step is low level signal to the first triggering signal again, sampling hold circuit completes sampling, now, I/O port is set to output port by MCU, and is set to low level, because I/O port is low level, thus the electric charge that the RC circuit in sampling hold circuit stores is timely released, sampled voltage in sampling hold circuit is reset, and meanwhile, the sampled voltage in sampling hold circuit also can reset by control circuit under the triggering of the second triggering signal; Afterwards, MCU exits RSSI and interrupts, and this I/O port is re-set as AD passage, waits for the next high level signal of the first triggering signal.
Certainly, the software and hardware combining that the embodiment of the present invention provides realizes after sampling hold circuit completes sampling, and when resetting the sampled voltage of sampling hold circuit, optical line terminal also adopts the structure of embodiment two or embodiment three on hardware.
Although describe the preferred embodiments of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. an optical line terminal, the microprogram control unit MCU comprising optical fiber receive module APD, the mirror current source be connected with the output of described APD, the sampling hold circuit be connected with the output of described mirror current source and be connected with the output of described sampling hold circuit, it is characterized in that
Described optical line terminal also comprises control circuit, and described control circuit is connected with the input of described sampling hold circuit, and/or described control circuit is connected with the output of described sampling hold circuit;
Wherein, after described sampling hold circuit completes sampling, the sampled voltage in described sampling hold circuit resets by described control circuit.
2. optical line terminal as claimed in claim 1, it is characterized in that, described control circuit and sampling resistor are connected in parallel, and wherein, one end of described sampling resistor is connected with the output of described mirror current source, and the other end ground connection of described sampling resistor.
3. optical line terminal as claimed in claim 1 or 2, is characterized in that, for the first triggering signal of triggering described sampling hold circuit with for triggering the second triggering signal reverse signal each other of described control circuit.
4. the optical line terminal as described in any one of claims 1 to 3, it is characterized in that, described control circuit comprises a control switch, wherein, one end of described control switch is connected with the input of described sampling hold circuit or output, the other end ground connection of described control switch.
5. the optical line terminal as described in any one of Claims 1 to 4, is characterized in that,
When described sampling hold circuit is sampled, the sampled voltage that described sampling hold circuit exports to be transferred to the AD conversion unit in described MCU by described MCU by the I/O port that is connected with described sampling hold circuit; And,
After described sampling hold circuit completes sampling, described I/O port is set to low level by described MCU, resets to make the sampled voltage in described sampling hold circuit.
6. an optical line terminal, the microprogram control unit MCU comprising optical fiber receive module APD, the mirror current source be connected with the output of described APD, the sampling hold circuit be connected with the output of described mirror current source and be connected with the output of described sampling hold circuit, it is characterized in that
When described sampling hold circuit is sampled, the sampled voltage that described sampling hold circuit exports to be transferred to the AD conversion unit in described MCU by described MCU by the I/O port that is connected with described sampling hold circuit; And,
After described sampling hold circuit completes sampling, described I/O port is set to low level by described MCU, resets to make the sampled voltage in described sampling hold circuit.
7. optical line terminal as claimed in claim 6, it is characterized in that, described optical line terminal also comprises control circuit, and described control circuit is connected with the input of described sampling hold circuit, and/or described control circuit is connected with the output of described sampling hold circuit;
Wherein, after described sampling hold circuit completes sampling, the sampled voltage in described sampling hold circuit resets by described control circuit.
8. optical line terminal as claimed in claim 7, it is characterized in that, described control circuit and sampling resistor are connected in parallel, and wherein, one end of described sampling resistor is connected with the output of described mirror current source, and the other end ground connection of described sampling resistor.
9. as claimed in claim 7 or 8 optical line terminal, is characterized in that, for the first triggering signal of triggering described sampling hold circuit with for triggering the second triggering signal reverse signal each other of described control circuit.
10. the optical line terminal as described in any one of claim 7 ~ 9, is characterized in that, described control circuit comprises a control switch, and wherein, one end of described control switch is connected with the input of described sampling hold circuit, the other end ground connection of described control switch.
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| CN201310740635.0A CN104753605A (en) | 2013-12-27 | 2013-12-27 | Optical line terminal |
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| CN201310740635.0A CN104753605A (en) | 2013-12-27 | 2013-12-27 | Optical line terminal |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1179034A (en) * | 1996-09-13 | 1998-04-15 | 三星电子株式会社 | Method and device for controlling digit automatic gain of mobile radio communication system communication terminal |
| CN102364857A (en) * | 2011-02-01 | 2012-02-29 | 杭州士兰微电子股份有限公司 | Primary side constant current switching power controller and method |
| CN102394630A (en) * | 2011-11-25 | 2012-03-28 | 浙江商业职业技术学院 | Peak value sampling retaining circuit and method thereof used for switch power supply |
| CN102780525A (en) * | 2011-05-09 | 2012-11-14 | 深圳新飞通光电子技术有限公司 | Burst received optical power detection device and method thereof |
-
2013
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1179034A (en) * | 1996-09-13 | 1998-04-15 | 三星电子株式会社 | Method and device for controlling digit automatic gain of mobile radio communication system communication terminal |
| CN102364857A (en) * | 2011-02-01 | 2012-02-29 | 杭州士兰微电子股份有限公司 | Primary side constant current switching power controller and method |
| CN102780525A (en) * | 2011-05-09 | 2012-11-14 | 深圳新飞通光电子技术有限公司 | Burst received optical power detection device and method thereof |
| CN102394630A (en) * | 2011-11-25 | 2012-03-28 | 浙江商业职业技术学院 | Peak value sampling retaining circuit and method thereof used for switch power supply |
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Application publication date: 20150701 |