CN104750561B - Dynamic release method, system and a kind of processor of register file cache resources - Google Patents
Dynamic release method, system and a kind of processor of register file cache resources Download PDFInfo
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Abstract
The present invention provides a kind of dynamic release method of register file cache resources, system and a kind of processor, real-time monitoring can be carried out to long delay event in the case where not increasing and not modifying instruction, it is sent when monitoring long delay event and the register file buffer list entry that the thread where the long delay event occupies is labeled as the request preferentially replaced, after receiving request, the occupied register entry of the thread can be labeled as preferentially replacing by register file caching in time, if find later other threads need by its register from called in main register file register file caching in, then preferentially the thread can be replaced away, and other threads are unaffected.Therefore, compared with prior art, sensitiveer using monitoring of this programme to long delay event and do not need to be adjusted instruction, it is higher to the release recovery efficiency of register file cache resources.
Description
Technical field
The present invention relates to the technical field of multiline procedure processor design, the dynamics of specifically a kind of register file cache resources
Method for releasing, system and a kind of processor.
Background technique
The register file of multiline procedure processor generallys use the design of multi-level register file structure, including master register
Heap MRF (Main Register File)；RFC (Register File Cache) is cached with register file.
Main register file is used to store the general register of all threads, and capacity is big, but port is limited, and speed also compares
It is relatively slow.Register file caching port is more, and speed is fast, but capacity is small, general only to reserve a general deposits of 2-3 for per thread
The memory space of device.When some thread needs the register read not in register file caching and in main register file,
It needs that the register is got back to register file caching from main register file by replacement policy and uses, while choosing register
One list item of heap caching eliminates, and replacement policy is usually least recently used (Least Recently Use).Deposit
Device heap caching shares for multithreading, and resource is very valuable, in multiline procedure processor, how timely not to run temporary suspension
Thread occupied register file cache resources release recycling, allow the thread of needs to come using being multi-level register file
Design major issue in need of consideration.
In the prior art, mainly go out to may cause the instruction of long delay in static compilation phase lookup by compiler, this
Result of a little instructions after the completion of execution does not write back register file caching, directly writes back main register file, these may cause length
The instruction of delay includes the access instruction of system command and shared data, such as the Exclusive Load in ARMv8.This method is deposited
In following technical problem:
(1) instruction that compiler identifies in the static compilation stage is excessively general, because system command and access instruction are referring to
It enables and often occurring in stream, but the pause of long delay might not be will lead to.If the implementing result of all these instructions is not write
It returns register file caching and the execution efficiency of thread and slow to register file can be seriously affected if directly writing back main register file
Depositing resource is a kind of waste.
(2) static compilation needs tell these instructions of hardware to need by increasing the bit of some Hint types in instruction
The operation that progress Bypass is cached to register file can also bring thread execution efficiency equivalent to increase new instruction
It influences.
Summary of the invention
For this purpose, technical problem to be solved by the present invention lies in release recycling register file cache resources in the prior art
Method efficiency is lower.
In order to solve the above technical problems, the present invention provides a kind of dynamic release method of register file cache resources, including
Following steps:
Monitor whether each thread has long delay event；
If so, then judging whether thread where the long delay event occupies effective register file buffer list entry；
If occupying, the register file buffer list entry for occupying the thread where the long delay event is sent labeled as preferential
The request of replacement.
Preferably, the dynamic release method of the register file cache resources, it is described to have monitored whether that long delay thing occurs
The step of thread of part includes:
Whether each thread of actively monitoring occurs long delay event；And/or
It receives and the long delay signal that the thread of long delay event is sent occurs.
Preferably, the dynamic release method of the register file cache resources, transmission will be online by the long delay event institute
The register file buffer list entry of Cheng Zhanyong is labeled as the request preferentially replaced
Call number of the list item in register file caching and preferentially replace indication signal.
Preferably, the dynamic release method of the register file cache resources, will be where the long delay event sending
The register file buffer list entry that thread occupies is labeled as after the request preferentially replaced further include:
Judge whether the long delay event closes to an end；
Restore the request of long delay event place thread to the occupancy of register file buffer list entry if so, sending.
The present invention also provides a kind of dynamic release methods of register file cache resources, comprising the following steps:
It receives and the register file buffer list entry that the thread where long delay event occupies is labeled as the request preferentially replaced；
The register file buffer list entry for being occupied thread where long delay event according to the request is labeled as preferential replacement.
Preferably, the dynamic release method of the register file cache resources, will be online by long delay time institute receiving
The register file buffer list entry of Cheng Zhanyong is labeled as before the request preferentially replaced further include:
For register file buffer list entry, call number and marker are set；
It receives and the register file buffer list entry that the thread where long delay event occupies is labeled as the request preferentially replaced
In: the request includes the call number and preferential replacement indication signal of list item；
The register file buffer list entry for being occupied thread where long delay event according to the request is labeled as preferential replacement
In: register file buffer list entry is determined according to call number, sets the marker of the list item to preferentially to replace indication signal.
Preferably, the dynamic release method of the register file cache resources is requested according to described by long delay event
After the register file buffer list entry that place thread occupies is labeled as preferential replacement further include:
Receive request of the thread to the occupancy of register file buffer list entry where restoring the long delay event；
Occupancy of the thread to register file buffer list entry where restoring the long delay event.
The present invention also provides a kind of dynamic release systems of register file cache resources, comprising:
Monitoring unit, for monitoring whether each thread has long delay event；
Judging unit is connected with the monitoring unit, for monitoring that a certain thread has long delay in the monitoring unit
When event occurs, judge whether thread where the long delay event occupies effective register file buffer list entry；
Transmission unit is connected with the judging unit, for judging that the long delay event institute is online in the judging unit
When the effective register file buffer list entry of Cheng Zhanyong, sends and cache register file that thread where the long delay event occupies
List item is labeled as the request preferentially replaced.
Preferably, in the dynamic release system of the register file cache resources, the monitoring unit is used for actively monitoring
Whether each thread occurs long delay event；And/or
It receives and the long delay signal that the thread of long delay event is sent occurs.
Preferably, in the dynamic release system of the register file cache resources, the request packet of the transmission unit transmission
It includes call number of the list item in register file caching and preferentially replaces indication signal.
Preferably, in the dynamic release system of the register file cache resources, the judging unit, being also used to judge should
Whether long delay event closes to an end；
The transmission unit is also used to when the judging unit judges that the long delay event closes to an end, and is sent and is restored
Request of the thread to the occupancy of register file buffer list entry where the long delay event.
The present invention also provides a kind of register file cachings, comprising:
Receiving unit, for receiving the register file buffer list entry for occupying the thread where long delay event labeled as excellent
The request first replaced；
Releasing unit is connected with the receiving unit, for being occupied thread where long delay event according to the request
Register file buffer list entry labeled as preferential replacement.
Preferably, the register file caching, further includes setting unit:
The setting unit, for call number and marker to be arranged for register file buffer list entry；
The receiving unit, the register file buffer list entry for occupying the thread where long delay event received mark
Request preferentially to replace includes the call number and preferential replacement indication signal of list item；
The releasing unit determines corresponding register file buffer list entry according to call number, the marker of the list item is set
It is set to preferential replacement indication signal.
Preferably, the register file caching, further includes recovery unit:
The receiving unit, thread where being also used to receive the recovery long delay event account for register file buffer list entry
Request；
The recovery unit is connected with the receiving unit, for thread where restoring the long delay event to register
The occupancy of heap buffer list entry.
The present invention also provides a kind of processors, comprising:
The dynamic release system of above-mentioned register file cache resources and above-mentioned register file caching；
Register file caching, in the request for receiving a certain thread and needing to call in register from main register file
When, random selection is marked with the list item preferentially replaced and is replaced.
The above technical solution of the present invention has the following advantages over the prior art:
Dynamic release method, system and a kind of processor of register file cache resources of the present invention, can be not
Increase and real-time monitoring is carried out to long delay event in the case where not modifying instruction, sending when monitoring long delay event will be by
The register file buffer list entry that thread where the long delay event occupies is labeled as the request preferentially replaced, and after receiving request, posts
Storage heap caching can be in time by the occupied register entry of the thread labeled as can preferentially replace, if finding other lines later
Journey needs the thread from calling in main register file in register file caching then can preferentially be replaced away to its register,
And other threads are unaffected.Therefore, compared with prior art, cleverer using monitoring of this programme to long delay event
It is quick and do not need to be adjusted instruction, it is higher to the release recovery efficiency of register file cache resources.
Detailed description of the invention
In order to make the content of the present invention more clearly understood, it below according to specific embodiments of the present invention and combines
Attached drawing, the present invention is described in further detail, wherein
Fig. 1 is the dynamic release method of register file cache resources described in 1 one specific examples of the embodiment of the present invention
Flow chart；
The stream of the dynamic release method of register file cache resources described in 1 one specific examples of Fig. 2 embodiment of the present invention
Cheng Tu；
Fig. 3 is the dynamic release method of register file cache resources described in 2 one specific examples of the embodiment of the present invention
Flow chart；
Fig. 4 is the dynamic release method of register file cache resources described in 2 one specific examples of the embodiment of the present invention
Flow chart；
Fig. 5 is the dynamic release system and register file of register file cache resources described in a specific example of the invention
Cache the functional block diagram being used cooperatively；
Fig. 6 is the dynamic release system and register file of register file cache resources described in a specific example of the invention
Cache the functional block diagram being used cooperatively；
Fig. 7 is the schematic diagram of the dynamic release process of register file cache resources described in the embodiment of the present invention 5.
Specific embodiment
Embodiment 1
The present embodiment provides a kind of dynamic release methods of register file cache resources, are mainly used in multiline procedure processor
In, for operating to register file caching, it is slow that register file is sent a request to when needing to discharge register file cache resources
It deposits.As shown in Figure 1, specifically comprising the following steps:
S11: monitoring whether each thread has long delay event, and S12 is entered step if having, and otherwise continues to monitor.
Wherein it is possible to which setting time threshold value determines whether long delay event, the time that event needs to pause is more than the time threshold
Then regard as long delay event.It can also be not provided with specific time threshold, but according to warp during processor design
Determining long delay event is tested, as memory access missing, write operation cache read-after-write conflict (Store Buffer RAW), branch prediction
Mistake, wherein access missing such as TLB (Translation Look-aside Buffer) missing, second-level cache missing, three
Grade Cache missing performs the instruction of fence class such as Sync, T1bi etc., these are all the long delay events generally acknowledged in processor.
S12: judging whether thread where long delay event occupies effective register file buffer list entry, if occupying into
Enter step S13, otherwise return step S11 continues to be monitored thread.
S13: the register file buffer list entry for occupying the thread where the long delay event is sent labeled as preferential replacement
Request.
By carrying out real-time monitoring to thread, sensitivity is higher, and long delay event is not also general is defined in system
The access instruction of instruction or shared data, but judged according to time threshold, or directly assert clear when design processor
Long delay event, had higher efficiency in specific execute.
Wherein the monitoring mode in step S11 can have following two:
Whether each thread of actively monitoring occurs long delay event, such as the state of Monitoring instruction transmitting queue, judges that it is
It is no to transmit a fence class instruction, if so, illustrating that this thread is to pause within some time.Also it can receive hair
Grow delay event thread send long delay signal, such as have occurred Cache missing or TLB missing after, memory access unit LSU
(Load Store Unit), which can be sent, will the long delay signal to pause for a long time.
Preferably, in step s 13, the register file cache table for occupying the thread where the long delay event of transmission
Item replaces indication signal labeled as the call number requested including list item in register file caching preferentially replaced and preferentially.It is logical
Cross list item marked index number can a certain thread occupies in flag register heap caching all registers, call number can use
Thread number indicates, can so determine the list item for needing preferentially to replace quickly, other running threads are cached in register file
In register entries (i.e. storage content) will not be gone out by LRU replacement, but the deposit of the thread the long delay event
Device entry is preferentially replaced, and is equivalent to and is increased the use resource that register file caches to other threads.
It is further preferred that as shown in Fig. 2, further including following steps after the step S13:
S14: judging whether the long delay event closes to an end, if then entering step S15, otherwise repeats this step.
S15: request of the thread to the occupancy of register file buffer list entry where restoring the long delay event is sent.
By aforesaid operations, the register entries of some register files caching of the thread can be restored in advance, more effectively
Raising be resumed thread register file caching service efficiency.
Embodiment 2
The present embodiment provides a kind of dynamic release methods of register file cache resources, applied in multiline procedure processor
In register file caching, cooperate with the method in embodiment 1, as shown in Figure 3, comprising the following steps:
S21: it receives the register file buffer list entry that the thread where long delay event occupies and is asked labeled as what is preferentially replaced
It asks.
S22: the register file buffer list entry for being occupied thread where long delay event according to the request is labeled as preferential
Replacement.
When there are other threads to need to call in its register from main register file register file caching, then will preferentially post
Label is replaced away in storage heap caching for the entry of replacement.
Preferably, further include following steps before step S21:
S20: being arranged call number and marker for register file buffer list entry, and wherein call number can be the occupancy register
Thread thread number, flag bit can indicate with simplest " 1 " and " 0 ", and such as " 1 " indicates preferentially to replace, " 0 " table
Showing preferentially to replace.
In the step s 21, the request received includes the call number and preferential replacement indication signal of list item.Call number
As thread number, preferential indication signal of replacing is " 1 ".
In step S22, the list item of corresponding register file caching is determined according to call number, the marker of the list item is set
It is set to preferential replacement indication signal.The register that thread occupancy can be quickly found according to thread number, if deposited at this time
The flag bit of device is " 0 ", then the preferential replacement indication signal " 1 " received remaining carries out and operation, so that flag bit be set
It is set to " 1 ", can preferentially be replaced.When having during other threads cache from calling in main register file to register file, occupy
When register, then " 0 " is set by the marker, indicates that the register can not be replaced.Only have the register can be by
When replacement, flag bit can just be arranged to " 1 ".
Preferably, as shown in figure 4, it is further comprising the steps of after step s 22:
S23: request of the thread to the occupancy of register file buffer list entry where restoring the long delay event is received.
S24: occupancy of the thread to register file buffer list entry where restoring the long delay event.The step can choose
The idle periods of data path between register file caching and main register file carry out.
By restoring some register file cache entries of the thread in advance, it can effectively improve and be resumed posting for thread
The service efficiency of storage heap caching.
Embodiment 3
The present embodiment provides a kind of dynamic release systems 1 of register file cache resources, are applied in multiline procedure processor,
Cooperate with register file caching 2, as shown in Figure 5, comprising:
Monitoring unit 101, for monitoring whether each thread has long delay event.It can be sentenced with setting time threshold value
Whether fixed be long delay event, and it is more than that the time threshold then regards as long delay event that event, which needs the time paused,.It can also be with
It is not provided with specific time threshold, but the empirically determined long delay event for being during processor design, such as visit
Missing, write operation caching read-after-write conflict (Store Buffer RAW), branch misprediction are deposited, wherein access missing is for example
TLB (Translation Look-aside Buffer) missing, three-level Cache missing, performs fence at second-level cache missing
Class instruction such as Sync, Tlbi etc., these are all the long delay events generally acknowledged in processor.
Judging unit 102 is connected with the monitoring unit 101, for monitoring that a certain thread has in the monitoring unit
When long delay event occurs, judge whether thread where the long delay event occupies effectively register file buffer list entry.
Transmission unit 103 is connected with the judging unit 102, for judging the long delay thing in the judging unit 102
When thread occupies effective register file buffer list entry where part, the deposit for occupying the thread where the long delay event is sent
Device heap buffer list entry is labeled as the request preferentially replaced.
For this programme by carrying out real-time monitoring to thread, sensitivity is higher, and the also not general restriction of long delay event
In system command or the access instruction of shared data, but judged according to time threshold, or directly assert design processor
When specific long delay event, had higher efficiency in specific execute.
Preferably, whether the monitoring unit 101 occurs long delay event for each thread of actively monitoring；And/or it connects
The long delay signal that the thread of transmitting-receiving growth delay event is sent.Wherein:
Whether each thread of actively monitoring occurs long delay event, such as the state of Monitoring instruction transmitting queue, judges that it is
It is no to transmit a fence class instruction, if so, illustrating that this thread is to pause within some time.Also it can receive hair
Grow delay event thread send long delay signal, such as have occurred Cache missing or TLB missing after, memory access unit LSU
(Load Store Unit) sends notification signal to the system in the present embodiment.
It is further preferred that the request that the transmission unit 103 is sent includes index of the list item in register file caching
Number and preferentially replace indication signal.It, can be quickly by all registers of the thread in call number flag register heap caching
Determine the register that needs preferentially to replace, register entries of other running threads in register file caching will not be by
LRU replacement is gone out, but the register entries of the thread of the long delay event are preferentially replaced, and is equivalent to and is increased to other threads
The use resource of register file caching.
Preferably, the judging unit 102, is also used to judge whether the long delay event closes to an end.The transmission is single
Member 103, is also used to when the judging unit 102 judges that the long delay event closes to an end, and sends and restores the long delay event
Request of the place thread to the occupancy of register file buffer list entry.The some register files that can restore the thread in advance in this way are slow
The register entries deposited more effectively improve the register file caching service efficiency for being resumed thread.
Embodiment 4
The present embodiment provides a kind of register file cachings 2, the dynamic with register file caching thread described in embodiment 3
Release system 1 cooperates, as shown in Figure 5, comprising:
Receiving unit 201 is labeled as receiving the register file buffer list entry that the thread where long delay event occupies
The request preferentially replaced.
Releasing unit 202 is connected with the receiving unit, for being accounted for thread where long delay event according to the request
Register file buffer list entry is labeled as preferential replacement.
When there are other threads to need to call in its register from main register file register file caching, then will preferentially post
Label has the list item of replacement to replace away in storage heap caching.
It preferably, further include setting unit 203, for call number and marker to be arranged for register file buffer list entry.
The receiving unit 201, the register file buffer list entry mark that the thread where long delay event received occupies
It is denoted as the call number and preferential replacement indication signal that the request preferentially replaced includes list item；Wherein call number can post to occupy this
The thread number of the thread of storage, flag bit can indicate that such as " 1 " indicates preferentially to replace with simplest " 1 " and " 0 ",
" 0 " indicates preferentially to replace.
The releasing unit 202 determines the list item of corresponding register file caching according to call number, by the mark of the list item
Position is set as preferentially replacing indication signal.The register that thread occupancy can be quickly found according to thread number, if at this time
The flag bit of register is " 0 ", then it is carried out or operated with the preferential replacement indication signal " 1 " received, thus will mark
Position is set as " 1 ", can preferentially be replaced.When having during other threads cache from calling in main register file to register file,
When occupying register, then by the marker " 0 " is set, indicates that the register can not be replaced.Only have the register can
When preferentially being replaced, flag bit can just be arranged to " 1 ".
It is further preferred that as shown in fig. 6, further including recovery unit 204.The receiving unit 201, is also used to receive extensive
Request of the thread to the occupancy of register file buffer list entry where the multiple long delay event.The recovery unit 204, connects with described
It receives unit 201 to be connected, for thread where restoring the long delay event to the occupancy of register file buffer list entry.By extensive in advance
Some register file cache entries of the multiple thread can effectively improve the use effect for being resumed the register file caching of thread
Rate.
Embodiment 5
The present embodiment provides a kind of processor, the dynamic release system including register file cache resources described in embodiment 3
System and register file as described in example 4 caching.Register file caching, receive other threads need by register from
When the request that main register file is called in, random selection is marked with the list item preferentially replaced and is replaced.Specifically with data manipulation
For address translation bypass buffers (DTLB) missing, which will lead to the thread belonging to it and to wait for a long time, until hard
Part page table lookaside buffer backfill (Hardware table walk) end backfills TLB, and during which the thread may need to pause
A clock cycle up to a hundred.Detailed process such as Fig. 7, the information that each table indicates in figure are as follows:
First row: the thread number and preferentially replace indication signal that the dynamic release system of register file cache resources is sent
Jointly control signal；Secondary series: marker identifies whether the thread has preferential replacement power when replacing next time；Third column:
Thread number；4th column: register number；It needs to be combined with thread number to determine register, such as: register number 4, line
Journey number is 2, then the value of corresponding register is the value of No. 4 registers of thread 2；5th column: the corresponding value of register.
Step 1, DTLB missing has occurred in memory access unit 3, i.e. LSU (Load Store Unit) in implementation procedure, will
Missing indication signal passes to the dynamic release system of register file caching thread.
If being that the long delay event has occurred in No. 3 threads in this instance, then in step 2, register file caching thread is moved
State discharges system for thread number " 3 " and preferential replacement indication signal " 1 ", is sent to register file caching.
Step 3, pass through in register file caching or the flag bit of the long delay thread is replaced with " 1 " by operation.I.e. by line
Flag bit corresponding to the list item that journey number is 3 is set as " 1 ".
It step 4, can preferentially be the entry of " 1 " from flag bit in next register file buffer list entry replacement process
Middle random selection is replaced, and the flag bit of the entry is reset after replacement, when there is no the entry that flag bit is " 1 ", is continued
It is replaced using original lru algorithm.
The method whether scheme in the present embodiment has long delay event by hardware real-time monitoring thread, does not need to modify
Instruction format itself increases new instruction, and sensitive to long delay event detection, slow by thread number flag register heap
All registers of the thread in depositing, cracking find of energy can carry on the back the register preferentially replaced, enable other running lines
Cheng Shouyi, because the entry in register file caching of other threads will not be gone out by LRU replacement, but the pause line
The register entries of journey are preferentially replaced, and are equivalent to and are increased the use resource that register file caches to other threads.
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as method, system or computer program
Product.Therefore, complete hardware embodiment, complete software embodiment or reality combining software and hardware aspects can be used in the present invention
Apply the form of example.Moreover, it wherein includes the computer of computer usable program code that the present invention, which can be used in one or more,
The computer program implemented in usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) produces
The form of product.
The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Claims (15)
1. a kind of dynamic release method of register file cache resources, which comprises the following steps:
Monitor whether each thread has long delay event；
If having, then judge whether thread where the long delay event occupies effective register file buffer list entry；
If occupying, the register file buffer list entry for occupying the thread where the long delay event is sent labeled as preferential replacement
Request.
2. the dynamic release method of register file cache resources according to claim 1, which is characterized in that the monitoring is
It is no have occur long delay event thread the step of include:
Whether each thread of actively monitoring occurs long delay event；And/or
It receives and the long delay signal that the thread of long delay event is sent occurs.
3. the dynamic release method of register file cache resources according to claim 1, which is characterized in that transmission will be by this
The request that the register file buffer list entry that thread where long delay event occupies is labeled as preferentially replacing includes:
Call number of the list item in register file caching and preferentially replace indication signal.
4. the dynamic release method of register file cache resources according to claim 1, which is characterized in that will be by sending
The register file buffer list entry that thread where the long delay event occupies is labeled as after the request preferentially replaced further include:
Judge whether the long delay event closes to an end；
Restore the request of long delay event place thread to the occupancy of register file buffer list entry if so, then sending.
5. a kind of dynamic release method of register file cache resources, which comprises the following steps:
It receives and the register file buffer list entry that the thread where long delay event occupies is labeled as the request preferentially replaced；It is described
Request is to have monitored that long delay event occurs for thread by processor, and thread where the long delay event occupies effective deposit
It is transmitted when device heap buffer list entry；
The register file buffer list entry for being occupied thread where long delay event according to the request is labeled as preferential replacement.
6. the dynamic release method of register file cache resources according to claim 5, which is characterized in that will be by receiving
The register file buffer list entry that thread where the long delay time occupies is labeled as before the request preferentially replaced further include:
For register file buffer list entry, call number and marker are set；
It receives and the register file buffer list entry that the thread where long delay event occupies is labeled as in the request preferentially replaced: institute
State the call number and preferential replacement indication signal that request includes list item；
The register file buffer list entry for being occupied thread where long delay event according to the request is labeled as in preferential replacement: root
Register file buffer list entry is determined according to call number, sets the marker of the list item to preferentially to replace indication signal.
7. the dynamic release method of register file cache resources according to claim 5, which is characterized in that according to
After the register file buffer list entry that request occupies thread where long delay event is labeled as preferential replacement further include:
Receive request of the thread to the occupancy of register file buffer list entry where restoring the long delay event；
Occupancy of the thread to register file buffer list entry where restoring the long delay event.
8. a kind of dynamic release system of register file cache resources characterized by comprising
Monitoring unit, for monitoring whether each thread has long delay event；
Judging unit is connected with the monitoring unit, for monitoring that a certain thread has long delay event in the monitoring unit
When generation, judge whether thread where the long delay event occupies effective register file buffer list entry；
Transmission unit is connected with the judging unit, for judging that thread where the long delay event accounts in the judging unit
When with effective register file buffer list entry, the register file buffer list entry for occupying the thread where the long delay event is sent
Labeled as the request preferentially replaced.
9. the dynamic release system of register file cache resources according to claim 8, it is characterised in that:
Whether the monitoring unit occurs long delay event for each thread of actively monitoring；And/or
It receives and the long delay signal that the thread of long delay event is sent occurs.
10. the dynamic release system of register file cache resources according to claim 8, it is characterised in that:
The request that the transmission unit is sent includes call number and preferential replacement instruction letter of the list item in register file caching
Number.
11. the dynamic release system of register file cache resources according to claim 8, it is characterised in that:
The judging unit, is also used to judge whether the long delay event closes to an end；
The transmission unit is also used to when the judging unit judges that the long delay event closes to an end, and is sent and is restored the length
Request of the thread to the occupancy of register file buffer list entry where delay event.
12. a kind of register file caching characterized by comprising
The register file buffer list entry that the thread where long delay event occupies is labeled as preferentially replacing by receiving unit for receiving
The request changed；The request is to have monitored that long delay event, and thread where the long delay event occur for thread by processor
It occupies transmitted when effective register file buffer list entry；
Releasing unit is connected with the receiving unit, for being posted according to the request by what thread where long delay event occupied
Storage heap buffer list entry is labeled as preferential replacement.
13. register file caching according to claim 12, which is characterized in that further include setting unit:
The setting unit, for call number and marker to be arranged for register file buffer list entry；
The receiving unit, the register file buffer list entry for occupying the thread where long delay event received is labeled as excellent
The request first replaced includes the call number and preferential replacement indication signal of list item；
The releasing unit determines corresponding register file buffer list entry according to call number, sets the marker of the list item to
Preferential replacement indication signal.
14. register file caching according to claim 12, it is characterised in that further include recovery unit:
The receiving unit is also used to receive the occupancy for restoring long delay event place thread to register file buffer list entry
Request；
The recovery unit is connected with the receiving unit, slow to register file for thread where restoring the long delay event
Deposit the occupancy of list item.
15. a kind of processor characterized by comprising
Dynamic release system including any register file cache resources of claim 8-11；
Any register file caching of claim 12-14；
The register file caching, when receiving the request that a certain thread needs to call in register from main register file, with
Machine selected marker has the list item preferentially replaced to be replaced.
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