CN1047406A

CN1047406A - The dual-port storage of real-time signal processor

Info

Publication number: CN1047406A
Application number: CN 89102868
Authority: CN
Inventors: 蒋南峰; 刘耀骐; 肖允治
Original assignee: Individual
Current assignee: Individual
Priority date: 1989-05-08
Filing date: 1989-05-08
Publication date: 1990-11-28

Abstract

A kind of dual-port storage of real-time signal processor belongs to computing machine, digital signal processing, real-time signal processing technology field.The present invention proposes to utilize the serial port of twoport dynamic memor spare as the I/O of high-speed real-time signal, new departure that its parallel port is carried out access through a plurality of paths, a plurality of processor, this scheme only just can realize the exchange of data I/O buffer zone and deal with data storage portions simply to the change of an addressing benchmark pointer with counting circuit, in addition, because I/O buffer zone and deal with data storage portions are co-located in the storage entity, can be convenient to many batch datas relation is each other handled.

Description

The dual-port storage of real-time signal processor

The invention belongs to computing machine, digital signal processing, real-time signal processing technology field.

Live signal to successive input carries out continual disposal route two identical storage structures of use usually at present, when one as the deal with data memory during by the processor access, another carries out the input of live signal and the output of result then as input/output (i/o) buffer through input-output apparatus.After the I/O process of a batch data was finished, the processing procedure in the deal with data memory also finished.Two storage structures switch with on-off circuit, exchange the status mutually, thereby can guarantee the continuity handled.

But in the high-speed real-time signal processor,, generally all use a plurality of processors, by a plurality of paths the deal with data memory is carried out access simultaneously for improving data processing speed.If adopt above-mentioned common disposal route, then the high-speed switching circuit of the address bus of a plurality of paths, data bus will take the equipment cost and the volume of significant proportion.In addition, because adjacent two batch data branches are in two structures, feasible processing often can only be confined to carry out in same batch data, if a batch data is an images of moving target, will meet difficulty need be by the motion process of the data analysis target of different batches the time.

The objective of the invention is to use the memory of device configuration high-speed parallel real-time signal processor cheaply, simplify the high speed switching mechanism of input/output (i/o) buffer and deal with data memory, reducing equipment cost and volume significantly, and realize the processing of multiple batches of data relation each other.

The present invention designs the new departure with the memory of twoport dynamic memor spare structure real-time signal processor.It is characterized in that utilizing the I/O of the serial port of twoport dynamic memor spare as the high-speed real-time signal, its parallel port is through a plurality of paths, and a plurality of processors carry out access.This programme can adopt the dynamic storaging chip of TMS4161 twoport or the dynamic storaging chip of TMS4461 twoport of high speed graphic display terminal.Its inner structure respectively as shown in Figures 1 and 2.They have serial and parallel two access ports, the also access according to priority at a high speed of its serial port, the I/O requirement of positive adaptation live signal; Its parallel port and common dynamic memory device are identical, can link to each other through a plurality of processors of a plurality of paths with the high-speed parallel operation, the serial port of device and parallel port have separately independently data bus (D among Fig. 1, Q and SIN sout, D Q and SDQ among Fig. 2), but two mouthfuls of shared cover address bus (A0-A7 among Fig. 1 and Fig. 2).Since serial port once can 256 orders of addressing data, take the time of address bus, the time that only is equivalent to data of parallel port addressing, therefore can think that the work of parallel port is subjected to the influence of serial port hardly, both can carry out addressing and access independently.

The structure of the memory of the said real-time signal processor of the present invention is shown in Fig. 3 frame of broken lines: the storage matrix of twoport dynamic memor spare is divided into n zone, has divided four Physical Extents into shown in this figure below Fig. 3 (a).In certain work period, specifying a storage portions is the I/O buffer zone, carry out access by serial port through the serial-shift device, outer a part of zone or the Zone Full of order is the data access-processing district, carries out access by a plurality of processors of parallel running through the parallel port that is linked to be a plurality of paths.Behind the data update all of I/O buffer zone, processing procedure in the deal with data storage portions finishes, before the next work period begins, interim deal with data storage portions the last week that will have a result is reassigned and is the I/O buffer zone, make result to export through serial port, there is the I/O buffer zone of input data in the last cycle and reassigns and be the deal with data storage portions, make its input data that had enter processor, finished the exchange of I/O buffer zone and deal with data storage portions like this.This exchange needn't be changed by a large amount of on-off circuits, as long as the base address pointer when changing addressing as requested with counting circuit.

Because I/O buffer zone and deal with data storage portions are co-located in the storage entity, sequentially specify I/O buffer zone and deal with data district by turns according to the work period as shown in Figure 4, like this, to store simultaneously in a module has preceding n batch input and output data, and this facilitates is handled many batch datas relation each other.For the ease of management, the I/O buffer zone is defined as logical page (LPAGE) 0, go down by that analogy, as shown in Figure 4.The antagonistic relations of the module subregion (Physical Extents) of logical page (LPAGE) and reality are by the work period " rotation ", but for each work period of processor, the data of certain logical page (LPAGE) storage all have the identity logic status, for example: 0 page of I/O buffer zone always, 1 page of always current input imagery district.(" current " " last width of cloth " is all for processor among Fig. 4).

Above-mentioned dual-port storage also can be realized with VLSI (very large scale integrated circuit) technology.

Brief Description Of Drawings:

Fig. 1 is the dynamic storaging chip inner structure of TMS4161 twoport

Fig. 2 is the dynamic storaging chip inner structure of TMS4461 twoport

Twoport quadrature access storage unit the application in array real-time television image processor of Fig. 3 for constituting with twoport dynamic memor spare.

Wherein frame of broken lines is the storage module array.

Fig. 3 (a) is the synoptic diagram of a storage module.

Fig. 4 is the logical page (LPAGE) of twoport quadrature access storage unit when the processing of the TV image of continuous input being carried out on the time domain and the rotary corresponding relation of Physical Extents.

Fig. 5 is decomposed into the calculating process that one dimension is handled for twoport quadrature access storage unit 2D signal being handled.

Wherein (a) is the one dimension convolution algorithm synoptic diagram of horizontal direction

(b) be the long-pending computing synoptic diagram of a paper roll of vertical direction

(c) be the rotation of logical page (LPAGE) one Physical Extents corresponding relation

The 0th page is input/output (i/o) buffer, and the 1st page is the raw data district, and the 2nd page is the processing impact damper, and the 3rd page is destination accumulator.

The embodiment that the present invention is used for the real-time image signal processor as shown in Figure 3.Can use in the radar echo signal processor.

For using twoport quadrature memory of the present invention, it is divided into 4 * 4 modules shown in the frame of broken lines.Adopt the quadrature access structure, promptly can be by the horizontal direction access of picture intelligence, also can be by the vertical direction access.So that being decomposed into a plurality of one dimensions, the two-dimensional image processing handles.Be illustrated in figure 5 as the calculating process synoptic diagram that two-dimensional convolution is decomposed into the addition of a plurality of one dimension convolution.This algorithm makes the multiprocessor that carries out parallel processing can not need communication network (promptly " the flowing water data transfer line " on this figure top can save) each other.Experimental line uses 128 TMS4161 twoport storaging chips, can store back the television image of 512 * 512 point * 8.Switch I/O buffer zone and deal with data storage portions if use traditional on-off mode instead, this structure will need 4 * 4 * 2 * 8+19 * 2=294 high-speed switching circuit.Because TV data I/O speed is 10 ⁷Individual/second, memory chip must be selected high-speed chip for use.Cost and volume will improve 3～10 times.

Address translator uses TMS34061 and 12 " programmable logic array " 16V8 among Fig. 3.System controller is temporarily done simulated experiment with IBM-PC/XT at present.TMS34061 is a special chip, can produce needed various address signals of TV clock signal and dual-port storage and control signal easily.But its clock frequency can only arrive 10 ⁶Conspicuous it, influenced the access speed of the parallel port of experimental system.Test result, the serial port of this experimental system meets the requirement of television system vision signal fully.Because be subjected to the restriction of TMS34061, parallel port can only reach the speed of per second access 12.5 width of cloth pictures.If use novel dual-port storage TMS4461 instead module is divided into 8 * 8 modules, and designs address translator with high speed device, this storage system can satisfy the requirement of real-time television image processing fully.For the radar echo signal processor, present experimental system can meet the demands enough.

Experimental system uses 8 TMS320C25 to constitute the parallel processor array, use streamline communication mode per second can finish 3 of 12.5 width of cloth television images * 3 convolution algorithm, concerning this system, processor slice, thin piece number is unrestricted, if use 16 TMS320C25 then can finish 3 * 3 convolution algorithms in real time.If use the algorithm that two-dimensional convolution is decomposed into the one dimension convolution, then require module is divided into more module, just can reach the speed that TV needs, this will realize by means of the VLSI (very large scale integrated circuit) of this organization plan.Select for use the TMS320C25 machine of dealing with neither optimal selection in the experiment, if be the special-purpose array processor of this system design, speed and performance will be further enhanced.

Claims

1, a kind of dual-port storage of real-time processor is characterized in that utilizing the I/O of the serial port of twoport dynamic memor spare as the high-speed real-time signal, and its parallel port is through a plurality of paths, and a plurality of processors carry out access.

2,, it is characterized in that the storage matrix of said twoport dynamic memor spare is divided into n zone as the said dual-port storage of claim 1.In certain work period, specifying a storage portions is the I/O buffer zone, carry out access by serial port through the serial-shift device, a part of zone in addition or Zone Full are the data access-processing district, carry out access by a plurality of processors of parallel running through the parallel port that is linked to be a plurality of paths.Behind the data update all of I/O buffer zone, processing procedure in the deal with data storage portions finishes, before the next work period begins, interim deal with data storage portions the last week that will have a result is reassigned and is the I/O buffer zone, make result to export through serial port, there is the I/O buffer zone of input data in the last cycle reassigns and is the deal with data storage portions, makes its input data that had enter processor.