CN104735370B - A kind of CNC high-pressure multiple circuit for EMCCD - Google Patents
A kind of CNC high-pressure multiple circuit for EMCCD Download PDFInfo
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Abstract
The invention discloses a kind of CNC high-pressure multiple circuit for EMCCD, including DC level switching circuit, D/A converting circuit and the part of push-pull driver circuit three.The input signal of circuit includes 10 bit digital control signals and clock signal, and output signal is the multiple circuit that high pressure clock drive signals are used to drive EMCCD, outside offer+56V and+5V two-way direct current supplys.The high level of circuit output signal of the present invention has the stability better than 50mV, meets requirement of the high-quality imagings of EMCCD for high pressure clock drive signals.The present invention using digital controlled signal control output square-wave signal low and high level can remotely located EMCCD multiplication factor, realize applications of the EMCCD in space industry.
Description
Technical field
The present invention relates to optical imaging device EMCCD frequency multiplied clock actuation techniques, more particularly to remotely located EMCCD
Multiplication factor technology, belongs to automation control area.
Background technology
EMCCD technologies are also known as " gain on piece " technology, are a kind of new signal detection technologies of comparison, it with it is general
Logical CCD difference is to continue to have gain register again after its readout register, and its electrode structure is different from readout register, electricity
Lotus is after multistage gain register, and the gain of signal is up to more than 1000 times.Gain changes with temperature on piece, studies table
Bright, temperature is lower, and the multiplication gain on piece is higher, and noise is lower, is required to select in actual applications according to different use conditions
Select temperature control scheme.
The first Application of EMCCD technologies is that EMCCD technologies were applied to him by Andor Techology Ltd in 2001
Issue iXon series high-end hypersensitivity camera on.EMCCD technologies are fast-developing in the more than ten years after, main
To be applied to the fields such as astronomical observation, space flight, biological observation, according to different application conditions, select different refrigerating conditions and
Double control method., Derek Ives article in 2007《Advanced Microelectronics ULTRASPEC–A
low light level astronomical CCD camera for a high speed spectro-photometer
application》The spectrographic detection telescope manufactured using EMCCD as image device is described, the telescope is located at Chile,
Cold temperatures during work reach -100 DEG C.There are technical grade in the companies such as current Andor, E2V, Princeton Instrument
Sold using the EMCCD cameras of semiconductor cooler.In space industry, EMCCD there is no the precedent of in-orbit application, still visit at present
Rope stage, Gong Dezhu, Wang Li, Lu Xin in 2008《Space technology and application》Deliver《Micro light detecting EMCCD is highly sensitive
The application pre-test spent in star sensor》In, the research for having carried out exploration is applied in space flight for EMCCD.
Due to there is doubling technology on piece, EMCCD peripheral drive circuit is compared with common CCD, it is necessary to increase all the way
The high voltage multiplier signal of multiplication is controlled, multiplied signal generally uses the sine wave or square-wave signal for meeting certain phase condition, just
The uniformity of string peak voltage value and the stability influence picture quality of square wave high level.Fig. 5 is imaged for the EMCCD of E2V companies
Chip CCD201 multiplication factors and the relation of square wave high level, the approximate exponent function relation in 38V~48V is interval.EMCCD is imaged
Multiplication factor of the multiplier electrode of chip under normal temperature near 48V is about 800 times, and the relation of multiplication factor and voltage pulsation is about
4.8/10mV, it is 0.9DN/10mV to calculate the influence under the 5ms time of integration to image.Under non-doubling mode, 12 displays
Picture noise be about 6.4DN.Compared with the other noises of circuit, the fluctuation of multiplier electrode can not be such that circuit noise significantly increases
Plus.
In order to meet application of the EMCCD cameras in space industry, in addition to requiring above-mentioned multiplication stability, circuit function
On also to realize that teleinstruction sets the function of multiplication factor, while circuit will have miniaturization concurrently and the characteristics of low-power consumption, fixation
Multiplication and analog multiplication regulation can not meet use requirement.
The content of the invention
The technology of the present invention solves problem：Overcoming the deficiencies in the prior art, there is provided a kind of CNC high-pressure for EMCCD times
Increase circuit, meet multiplication stability, possess the characteristics of miniaturization and low-power consumption.
The present invention technical solution be：A kind of CNC high-pressure multiple circuit for EMCCD, including direct current flat turn
Change circuit, D/A converting circuit and push-pull driver circuit；
Low eight of the high sum-bit of the ten digits control signal of outside input is exported to DC level switching circuit respectively
And D/A converting circuit, DC level switching circuit is in the presence of the high two digits signal, by+the 56V of outside input
High voltage direct current flat turn turns to the high level of high pressure clock drive signals, exports to push-pull driver circuit；D/A converting circuit will
The low eight-digit number word signal changes into analog voltage, and push-pull drive electricity is given as the low level output of high pressure clock drive signals
Road；
Push-pull driver circuit carries out blocking to the clock signal of outside input, using the clock signal after blocking to direct current
The output level of flat change-over circuit carries out level conversion, and it is that 0V, high level are DC level switching circuit output to obtain low level
The square-wave signal of level, obtained square-wave signal and level that D/A converting circuit is exported is superimposed, obtain the drive of high pressure clock
Dynamic signal is simultaneously outwards exported.
Described DC level switching circuit includes diode D1, diode D2, DC level conversion chip U1, electric capacity
C1, electric capacity C2, electric capacity C3, resistance R1, resistance R2, resistance R3, resistance R4, FET Q1 and FET Q2；
DC level conversion chip U1 input and the+56V high voltage direct current flushconnections of outside input, direct current flat turn
Change the output level VDD that chip U1 output end is used to export DC level switching circuit；Diode D1 negative pole and direct current
Flat conversion chip U1 input connection, diode D1 positive pole is connected with DC level conversion chip U1 output end；
DC level conversion chip U1 adjustment end simultaneously with resistance R1 one end, resistance R2 one end, resistance R3 one
End and diode D2 positive pole connection, the resistance R2 other end are connected with FET Q2 drain electrode, FET Q2 source
Pole is grounded, and FET Q2 grid is connected with data signal D [1]；The resistance R1 other end connects with FET Q1 drain electrode
Connect, FET Q1 source electrode is connected with FET Q2 source electrode, FET Q1 grid is connected with data signal D [0]；
The resistance R3 other end is connected with FET Q2 source electrode；Diode D2 negative pole and DC level conversion chip U1 output
End connection, diode D2 positive pole be connected with electric capacity C2 one end and resistance R4 one end respectively, the electric capacity C2 other end and
FET Q2 source electrode connection；The output end and electric capacity C3 of the resistance R4 other end simultaneously with DC level conversion chip U1
One end connection, the electric capacity C3 other end is connected with FET Q2 source electrode；Electric capacity C1 is connected to DC level conversion chip
Between U1 input and FET Q1 source electrode；The data signal D [0] and D [1] represent the ten digits of outside input
Control signal it is high two.
The D/A converting circuit include electric capacity C4, electric capacity C5, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9,
Digital-to-analogue conversion device U2, operational amplifier U3, DC voltage V1；
Low eight connections of digital-to-analogue conversion device U2 input and the ten digits control signal of outside input, digital-to-analogue turns
Parallel operation part U2 output end is connected with resistance R5 one end, the resistance R5 other end respectively with resistance R6 one end and electric capacity C4
One end is connected, and the electric capacity C4 other end is connected with operational amplifier U3 output end, and on the one hand the resistance R6 other end passes through electricity
Hold C5 ground connection, on the other hand the in-phase input end with operational amplifier U3 is connected；Resistance R7 one end is with operational amplifier U3's
Output end is connected, resistance R7 other end inverting input on the one hand respectively with operational amplifier U3 and resistance R9 one end
Connection, is on the other hand grounded by resistance R8；The resistance R9 other ends are connected with DC voltage V1 anode, and DC voltage V1's is negative
End ground connection, the voltage that the DC voltage V1 is an externally input, operational amplifier U3 output end is used to export digital-to-analogue conversion electricity
The output level Vout on road.
The push-pull driver circuit includes diode D3, diode D4, diode D5, diode D6, diode D7, electric capacity
C6, electric capacity C7, electric capacity C8, electric capacity C9, electric capacity C10, FET Q3, FET Q4, resistance R10, resistance R11, resistance
R12, resistance R13 and resistance R14；
The output level VDD of DC level switching circuit is connected with diode D3 positive pole, diode D3 negative pole and two
Pole pipe D4 negative pole connection, diode D4 positive pole is connected with FET Q3 grid, FET Q3 source electrode and two poles
Pipe D3 positive pole connection, electric capacity C6 is connected between diode D3 positive pole and negative pole；FET Q3 drain electrode simultaneously with electricity
Hold C10 one end and FET Q4 drain electrode connection；On the one hand the electric capacity C10 other end is used to export push-pull driver circuit
High pressure clock drive signals R2HV, on the other hand the negative pole with diode D7 be connected, diode D7 positive pole and digital-to-analogue conversion
The output level Vout of circuit positive pole connection, the output level Vout of D/A converting circuit negative pole and FET Q4 source
Pole is connected；FET Q4 grid is connected with diode D6 negative pole, and diode D6 positive pole connects with diode D5 positive pole
Connect, diode D5 negative pole is grounded after being connected with FET Q4 source electrode；Electric capacity C7 is connected to diode D5 positive pole and born
Between pole；Resistance R12 connection diodes D5 positive pole and diode D3 negative pole；
Resistance R10 one end is connected with FET Q3 drain electrode, and the resistance R10 other end while with diode D4 just
The grid connection of pole, electric capacity C8 one end and FET Q3, the electric capacity C8 other end passes through resistance R11 and outside input
Clock signal is connected；Resistance R14 one end is connected with FET Q4 source electrode, and the resistance R14 other end is while and diode
The grid connection of D6 negative pole, electric capacity C9 one end and FET Q4, the electric capacity C9 other end pass through resistance R13 with it is outside
The clock signal connection of input.
The present invention has advantages below compared with prior art：
(1) present invention is changed using 10 bit digital quantities control multiplied clock signal high level in the range of 38~50V, is controlled
The quantization error of amount processed is equal toAbout 10mV, is linear close between control digital quantity and multiplied signal high level
System, is exponential relationship between multiplied signal high level and multiplication factor, and the degree of refinement of discrete control multiplication factor is better than 5/
DN。
(2) method of the invention by using DC voltage-stabilizing and LPF so that high voltage multiplier clock signal high level
Noise under normal temperature is about 35mV (oscillograph actual measurement is obtained).
(3) present invention realizes the functions such as input clock signal blocking, electric current driving, level superposition using discrete device,
Under 2.5M clock frequency, the power consumption of whole circuit is about 0.85W.
Brief description of the drawings
Fig. 1 is structured flowchart of the invention；
Fig. 2 is the schematic diagram of DC level switching circuit of the present invention；
Fig. 3 is the schematic diagram of D/A converting circuit of the present invention；
Fig. 4 is the schematic diagram of push-pull driver circuit of the present invention；
Fig. 5 is EMCCD chips multiplication factor and voltage, the relation of temperature；
Fig. 6 is the actual measurement signal output waveform of application example of the present invention.
Embodiment
The present invention is described in further detail with specific embodiment below in conjunction with the accompanying drawings：
As shown in figure 1, the present invention proposes a kind of CNC high-pressure multiple circuit for EMCCD, including direct current flat turn
Change circuit, D/A converting circuit and the part of push-pull driver circuit three.The input signal of circuit include 10 bit digital control signals and
Clock signal, output signal is high pressure clock drive signals, for driving EMCCD, at the same it is outside for the circuit provide+56V with+
5V two-way direct current supplys.The output of the high two control DC level switching circuit of digital controlled signal ,+56V high voltage direct currents
As the high level of high pressure clock drive signals after mean longitude DC level switching circuit, DC level switching circuit utilizes integrated steady
Volt circuit is realized, realizes the thick control to high pressure clock drive signals high level, and its output level has higher stability；It is low
Eight are converted into analog voltage through D/A converting circuit, then are used as high pressure clock to drive after active low pass filter filtering voltage regulation
The low level of dynamic signal, realizes and the essence of high pressure clock drive signals high level is controlled.The effect of push-pull driver circuit includes three
Part：To the clock signal blocking of input；Level conversion is carried out to push-pull circuit using the clock signal after blocking and electric current drives
It is dynamic；Complete the level superposition of low level and clock signal.Level conversion is carried out to push-pull circuit using the clock signal after blocking
(according to clock signal, the switching between low and high level is realized using FET Q3 and Q4) is driven with electric current, low level is obtained
For the square-wave signal that 0V, high level are DC level switching circuit output level, by obtained square-wave signal and digital-to-analogue conversion electricity
The level of road output is superimposed, obtains high pressure clock drive signals and outwards exports.There is push-pull driver circuit high power supply to suppress
Than influence of the power supply to the level equalization of output signal can be suppressed, push-pull driver circuit uses discrete device, full
Reduce power consumption on the basis of sufficient performance indications requirement.
The present invention can realize the function of discrete control multiplication factor, and circuit need to meet following requirements：The high pressure of output
Clock drive signals high level is adjustable in the range of 38V~50V, and low level is adjustable in the range of 0~3V, the high pressure clock of output
The rise time and fall time of drive signal are less than 15ns；The power consumption of circuit is less than 1W, high pressure clock drive signals high level
Noise be less than 50mV, meet EMCCD it is high-quality imaging for high pressure clock drive signals requirement.The present invention utilizes numeral control
The low and high level of signal processed control output square-wave signal can remotely located EMCCD multiplication factor, realize EMCCD in space industry
Application.
The schematic diagram of DC level switching circuit is as shown in Fig. 2 including diode D1, diode D2, DC level conversion
Chip U1 (model LM117), electric capacity C1, electric capacity C2, electric capacity C3, resistance R1, resistance R2, resistance R3, resistance R4, FET
Q1 and FET Q2；
U1 input and the+56V high voltage direct current flushconnections of outside input, DC level conversion chip U1 output end
Output level VDD for exporting DC level switching circuit；Diode D1 negative pole is defeated with DC level conversion chip U1's
Enter end connection, diode D1 positive pole is connected with DC level conversion chip U1 output end；
U1 adjustment end simultaneously with resistance R1 one end, resistance R2 one end, resistance R3 one end and diode D2
Positive pole is connected, and the resistance R2 other end is connected with FET Q2 drain electrode, FET Q2 source ground, FET Q2
Grid be connected with data signal D [1]；The resistance R1 other end is connected with FET Q1 drain electrode, FET Q1 source
Pole is connected with FET Q2 source electrode, and FET Q1 grid is connected with data signal D [0]；The resistance R3 other end with
FET Q2 source electrode connection；Diode D2 negative pole is connected with DC level conversion chip U1 output end, diode D2
Positive pole be connected respectively with electric capacity C2 one end and resistance R4 one end, the electric capacity C2 other end and FET Q2 source electrode
Connection；The resistance R4 other end is connected with DC level conversion chip U1 output end and electric capacity C3 one end simultaneously, electric capacity
The C3 other end is connected with FET Q2 source electrode；Electric capacity C1 is connected to DC level conversion chip U1 input and field is imitated
Should be between pipe Q1 source electrode；The data signal D [0] and D [1] represent the high by two of the ten digits control signal of outside input
Position.
The operation principle of DC level switching circuit is：The input signal of DC level switching circuit is+56V, is output as
U1 output voltage.Output voltage is determined that D [0] and D [1] control FET by high two D [0] of digital control amount and D [1]
Q1 and Q2 open and close, U1 output voltage values are met：
Vout=1.25 × (1+R/R4)+Iadj×R4 (1)
Wherein R is resistance R1~R3 parallel value, IadjFor the electric current of U1 adjustment ends, provided by device data handbook.Selection
Suitable resistance value R1~R4, make D [0] and D [1] for 00,01,10,11 when, U1 output voltage values be respectively 47V, 44V,
41V、38V.Diode D1 and D2 play overvoltage protection, it is to avoid U1 is damaged because backward voltage is excessive.Can by oscillograph observation
30mV is less than with the output valve noise for obtaining DC level switching circuit.The output signal of final DC level switching circuit for+
38~47V.
The schematic diagram of D/A converting circuit as shown in figure 3, including electric capacity C4, electric capacity C5, resistance R5, resistance R6, resistance R7,
Resistance R8, resistance R9, digital-to-analogue conversion device U2 (model AD558), operational amplifier U3 (model AD847), DC voltage
V1；
Low eight D [2 of digital-to-analogue conversion device U2 input and the ten digits control signal of outside input:9] connect,
Digital-to-analogue conversion device U2 output end is connected with resistance R5 one end, resistance R5 other end one end respectively with resistance R6 and electricity
Hold C4 one end connection, the electric capacity C4 other end is connected with operational amplifier U3 output end, and the resistance R6 other end is on the one hand
It is grounded by electric capacity C5, on the other hand the in-phase input end with operational amplifier U3 is connected；Resistance R7 one end and operation amplifier
Device U3 output end connection, the inverting input and resistance R9 of the resistance R7 other end on the one hand respectively with operational amplifier U3
One end connection, be on the other hand grounded by resistance R8；The resistance R9 other ends and V1 anode connection, V1 negativing ending grounding.Its
Middle electric capacity C4, electric capacity C5, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, operational amplifier U3 and V1 composition are active low
Bandpass filter.The voltage that DC voltage V1 is an externally input, operational amplifier U3 output end is used to export D/A converting circuit
Output level Vout.Digital-to-analogue conversion device U2 (model AD558) and operational amplifier U3 (model AD847) power supply electricity
Press as+5V direct current supplys.
The operation principle of D/A converting circuit is：Low eight Ds [2 of the digital-to-analogue conversion device U2 digital controlled signal:9] turn
Change analog signal into, signal voltage range is 0~2.5V.Active low-pass filter is used for the high frequency for eliminating d convertor circuit
Noise simultaneously improves driving force.The cut-off frequency of low pass filter is determined that EMCCD line synchronising signal is frequently by R5, R6, C4, C5
Rate is 2.5kHz, therefore the cut-off frequency selection of low pass filter is 2.5kHz.Low pass filter has amplification and voltage shifts concurrently
Function, regulation resistance R7~R9 can be set gain and the translation voltage of low pass filter, finally makes the output direct current of wave filter
Level is 1.5~4.5V.
The schematic diagram of push-pull driver circuit is as shown in figure 4, including diode D3, diode D4, diode D5, diode
D6, diode D7, electric capacity C6, electric capacity C7, electric capacity C8, electric capacity C9, electric capacity C10, FET Q3, FET Q4, resistance
R10, resistance R11, resistance R12, resistance R13 and resistance R14.
The output level VDD of DC level switching circuit is connected with diode D3 positive pole, diode D3 negative pole and two
Pole pipe D4 negative pole connection, diode D4 positive pole is connected with FET Q3 grid, FET Q3 source electrode and two poles
Pipe D3 positive pole connection, electric capacity C6 is connected between diode D3 positive pole and negative pole；FET Q3 drain electrode simultaneously with electricity
Hold C10 one end and FET Q4 drain electrode connection；On the one hand the electric capacity C10 other end is used to export push-pull driver circuit
High pressure clock drive signals R2HV, on the other hand the negative pole with diode D7 be connected, diode D7 positive pole and digital-to-analogue conversion
The output level Vout of circuit positive pole connection, the output level Vout of D/A converting circuit negative pole and FET Q4 source
Pole is connected；FET Q4 grid is connected with diode D6 negative pole, and diode D6 positive pole connects with diode D5 positive pole
Connect, diode D5 negative pole is grounded after being connected with FET Q4 source electrode；Electric capacity C7 is connected to diode D5 positive pole and born
Between pole；Resistance R12 connection diodes D5 positive pole and diode D3 negative pole；
Resistance R10 one end is connected with FET Q3 drain electrode, and the resistance R10 other end while with diode D4 just
The grid connection of pole, electric capacity C8 one end and FET Q3, the electric capacity C8 other end passes through resistance R11 and outside input
Clock signal is connected；Resistance R14 one end is connected with FET Q4 source electrode, and the resistance R14 other end is while and diode
The grid connection of D6 negative pole, electric capacity C9 one end and FET Q4, the electric capacity C9 other end pass through resistance R13 with it is outside
The clock signal connection of input.
The operation principle of push-pull driver circuit is：VDD is the output voltage of DC converting circuit, and magnitude of voltage is 38~47V.
Vout is the output voltage of D/A converting circuit.Q3 and Q4 are respectively the FET of p-type and N-type, when CLK_IN is high, Q3
Q4 is closed to open, on the contrary Q3 opens Q4 and closed (push-pull driver circuit realizes that level conversion and electric current drive by Q3 and Q4).
R11, R13, C8, C9 isolate the influence of CLK_IN DC levels, and direct current biasing is provided by D3~D6, R12.C10 and D7 are front end
Clock signal be superimposed with Vout level, output high pressure clock drive signals R2HV, D7 pressure drop is 1.5V, therefore and front end
The superimposed DC level of clock signal is 0~3V, the high level scope of the clock signal R2HV after superposition for 38~50V (i.e.
For the high voltage multiplier signal of output), realize the function by discrete control EMCCD multiplication factors.It can be obtained by emulation
Push-pull driver circuit is about 70dB in the PSRR of low-frequency range.
Through overtesting, the working effect for obtaining this example is：Discrete control EMCCD multiplication factors are realized, in 2.5M
Clock frequency under, rise time of output signal is 13ns, and fall time is 11ns, and the noise of high level is 35mV, to figure
The contribution (influence/image overall noise of the multiple circuit noise for image dark background noise) of picture dark background noise is 18%, after
The power consumption of circuit is 0.85W when end load is 10pF.Illustrate that circuit of the present invention meets the high-quality imaging use requirements of EMCCD.It is defeated
The waveform for going out signal is as shown in Figure 6.
The non-detailed description of the present invention is known to the skilled person technology.
Claims (4)
1. a kind of CNC high-pressure multiple circuit for EMCCD, it is characterised in that：Turn including DC level switching circuit, digital-to-analogue
Change circuit and push-pull driver circuit；
Low eight of the high sum-bit of the ten digits control signal of outside input is exported respectively gives DC level switching circuit sum
Analog conversion circuit, DC level switching circuit is in the presence of the high two digits signal, by+56V the high pressures of outside input
DC level is converted into the high level of high pressure clock drive signals, exports to push-pull driver circuit；D/A converting circuit will be described
Low eight-digit number word signal changes into analog voltage, as the low level output of high pressure clock drive signals to push-pull driver circuit；
Push-pull driver circuit carries out blocking to the clock signal of outside input, using the clock signal after blocking to direct current flat turn
The output level for changing circuit carries out level conversion, and it is that 0V, high level are DC level switching circuit output level to obtain low level
Square-wave signal, obtained square-wave signal and level that D/A converting circuit is exported is superimposed, obtain high pressure clock driving letter
Number and outwards export.
2. a kind of CNC high-pressure multiple circuit for EMCCD according to claim 1, it is characterised in that：Described is straight
Flow level shifting circuit include diode D1, diode D2, DC level conversion chip U1, electric capacity C1, electric capacity C2, electric capacity C3,
Resistance R1, resistance R2, resistance R3, resistance R4, FET Q1 and FET Q2；
DC level conversion chip U1 input and the+56V high voltage direct current flushconnections of outside input, DC level conversion core
Piece U1 output end is used for the output level VDD for exporting DC level switching circuit；Diode D1 negative pole and direct current flat turn
Chip U1 input connection is changed, diode D1 positive pole is connected with DC level conversion chip U1 output end；
DC level conversion chip U1 adjustment end simultaneously with one end of resistance R1 one end, resistance R2 one end, resistance R3 with
And diode D2 positive pole is connected, the resistance R2 other end is connected with FET Q2 drain electrode, and FET Q2 source electrode connects
Ground, FET Q2 grid is connected with data signal D [1]；The resistance R1 other end is connected with FET Q1 drain electrode, field
Effect pipe Q1 source electrode is connected with FET Q2 source electrode, and FET Q1 grid is connected with data signal D [0]；Resistance
The R3 other end is connected with FET Q2 source electrode；Diode D2 negative pole connects with DC level conversion chip U1 output end
Connect, diode D2 positive pole is connected with electric capacity C2 one end and resistance R4 one end respectively, electric capacity the C2 other end and field are imitated
Should pipe Q2 source electrode connection；The resistance R4 other end simultaneously with DC level conversion chip U1 output end and electric capacity C3 one
End connection, the electric capacity C3 other end is connected with FET Q2 source electrode；Electric capacity C1 is connected to DC level conversion chip U1's
Between input and FET Q1 source electrode；The data signal D [0] and D [1] represent the ten digits control of outside input
Signal it is high two.
3. a kind of CNC high-pressure multiple circuit for EMCCD according to claim 1, it is characterised in that：The digital-to-analogue
Change-over circuit include electric capacity C4, electric capacity C5, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, digital-to-analogue conversion device U2,
Operational amplifier U3, DC voltage V1；
Low eight connections of digital-to-analogue conversion device U2 input and the ten digits control signal of outside input, digital analog converter
Part U2 output end is connected with resistance R5 one end, the one end and electric capacity C4 one end of the resistance R5 other end respectively with resistance R6
Connection, the electric capacity C4 other end is connected with operational amplifier U3 output end, and on the one hand the resistance R6 other end passes through electric capacity C5
Ground connection, on the other hand the in-phase input end with operational amplifier U3 is connected；Resistance R7 one end and operational amplifier U3 output
On the one hand end connection, the resistance R7 other end connects with operational amplifier U3 inverting input and resistance R9 one end respectively
Connect, be on the other hand grounded by resistance R8；The resistance R9 other ends are connected with DC voltage V1 anode, DC voltage V1 negative terminal
Ground connection, the voltage that the DC voltage V1 is an externally input, operational amplifier U3 output end is used to export D/A converting circuit
Output level Vout.
4. a kind of CNC high-pressure multiple circuit for EMCCD according to claim 1, it is characterised in that：It is described to recommend
Drive circuit includes diode D3, diode D4, diode D5, diode D6, diode D7, electric capacity C6, electric capacity C7, electric capacity
C8, electric capacity C9, electric capacity C10, FET Q3, FET Q4, resistance R10, resistance R11, resistance R12, resistance R13 and resistance
R14；
The output level VDD of DC level switching circuit is connected with diode D3 positive pole, diode D3 negative pole and diode
D4 negative pole connection, diode D4 positive pole is connected with FET Q3 grid, FET Q3 source electrode and diode D3
Positive pole connection, electric capacity C6 is connected between diode D3 positive pole and negative pole；FET Q3 drain electrode simultaneously with electric capacity C10
One end and FET Q4 drain electrode connection；On the one hand the electric capacity C10 other end is used for the height for exporting push-pull driver circuit
Clock drive signals R2HV is pressed, on the other hand the negative pole with diode D7 is connected, diode D7 positive pole and D/A converting circuit
Output voltage Vout positive pole connection, the source electrode of the output voltage Vout of D/A converting circuit negative pole and FET Q4 connects
Connect；FET Q4 grid is connected with diode D6 negative pole, and diode D6 positive pole is connected with diode D5 positive pole, and two
Pole pipe D5 negative pole is grounded after being connected with FET Q4 source electrode；Electric capacity C7 be connected to diode D5 positive pole and negative pole it
Between；Resistance R12 connection diodes D5 positive pole and diode D3 negative pole；
Resistance R10 one end is connected with FET Q3 drain electrode, resistance R10 other end positive pole simultaneously with diode D4,
Electric capacity C8 one end and FET Q3 grid connection, the electric capacity C8 other end by resistance R11 and outside input when
Clock signal is connected；Resistance R14 one end is connected with FET Q4 source electrode, the resistance R14 other end simultaneously with diode D6
Negative pole, electric capacity C9 one end and FET Q4 grid connection, the electric capacity C9 other end is defeated by resistance R13 and outside
The clock signal connection entered.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510065348.3A CN104735370B (en) | 2015-02-06 | 2015-02-06 | A kind of CNC high-pressure multiple circuit for EMCCD |
Applications Claiming Priority (1)
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| CN201510065348.3A CN104735370B (en) | 2015-02-06 | 2015-02-06 | A kind of CNC high-pressure multiple circuit for EMCCD |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158658A (en) * | 2011-01-26 | 2011-08-17 | 中国科学院长春光学精密机械与物理研究所 | System for realizing peculiar driving signal of electron-multiplying charge coupled device (EMCCD) |
| CN102447849A (en) * | 2011-09-06 | 2012-05-09 | 中国科学院长春光学精密机械与物理研究所 | System for realizing EMCCD signal driving by high-voltage operational amplifier |
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| CN102158658A (en) * | 2011-01-26 | 2011-08-17 | 中国科学院长春光学精密机械与物理研究所 | System for realizing peculiar driving signal of electron-multiplying charge coupled device (EMCCD) |
| CN102447849A (en) * | 2011-09-06 | 2012-05-09 | 中国科学院长春光学精密机械与物理研究所 | System for realizing EMCCD signal driving by high-voltage operational amplifier |
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| Title |
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| 幅值可调的EMCCD倍增时钟驱动电路设计;陈苏广 等;《光电工程》;20120430;第39卷(第4期);第145-150页 * |
| 空间EMCCD成像系统中倍增高压时钟驱动设计;谢宗宝 等;《科学技术与工程》;20110630;第11卷(第17期);第3946-3950页 * |
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