CN104735010B - Ofdm system receiving terminal determines the device of sync bit - Google Patents
Ofdm system receiving terminal determines the device of sync bit Download PDFInfo
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- CN104735010B CN104735010B CN201310723400.0A CN201310723400A CN104735010B CN 104735010 B CN104735010 B CN 104735010B CN 201310723400 A CN201310723400 A CN 201310723400A CN 104735010 B CN104735010 B CN 104735010B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
Abstract
The invention discloses the device that a kind of ofdm system receiving terminal determines sync bit, including channel time domain impulse response modulus value register, the first accumulator, the second accumulator, comparator；Channel time domain impulse response modulus value register is used for the modulus value for storing channel time domain impulse response | h (i) |；First accumulator, initial value 0, then progressively adds up | h (j) | value；Second accumulator, initial value be | h (Ncp) |+| h (Ncp+1) |+...+| h (L 1) |, then progressively subtract | h (Ncp+j) | value；Comparator, to each j, compare the first accumulator currency, the currency of the second accumulator, export sync bit；L is the length of channel time domain impulse response, and Ncp is cyclic-redundancy prefix length, and L is more than Ncp；I is from 0 to L 1 integer；J is the integer of 1 Ncp from 0 to L.The ofdm system receiving terminal of the present invention determines the device of sync bit, and the minimum sync bits of ISI can be provided under long time delay channel circumstance.
Description
Technical field
The present invention relates to digital communication technology, the dress of sync bit is determined more particularly to a kind of ofdm system receiving terminal
Put.
Background technology
It is well known that in OFDM (Orthogonal frequency-division multiplexing, orthogonal frequency division multiplexing
With) in system, generally use CP (cyclic-redundancy prefix) resists ISI (intersymbol interference).When channel delay spread is (to coordinate
Contextual declaration is convenient, is designated as D here) no more than CP length (to coordinate contextual declaration convenient, being designated as Ncp here) when, together
Step, which is put, chooses first path position, and can ensure no any ISI (intersymbol interference), as shown in Figure 1.
But because ground-based wireless transmissions environment is complicated and changeable（Especially in city）, having through multihop propagation can
Long delay multipath can be introduced.More importantly in such as CMMB（China Mobile Multimedia Broadcasting, in
State's mobile multimedia broadcast television system）In, because being arranged net using SFN (SFN) mode, along with numerous benefit points is launched
Stand, receiver may receive the signal from multiple cell sites or repeater station simultaneously, and these cell sites or repeater station distance connect
Receipts machine is far and near different along with repeater station inevitably brings extra latency so that channel delay is very big.It is all these
Factor can cause channel delay spread D to be likely to be greater than CP length Ncp.
In this case, if still continuing to use traditional method of synchronization for taking first path position, as Fig. 2 shows, it is more likely that
The bigger multipath of some stronger delay spreads (such as h (L-1) in figure) is placed in outside Ncp scopes, thus bring compared with
Strong ISI (intersymbol interference).But if we are according to sync bit is taken as shown in Figure 3, because h (0) is relative to h (L-1)
It is weaker, therefore the ISI brought is with regard to small, therefore be a kind of more excellent method of synchronization.In order to calculate such a ISI minimums
Sync bit, this just needs a kind of long time delay channel circumstance（Channel delay spread length D is more than cyclic-redundancy prefix length Ncp）
The lower device for determining sync bit.
The content of the invention
, can be the technical problem to be solved in the present invention is to provide the device that a kind of ofdm system receiving terminal determines sync bit
Under long time delay channel circumstance the minimum sync bits of ISI (intersymbol interference) are provided for follow-up OFDM data receiving module.
In order to solve the above technical problems, ofdm system receiving terminal provided by the invention determines the device of sync bit, including
Channel time domain impulse response modulus value register, the first accumulator, the second accumulator, comparator；
The channel time domain impulse response modulus value register, for storing channel time domain impulse response h (i) modulus value | h
(i)|；The content of channel time domain impulse response modulus value register | h (i) | the input as the first accumulator, the second accumulator；
First accumulator, initial value 0, then progressively adds up | h (j) | value, the currency C1 of the first accumulator
(j) input as comparator below；
Second accumulator, initial value be | h (Ncp) |+| h (Ncp+1) |+...+| h (L-1) |, then progressively subtract |
H (Ncp+j) | value, the input of the currency C2 (j) of the second accumulator as comparator below；
The comparator, to each j, compare the first accumulator currency C1 (j), the currency C2 (j) of the second accumulator,
Export sync bit；
L is the length of channel time domain impulse response, and Ncp is cyclic-redundancy prefix length, and L is more than Ncp；
I is the integer from 0 to L-1；
J is position instruction variable, and j is the integer from 0 to L-1-Ncp.
Preferably, channel time domain impulse response h (i), is obtained by coarse channel estimation module.
Preferably, ofdm system receiving terminal determines that the course of work of the device of sync bit comprises the following steps：
First, the value of the first accumulator and the second accumulator is initialized, the initial value C1 (0)=0 of the first accumulator, second is tired
Add the initial value C2 (0) of device=| h (Ncp) |+| h (Ncp+1) |+...+| h (L-1) |, make j=0；
2nd, channel time domain impulse response modulus value register is taken out to be worth for j-th | h (j) |, it is added in the first accumulator, i.e.,
C1(j+1)=C1(j)+|h(j)|；
Take out channel time domain impulse response modulus value register (Ncp+j) individual value | h (Ncp+j) |, and from the second accumulator
Subtract this value in currency, i.e. C2 (j+1)=C2 (j)-| h (Ncp+j) |；
3rd, C1 (j+1) and C2 (j+1) value are compared, if C1 (j+1) >=C2 (j+1), exports j-th of channel time domain
Position corresponding to impulse response h (j) is sync bit, is terminated；Otherwise from adding 1, i.e. j=j+1, rebound walks position instruction variable j
Rapid two.
Preferably, ofdm system is China Mobile Multimedia Broadcasting television system, the length L of channel time domain impulse response is
2048, the synchronizing sequence that channel time domain impulse response is started by each time slot obtains, the deposit of channel time domain impulse response modulus value
2048 values of storage coexist in device, and cyclic-redundancy prefix length Ncp is 512.
The ofdm system receiving terminal of the present invention determines the device of sync bit, can be in long time delay channel circumstance（During channel
Prolong extension length D and be more than cyclic-redundancy prefix length Ncp）Under, providing ISI for follow-up OFDM data receiving module, (intersymbol is done
Disturb) minimum sync bit；It is not only applicable to CMMB（China Mobile Multimedia Broadcasting, China
Mobile multimedia broadcast television system）Reception system, as long as employing the digit wireless communication system of OFDM technology, connecing
Receiving end can synchronize location estimation with the present invention.
Brief description of the drawings
In order to illustrate more clearly of technical scheme, the accompanying drawing used required for the present invention is made below simple
Introduce, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for ordinary skill people
For member, on the premise of not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is that the sync bit when channel delay spread length is not more than cyclic-redundancy prefix length chooses schematic diagram；
Fig. 2 is when channel delay spread length is more than cyclic-redundancy prefix length, using conventional synchronization position selection side
Formula schematic diagram；
Fig. 3 is when channel delay spread length is more than cyclic-redundancy prefix length, is selected using the sync bit of the present invention
Take schematic diagram；
Fig. 4 is that the ofdm system receiving terminal of the present invention determines the embodiment schematic diagram of device one of sync bit；
The ofdm system receiving terminal that Fig. 5 is the present invention determines the device of a sync bit example structure in CMMB system
Figure.
Embodiment
Below in conjunction with accompanying drawing, clear, complete description is carried out to the technical scheme in the present invention, it is clear that described
Embodiment is the part of the embodiment of the present invention, rather than whole embodiments.It is general based on the embodiment in the present invention, this area
All other embodiment that logical technical staff is obtained on the premise of creative work is not made, belongs to protection of the present invention
Scope.
Embodiment one
Ofdm system receiving terminal determines the device of sync bit, as shown in figure 4, being posted including channel time domain impulse response modulus value
Storage, the first accumulator, the second accumulator, comparator；
The channel time domain impulse response modulus value register, for storing channel time domain impulse response h (i) modulus value | h
(i)|；The content of channel time domain impulse response modulus value register | h (i) | the input as the first accumulator, the second accumulator；i
For the integer from 0 to L-1, j is position instruction variable, and j is the integer from 0 to L-1-Ncp；L is channel time domain impulse response
Length, Ncp are cyclic-redundancy prefix length, and L is more than Ncp；
First accumulator, initial value 0, then progressively adds up | h (j) | value, the currency C1 of the first accumulator
(j) input as comparator below；
Second accumulator, initial value be | h (Ncp) |+| h (Ncp+1) |+...+| h (L-1) |, then progressively subtract |
H (Ncp+j) | value, the input of the currency C2 (j) of the second accumulator as comparator below；
The comparator, to each j, compare the first accumulator currency C1 (j), the currency C2 (j) of the second accumulator,
Export sync bit.
Preferably, channel time domain impulse response h (i), by other modules（Such as coarse channel estimation module）Obtain.
The ofdm system receiving terminal of embodiment one determines the device of sync bit, can be in long time delay channel circumstance（Channel
Delay spread length D is more than cyclic-redundancy prefix length Ncp）Under, provide ISI (intersymbols for follow-up OFDM data receiving module
Interference) minimum sync bit；It is not only applicable to CMMB（China Mobile Multimedia Broadcasting, in
State's mobile multimedia broadcast television system）Reception system, as long as employ the digit wireless communication system of OFDM technology,
Receiving terminal can synchronize location estimation with the present invention.
Embodiment two
Ofdm system receiving terminal based on embodiment one determines the device of sync bit, and its course of work includes following step
Suddenly：
First, the value of the first accumulator and the second accumulator is initialized, the initial value C1 (0)=0 of the first accumulator, second is tired
Add the initial value C2 (0) of device=| h (Ncp) |+| h (Ncp+1) |+...+| h (L-1) |, make j=0；
2nd, channel time domain impulse response modulus value register is taken out to be worth for j-th | h (j) |, it is added in the first accumulator, i.e.,
C1(j+1)=C1(j)+|h(j)|；
Take out channel time domain impulse response modulus value register (Ncp+j) individual value | h (Ncp+j) |, and from the second accumulator
Subtract this value in currency, i.e. C2 (j+1)=C2 (j)-| h (Ncp+j) |；
3rd, C1 (j+1) and C2 (j+1) value are compared, if C1 (j+1)>=C2 (j+1), then export j-th of channel time domain
Position corresponding to impulse response h (j) is sync bit, is terminated；Otherwise from adding 1, i.e. j=j+1, rebound walks position instruction variable j
Rapid two.
Embodiment three
Ofdm system receiving terminal based on embodiment one determines the device of sync bit, ofdm system CMMB（China
Mobile Multimedia Broadcasting, China Mobile Multimedia Broadcasting television system）, channel time domain impulse response
Length L is 2048, and channel time domain impulse response can be obtained by the synchronizing sequence that each time slot starts, therefore channel time domain rushes
Swash response modulus value register and 2048 values of storage coexist, i.e., | h (i) | (i=0,1,2...2047), in CMMB system, cyclic redundancy
Prefix length Ncp is fixed as 512.Ofdm system receiving terminal determines that the course of work of the device of sync bit is as follows：
First, the value of the first accumulator and the second accumulator is initialized, the initial value C1 (0)=0 of the first accumulator, second is tired
Add the initial value C2 (0) of device=| h (512) |+| h (513) |+...+| h (2047) |, make j=0；
2nd, channel time domain impulse response modulus value register is taken out to be worth for j-th | h (j) |, it is added in the first accumulator, i.e.,
C1(j+1)=C1(j)+|h(j)|；
Take out channel time domain impulse response modulus value register (512+j) individual value | h (512+j) |, and from the second accumulator
Subtract this value in currency, i.e. C2 (j+1)=C2 (j)-| h (512+j) |；
3rd, C1 (j+1) and C2 (j+1) value are compared, if C1 (j+1)>=C2 (j+1), then export j-th of channel time domain
Position corresponding to impulse response h (j) is sync bit, is terminated；Otherwise from adding 1, i.e. j=j+1, rebound walks position instruction variable j
Rapid two.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
God any modification, equivalent substitution and improvements done etc., should be included within the scope of protection of the invention with principle.
Claims (4)
1. a kind of ofdm system receiving terminal determines the device of sync bit, it is characterised in that including channel time domain impulse response mould
Value register, the first accumulator, the second accumulator, comparator；
The channel time domain impulse response modulus value register, for storing channel time domain impulse response h (i) modulus value | h (i) |；
The content of channel time domain impulse response modulus value register | h (i) | the input as the first accumulator, the second accumulator；
First accumulator, initial value 0, then progressively adds up | h (j) | value, the currency C1 (j) of the first accumulator makees
For the input of comparator below；
Second accumulator, initial value be | h (Ncp) |+| h (Ncp+1) |+...+| h (L-1) |, then progressively subtract | h
(Ncp+j) | value, the input of the currency C2 (j) of the second accumulator as comparator below；
The comparator, to each j, compare the first accumulator currency C1 (j), the currency C2 (j) of the second accumulator, export
Sync bit；
L is the length of channel time domain impulse response, and Ncp is cyclic-redundancy prefix length, and L is more than Ncp；
I is the integer from 0 to L-1；
J is position instruction variable, and j is the integer from 0 to L-1-Ncp.
2. ofdm system receiving terminal according to claim 1 determines the device of sync bit, it is characterised in that
Channel time domain impulse response h (i), obtained by coarse channel estimation module.
3. ofdm system receiving terminal according to claim 2 determines the device of sync bit, it is characterised in that
Ofdm system receiving terminal determines that the course of work of the device of sync bit comprises the following steps：
First, the value of the first accumulator and the second accumulator, the initial value C1 (0)=0 of the first accumulator, the second accumulator are initialized
Initial value C2 (0)=| h (Ncp) |+| h (Ncp+1) |+...+| h (L-1) |, make j=0；
2nd, channel time domain impulse response modulus value register is taken out to be worth for j-th | h (j) |, it is added in the first accumulator, i.e. C1 (j+
1)=C1(j)+|h(j)|；
Take out channel time domain impulse response modulus value register (Ncp+j) individual value | h (Ncp+j) |, and it is current from the second accumulator
Subtract this value in value, i.e. C2 (j+1)=C2 (j)-| h (Ncp+j) |；
3rd, C1 (j+1) and C2 (j+1) value are compared, if C1 (j+1) >=C2 (j+1), exports j-th of channel time domain impulse
The position responded corresponding to h (j) is sync bit, is terminated；Otherwise position instruction variable j from plus 1, i.e. j=j+1, rebound step
Two.
4. the ofdm system receiving terminal according to claim 1,2 or 3 determines the device of sync bit, it is characterised in that
Ofdm system is China Mobile Multimedia Broadcasting television system, and the length L of channel time domain impulse response is 2048, during channel
The synchronizing sequence that domain impulse response is started by each time slot obtains, and storage 2048 coexists in channel time domain impulse response modulus value register
Individual value, cyclic-redundancy prefix length Ncp are 512.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW200402221A (en) * | 2002-07-19 | 2004-02-01 | Mediatek Inc | Method and apparatus for frequency synchronization in a digital transmission system |
| US7974329B2 (en) * | 2006-10-26 | 2011-07-05 | Qualcomm, Incorporated | Method and apparatus for timing estimation in a wireless communications system |
| CN102594758A (en) * | 2011-01-11 | 2012-07-18 | 上海华虹集成电路有限责任公司 | Synchronous estimating device and synchronous estimating method for fine timing |
| CN102594757A (en) * | 2011-01-11 | 2012-07-18 | 上海华虹集成电路有限责任公司 | Synchronous estimating device and synchronous estimating method for coarse timing and fine timing |
| CN102611665A (en) * | 2011-01-24 | 2012-07-25 | 上海华虹集成电路有限责任公司 | Method and device for combined estimation of integer frequency offset and fine timing in CMMB (China mobile multimedia broadcasting) system |
-
2013
- 2013-12-24 CN CN201310723400.0A patent/CN104735010B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200402221A (en) * | 2002-07-19 | 2004-02-01 | Mediatek Inc | Method and apparatus for frequency synchronization in a digital transmission system |
| US7974329B2 (en) * | 2006-10-26 | 2011-07-05 | Qualcomm, Incorporated | Method and apparatus for timing estimation in a wireless communications system |
| CN102594758A (en) * | 2011-01-11 | 2012-07-18 | 上海华虹集成电路有限责任公司 | Synchronous estimating device and synchronous estimating method for fine timing |
| CN102594757A (en) * | 2011-01-11 | 2012-07-18 | 上海华虹集成电路有限责任公司 | Synchronous estimating device and synchronous estimating method for coarse timing and fine timing |
| CN102611665A (en) * | 2011-01-24 | 2012-07-25 | 上海华虹集成电路有限责任公司 | Method and device for combined estimation of integer frequency offset and fine timing in CMMB (China mobile multimedia broadcasting) system |
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Effective date of registration: 20151111 Address after: 214072 Jiangsu province Wuxi Liyuan Development Zone Hubin District 530 Building 1 room 1203 No. twelve Applicant after: JIANGSU MAXSCEND TECHNOLOGY CO., LTD. Address before: 201203, room 50, 202 Xia Xia Road, Shanghai, Pudong New Area Applicant before: Maxscend Technologies Inc. |
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Address after: 214072 Jiangsu province Wuxi Liyuan Development Zone Hubin District 530 Building 1 room 1203 No. twelve Applicant after: Jiangsu Zhuo Sheng microelectronics Limited by Share Ltd Address before: 214072 Jiangsu province Wuxi Liyuan Development Zone Hubin District 530 Building 1 room 1203 No. twelve Applicant before: JIANGSU MAXSCEND TECHNOLOGY CO., LTD. |
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