CN104733537B - Thin film transistor (TFT) and manufacturing method and its organic LED display device - Google Patents
Thin film transistor (TFT) and manufacturing method and its organic LED display device Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 55
- 239000002184 metal Substances 0.000 claims abstract description 55
- 239000012212 insulator Substances 0.000 claims abstract description 18
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 174
- 239000010408 film Substances 0.000 claims description 25
- 239000011229 interlayer Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 19
- 150000002500 ions Chemical class 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 239000000758 substrate Substances 0.000 description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 description 10
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- 238000005229 chemical vapour deposition Methods 0.000 description 6
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
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- 239000012535 impurity Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229920001621 AMOLED Polymers 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000003863 metallic catalyst Substances 0.000 description 4
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- 238000000137 annealing Methods 0.000 description 2
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- 230000003287 optical effect Effects 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
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- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
- H01L29/78615—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect with a body contact
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The present invention provides a kind of thin film transistor (TFT) and manufacturing method and its organic LED display device, including the first semiconductor layer, the second semiconductor layer being deposited on the first semiconductor layer, gate metal layer positioned at the gate insulator of the second semiconductor layer and above gate insulator, second semiconductor layer forms source region, drain region and the channel region between source region and drain region, first semiconductor layer is located at the lower section in the source region or drain region, and the covering for extending the second semiconductor layer forms body contact zone, the body contact zone can be electrically connected with source region or gate metal layer formation.So set, it can effectively inhibit floater effect.
Description
Technical field
The present invention relates to display technology field more particularly to a kind of thin film transistor (TFT) and manufacturing method and its organic light emissions two
Pole pipe display device.
Background technology
Organic Light Emitting Diode (OLED) display device is a kind of active luminescent device, compared to present mainstream FPD
Technique film transistor liquid crystal display (TFT-LCD) (TFT-LCD), OLED have a high contrast, wide viewing angle, low-power consumption, and volume is thinner etc. excellent
Point is expected to become the next-generation flat panel display after LCD, is most skill that attracts attention in current flat panel display
It is aobvious to be especially suitable for large-sized active matrix organic light-emitting diode (Active Matr ix OLED, AMOLED) for one of art
Showing device.Since OLED has driving current larger demand, and traditional non-crystalline silicon (a-Si) semiconductor is moved due to field-effect
Shifting rate is relatively low so that the polysilicon (poly-Si) with high mobility is widely used as the semiconductor layer of thin film transistor (TFT).
Under polysilicon (poly-Si) thin film transistor (TFT) (TFT) raceway groove used on AMOLED display device array substrate
The neutral body area of side is generally in electricity floating (float ing) state, this can generate floater effect (float ing body
Effect), cause TFT deterioration in characteristics, influence the display effect of AMOLED.
In order to solve the problems, such as this, body contact (body contact) structure is a kind of method being widely adopted.Compare often
It is T-shaped grid and H-type grid structure, and forms the body contact zone individually extended being connected with gate electrode in the semiconductor layer.
However, the technology can cause thin film transistor (TFT) area to increase, and cannot have due to the presence of polysilicon (poly-Si) bulk resistor
Effect inhibits floater effect, and raceway groove gets over that expanded letter polysilicon (poly-Si) resistance is bigger, and floater effect is more notable.
Therefore, in view of the above-mentioned problems, it is necessary to design a kind of thin film transistor (TFT) of improvement and manufacturing method and its organic hair
Optical diode display device is to overcome drawbacks described above.
The content of the invention
It is an object of the invention to provide a kind of thin film transistor (TFT) that can effectively inhibit floater effect and manufacturing method and its
Organic LED display device.
To realize object defined above, the present invention adopts the following technical scheme that：
A kind of thin film transistor (TFT) the second half is led including the first semiconductor layer, deposition Chong Die with the first semiconductor layer part
Body layer, the gate metal layer positioned at the gate insulator of the second semiconductor layer and above gate insulator, it is described
Second semiconductor layer forms source region, drain region and the channel region between source region and drain region, first semiconductor layer and is located at
The source region or the lower section in drain region, and the covering for extending the second semiconductor layer forms body contact zone, the body contact zone can be with
Source region or gate metal layer form electrical connection.
As further optimization, first semiconductor layer is located at the lower section of the source region, in the gate metal layer
Interlayer insulating film is formed, the interlayer insulating film covers on the gate insulating layer simultaneously, and the interlayer insulating film is equipped with
Contact hole corresponding with the source region and drain region and it is filled in be electrically connected respectively with source region and drain region in contact hole second respectively
Metal layer.
As further optimization, the body contact zone passes through the second metal layer in the contact hole that is shared with source region and source
Area forms electrical connection.
As further optimization, the interlayer insulating film is individually contacted equipped with corresponding with the body contact zone position
Hole and the second metal layer being electrically connected with body contact zone in the independent contact hole is filled in, the body contact zone passes through the list
Second metal layer in only contact hole is electrically connected with gate metal layer.
Following technical solution also can be used in the present invention：
A kind of manufacturing method of thin film transistor (TFT), includes the following steps：
Form the first semiconductor layer；
The second semiconductor layer is formed on first semiconductor layer, and part exposes first semiconductor layer to be formed
Body contact zone, second semiconductor layer include source region, drain region and the channel region between source region and drain region, the source region
Above body contact zone, the body contact zone extends along the length direction of channel region, and the body contact zone can be formed with source region
Electrical connection；
Gate insulator is formed on second semiconductor layer；
Subregion forms gate metal layer on the gate insulating layer.
As further optimization, the method further includes following steps：
Interlayer insulating film is formed in gate metal layer, the interlayer insulating film is covered in the gate insulator simultaneously
On, contact hole corresponding with the source region and drain region position respectively is set on the interlayer insulating film；
Second metal layer is formed further on interlayer insulating film, the second metal layer enters the contact hole and shape
Into source electrode and drain electrode, the body contact zone extends along the length direction of channel region.
As further optimization, the body contact zone passes through the second metal layer in the contact hole that is shared with source region and source
Area forms electrical connection.
Following technical solution also can be used in the present invention：
A kind of organic LED display device, including：
First semiconductor layer；
Second semiconductor layer, second semiconductor layer are arranged on first semiconductor layer, and described in the exposure of part
First semiconductor layer to form body contact zone, second semiconductor layer include source region, drain region and positioned at source region and drain region it
Between channel region, the source region is located above body contact zone, and the body contact zone can be formed with source region and is electrically connected；
Gate insulator is arranged on second semiconductor layer；
Gate metal layer, arrangement is on the gate insulating layer；
Source electrode and drain electrode, the source electrode and drain electrode are electrically connected respectively with the source region and drain region；
One of first pixel electrode, first pixel electrode and the source electrode or drain electrode are connected；
Organic Light Emitting Diode layer, the Organic Light Emitting Diode layer arrangement is on the first pixel electrode；
Second pixel electrode is arranged on the Organic Light Emitting Diode layer.
As further optimization, interlayer insulating film is additionally provided in the gate metal layer, the interlayer insulating film is simultaneously
Covering on the gate insulating layer, the interlayer insulating film be equipped with respectively contact hole corresponding with the source region and drain region and
It is filled in the second metal layer being electrically connected respectively with source region and drain region in contact hole.
As further optimization, the body contact zone passes through the second metal layer in the contact hole that is shared with source region and source
Area forms electrical connection.
The present invention in thin film transistor (TFT) by setting first, second semiconductor layer, two layers of semiconductor layer, and along channel length
Direction, being formed has body contact structure, can improve the electrology characteristic of TFT, and poly-Si bulk resistors can be avoided to influence, can be effective
Inhibit floater effect, while the area of TFT will not be dramatically increased.
Description of the drawings
Figure 1A is the plan view of the method first step of present invention manufacture TFT；
Figure 1B is the sectional view intercepted along the line I-I of Figure 1A；
Fig. 2A is the plan view of the method second step of present invention manufacture TFT；
Fig. 2 B are the sectional view intercepted along the line II-II of Fig. 2A；
Fig. 3 A are the plan view of the 3rd step of method of present invention manufacture TFT；
Fig. 3 B are the sectional view intercepted along the line III-III of Fig. 3 A；
Fig. 4 A are the plan view of the 4th step of method of present invention manufacture TFT；
Fig. 4 B are the sectional view intercepted along the line IV-IV of Fig. 4 A；
Fig. 5 A are the plan view of the 5th step of method of present invention manufacture TFT；
Fig. 5 B are the sectional view intercepted along the line V-V of Fig. 5 A；
Fig. 6 is the sectional view of organic LED display device of the present invention.
Specific embodiment
Figure 1A be show it is according to an exemplary embodiment of the present invention manufacture TFT the method first step plan view, Tu1BWei
The sectional view intercepted along the line I-I of Figure 1A.Referring to Figure 1A and 1B, a substrate 1 is provided, which is formed by glass or plastics,
Buffer layer 2 is formed on substrate 1, the buffer layer 2 is formed on substrate 1 by way of chemical vapor deposition (CVD).Buffer layer
2 effect is to prevent the heat transfer efficiency of aqueous vapor or impurity diffusion into semiconductor layer or during control crystallization in substrate from making
The crystallization for obtaining semiconductor layer is easier, and wherein semiconductor layer will be formed in lower column processing.The buffer layer 2 can be single
Layer or be made of plural layers.
Then, the first amorphous silicon layer is formed on the buffer layer 2.Here can be formed by chemical vapor deposition (CVD), and
And foreign ion is mixed in deposition process, impurity concentration is preferably 1 × 1019/ cm3It is more than magnitude.Then to the first amorphous
Silicon layer is patterned, so as to form 1 × 1019/ cm3First semiconductor layer 3.First semiconductor layer, 3 thickness is preferably
Between 50nm to 100nm.
Fig. 2A is the plan view for the method second step for showing manufacture TFT according to an exemplary embodiment of the present invention, and Fig. 2 B are
The sectional view intercepted along the line II-II of Fig. 2A.Second amorphous silicon layer is formed by chemical vapor deposition (CVD), thickness is preferably
For between 50nm to 100nm.Dehydrogenation can be carried out to it after non-crystalline silicon is formed herein, it is former to reduce hydrogen in amorphous silicon membrane
The content of son.Then the second amorphous silicon layer is crystallized, it is made to be converted into polysilicon layer.The method of crystallization is included but not
It is limited to crystallization inducing metal (MIC), metal induced lateral crystallization (MILC), super grain silicon (SGS, Super Grained
Silicon) or quasi-molecule laser annealing (ELA, Excimer Laser Anneal) crystallizes etc..MIC is a kind of all by contacting
Amorphous silicon layer is induced to more such as the metallic catalyst of nickel, palladium or aluminium etc or by injecting metallic catalyst in amorphous silicon layer
The method that crystal silicon layer carries out phase transformation.MI LC are a kind of horizontal strokes of generated silicide in reaction by metallic catalyst and silicon
To diffusion, the continuous crystal of amorphous silicon layer to be induced to turn to polysilicon layer method.SGS is one kind by forming silica, silicon nitride
Or the cap rock of the composition of silica and silicon nitride to be to control metallic catalyst to spread or permeate into amorphous silicon layer, by amorphous
The method that silicon layer turns to the polysilicon layer with large-size crystal grain.ELA crystallizations are the high temperature generated using laser, make non-crystalline silicon
Silicon atom is rearranged after melting, forms a kind of method of polysilicon.ELA crystallizes the polysilicon to be formed with higher
Mobility is currently used method.Different size of polysilicon grain can be formed by the energy for controlling laser.
Next, by being patterned to form the second semiconductor layer 4,4 figure of the second semiconductor layer to polysilicon layer
Case needs part the first semiconductor layer 3 of exposure to form the electrical connection of body contact zone 31 by subsequent technique.That is, described the second half lead
Body layer 4 and first semiconductor layer 3 partly overlap deposition.Hereafter, impurity can be mixed to the second semiconductor layer 4, adjusts TFT
Electrology characteristic, with meet design requirement.Doping can use ion implanting (ion implant) or ion doping (ion
) etc. doping modes realize that foreign ion can be N-type (such as P, As) or p-type (such as B, BF3), and impurity concentration is about
For 1 × 1019/ cm3Magnitude.
Fig. 3 A are the plan view for the 3rd step of method for showing manufacture TFT according to an exemplary embodiment of the present invention, and Fig. 3 B are
The sectional view intercepted along the line III-III of Fig. 3 A.Gate insulator 5 is formed on substrate 1, and covers whole face substrate 1.Grid
Insulating layer 5 can be formed by silica or other insulating materials.Gate metal layer 6 is further formed on gate insulator 5.Grid
Pole metal layer 6 can be formed by physical vapour deposition (PVD) (PVD) mode, and material can be aluminium (A1), molybdenum (Mo) or other metals or conjunction
Gold.Gate metal layer 6 can be the lamination of individual layer or multilayer material.6 figure of gate metal layer is made by photoetching and etching
Case, and then form gate electrode, conducting wire and other functional graphics.It is then possible to which gate metallic pattern is hard mask, pass through ion
Doping or ion implanting form source region 41, drain region 42 and between source region 41 and drain region 42 in the second semiconductor layer 4
Channel region (non-label).Line among the source region 41, drain region 42 is the width of channel region, perpendicular to the source region
41st, the direction of the line among drain region 42 is the length direction of channel region.First semiconductor layer 3 be located at the source region 41 or
Simultaneously extend the covering of the second semiconductor layer 4 and form body contact zone 31 in the lower section in drain region 42.So set, the electricity of TFT can be improved
Characteristic is learned, poly-Si bulk resistors can be avoided to influence, can effectively inhibit floater effect, while the face of TFT will not be dramatically increased
Product.In the present embodiment, the body contact zone 31 is located at 41 lower section of source region.That is the first semiconductor layer 3 and the second semiconductor layer 4
Partly overlap deposition in 41 position of source region, in other embodiments, the body contact zone that first semiconductor layer 3 is formed
31 may be located on the lower section in drain region 42, and extend the covering of the second semiconductor layer 4.By corresponding structure design, such as
Make to be formed between the body contact zone 31 and gate metal layer 6 and be electrically connected, poly-Si bulk resistors can equally be avoided to influence, it can
Effectively inhibit floater effect, while the area of TFT will not be dramatically increased.The ion concentration that source region 41 and drain region 42 are adulterated can be appropriate
Less than the impurity concentration of body contact zone 31, and the foreign ion and the first semiconductor layer 3 that above-mentioned source region 41 and drain region 42 mix
The type that foreign ion is mixed in deposition process is different.Specifically, length direction of first semiconductor layer 3 along channel region
Extension, first semiconductor layer 3 are located at the lower section of the source region 41 or drain region 42 and along the width of channel region to separate raceway groove
Extend the covering of the second semiconductor layer 4 in area.So set, can make body contact zone 31 that can extend along the length direction of channel region,
The electrology characteristic for improving TFT can be better achieved in width extension compared to body contact zone 31 along channel region, avoid
Poly-Si bulk resistors influence, and inhibit floater effect, while will not dramatically increase the area of TFT.
Fig. 4 A are the plan view for the 4th step of method for showing manufacture TFT according to an exemplary embodiment of the present invention, and Fig. 4 B are
The sectional view intercepted along the line IV-IV of Fig. 4 A.Interlayer insulating film 7 is further formed on substrate 1, and the interlayer insulating film 7 can
It is made of silica or other insulating materials.By photoetching and etching technics, contact hole 70 is made to be formed in interlayer insulating film 7
Precalculated position, and then expose TFT or other function element electrode districts, be electrically connected with external formed.In addition, to reduce second
The defects of semiconductor layer 4 is with 5 interface of gate insulator can carry out high annealing (anneal) to substrate and handle.Annealing temperature
Between 400 degree to 600 degree, the time can be 30 minutes or longer.
Fig. 5 A are the plan view for the 5th step of method for showing manufacture TFT according to an exemplary embodiment of the present invention, and Fig. 5 B are
The sectional view intercepted along the line V-V of Fig. 5 A.Second metal layer 8, the second metal layer 8 are further formed on the substrate 1
Material can be (A1), molybdenum (Mo) or other metal or alloy.Second metal layer 8 can be individual layer or multilayer material
Lamination.Then, by photoetching and etching technics, pattern second metal layer 8, after the second metal layer 8 inserts contact hole
Form the source electrode being connected respectively with source region 41 and drain region 42 and drain electrode.In addition, body contact zone 31 can be connect by what is shared
It contact hole 70 and next to fill the formation of second metal layer 8 therein and source region 41 and be electrically connected.In other embodiments, also may be used
It is electrically connected by the independent contact hole (not shown) and second metal layer 8 with 70 not intercommunication of contact hole with gate electrode.That is, described layer
Between insulating layer 7 be equipped with independent contact hole corresponding with the body contact zone 31 and being filled in the independent contact hole and connect with body
The second metal layer 8 that area 31 is electrically connected is touched, the body contact zone 31 passes through the second metal layer 8 and grid in the independent contact hole
Pole metal layer 6 is electrically connected.Fig. 6 is the Organic Light Emitting Diode with above-mentioned TFT according to exemplary embodiment of the present
(OLED) sectional view of display device.Referring to Fig. 6, planarization layer 91 is formed on the substrate 1 with the TFT in Fig. 5.Flat
Through hole 911 is formed in smoothization layer 91, to expose one of source electrode or drain electrode.By through hole 911 and source electrode and drain electrode it
One the first connected pixel electrode 92 is formed on planarization layer 91.Then, there is a part of first pixel electrode 92 of exposure
The pixel confining layers 93 on surface are formed on the first pixel electrode 92 and expose the first pixel electrode of part 92.Organic hair
Optical diode layer, that is, oled layer 94 is formed on 92 expose portion of the first pixel electrode, and oled layer 94 may further include
Hole injection layer, hole transmission layer, electron injecting layer, electron transfer layer, organic luminous layer etc., but not limited to this.Then second
Pixel electrode 95 is formed on oled layer 94.This completes OLED according to an exemplary embodiment of the present invention displays to fill
It puts.
Membrane according to the invention transistor, the method for manufacturing the thin film transistor (TFT) and the OLED with the thin film transistor (TFT)
Display device, by setting first, second semiconductor layer, 3,4 two layers of semiconductor layer, and along orientation, being formed has body
The thin film transistor (TFT) of contact structures, the TFT than traditional body contact structure individually extended in semiconductor layer regions save face
Product, and can preferably inhibit floater effect.
Finally it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention and it is unrestricted, although reference
The present invention is described in detail in preferred embodiment, any those of ordinary skill in the art, is not departing from this
In the spirit and scope of invention, when can make a little change and retouch, therefore protection scope of the present invention is when regarding claim model
It encloses subject to institute's defender.
Claims (10)
1. a kind of thin film transistor (TFT), it is characterised in that：It partly overlaps including the first semiconductor layer (3), with the first semiconductor layer (3)
The second semiconductor layer (4), the gate insulator (5) above the second semiconductor layer (4) and positioned at gate insulator of deposition
Gate metal layer (6) above layer (5), second semiconductor layer (4) form source region (41), drain region (42) and positioned at source region
(41) channel region between drain region (42), first semiconductor layer (3) are located under the source region (41) or drain region (42)
Side, and the covering for extending the second semiconductor layer (4) forms body contact zone (31), the body contact zone (31) can be with source region (41)
Or gate metal layer (6) forms electrical connection.
2. thin film transistor (TFT) according to claim 1, it is characterised in that：First semiconductor layer (3) is located at the source
The lower section in area (41) forms interlayer insulating film (7) on the gate metal layer (6), and the interlayer insulating film (7) is covered in simultaneously
On the gate insulator (5), the interlayer insulating film (7) is equipped with corresponding with the source region (41) and drain region (42) respectively
Contact hole (70) and the second metal layer (8) that (70) are electrically connected respectively with source region (41) and drain region (42) is filled in contact hole.
3. thin film transistor (TFT) according to claim 2, it is characterised in that：The body contact zone (31) by with source region (41)
Second metal layer (8) in shared contact hole (70) is electrically connected with source region (41) formation.
4. thin film transistor (TFT) according to claim 2, it is characterised in that：The interlayer insulating film (7) be equipped with it is described
The corresponding independent contact hole in body contact zone (31) position and being filled in the independent contact hole is electrically connected with body contact zone (31)
Second metal layer (8), the body contact zone (31) passes through the second metal layer (8) and gate metal in the independent contact hole
Layer (6) electrical connection.
5. a kind of manufacturing method of thin film transistor (TFT), it is characterised in that：Include the following steps：
Form the first semiconductor layer (3)；
The second semiconductor layer (4), and part exposure first semiconductor layer (3) are formed on first semiconductor layer (3)
To form body contact zone (31), second semiconductor layer (4) include source region (41), drain region (42) and positioned at source region (41) and
Channel region between drain region (42), the source region (41) are located above body contact zone (31), and the body contact zone (31) can be with source
Area (41) forms electrical connection；
Gate insulator (5) is formed on second semiconductor layer (4)；
Subregion forms gate metal layer (6) on the gate insulator (5).
6. the manufacturing method of thin film transistor (TFT) according to claim 5, it is characterised in that：The method further includes following step
Suddenly：
Form interlayer insulating film (7) in gate metal layer (6), the interlayer insulating film (7) while to be covered in the grid exhausted
In edge layer (5), contact corresponding with the source region (41) and drain region (42) position respectively is set on the interlayer insulating film (7)
Hole (70)；
Second metal layer (8) is formed further on interlayer insulating film (7), the second metal layer (8) enters the contact
Hole (70) simultaneously forms source electrode and drain electrode, and the body contact zone (31) extends along the length direction of channel region.
7. the manufacturing method of thin film transistor (TFT) according to claim 6, it is characterised in that：The body contact zone (31) passes through
The second metal layer (8) in contact hole (70) shared with source region (41) is electrically connected with source region (41) formation.
8. a kind of organic LED display device, it is characterised in that including：
The first semiconductor layer (3) of sheet integral type deposition；
Second semiconductor layer (4), second semiconductor layer (4) is partially depositing on first semiconductor layer (3), and part
For exposure first semiconductor layer (3) to form body contact zone (31), second semiconductor layer (4) includes source region (41), leakage
Area (42) and the channel region between source region (41) and drain region (42), the source region (41) are located in body contact zone (31)
Side, the body contact zone (31) can form with source region (41) and be electrically connected；
Gate insulator (5) is arranged on second semiconductor layer (4)；
Gate metal layer (6) is arranged on the gate insulator (5)；
Source electrode and drain electrode, the source electrode and drain electrode are electrically connected respectively with the source region (41) and drain region (42)；
One of first pixel electrode (92), first pixel electrode (92) and the source electrode or drain electrode are connected；
Organic Light Emitting Diode layer (94), the Organic Light Emitting Diode layer (94) are arranged on the first pixel electrode (92)；
Second pixel electrode (95) is arranged on the Organic Light Emitting Diode layer (94).
9. organic LED display device according to claim 8, it is characterised in that：The gate metal layer (6)
On be additionally provided with interlayer insulating film (7), the interlayer insulating film (7) while be covered on the gate insulator (5), the interlayer
Insulating layer (7) is equipped with contact hole (70) corresponding with the source region (41) and drain region (42) respectively and is filled in contact hole (70)
The second metal layer (8) being inside electrically connected respectively with source region (41) and drain region (42).
10. organic LED display device according to claim 9, it is characterised in that：The body contact zone (31)
It is electrically connected by the second metal layer (8) in the contact hole (70) shared with source region (41) with source region (41) formation.
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|---|---|---|---|---|
| US5489792A (en) * | 1994-04-07 | 1996-02-06 | Regents Of The University Of California | Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility |
| US6566176B1 (en) * | 2001-01-31 | 2003-05-20 | Advanced Micro Devices, Inc. | SOI device with wrap-around contact to underside of body, and method of making |
| CN101546782A (en) * | 2008-03-27 | 2009-09-30 | 三星移动显示器株式会社 | Thin film transistor, method of fabricating the same, and organic lighting emitting diode display device |
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| JPH07302908A (en) * | 1994-05-02 | 1995-11-14 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| KR100290787B1 (en) * | 1998-12-26 | 2001-07-12 | 박종섭 | Manufacturing Method of Semiconductor Memory Device |
| KR100513310B1 (en) * | 2003-12-19 | 2005-09-07 | 삼성전자주식회사 | Semiconductor device having two different operation modes employing an asymmetrical buried insulating layer and method of fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5489792A (en) * | 1994-04-07 | 1996-02-06 | Regents Of The University Of California | Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility |
| US6566176B1 (en) * | 2001-01-31 | 2003-05-20 | Advanced Micro Devices, Inc. | SOI device with wrap-around contact to underside of body, and method of making |
| CN101546782A (en) * | 2008-03-27 | 2009-09-30 | 三星移动显示器株式会社 | Thin film transistor, method of fabricating the same, and organic lighting emitting diode display device |
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