CN1047246C - Multi-processor system upgraded by addition of single-processor chip - Google Patents
Multi-processor system upgraded by addition of single-processor chip Download PDFInfo
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Abstract
The present invention relates to a multiprocessor system which uses a single processor chip to update and is provided with a structure similar to a single processor. The structure can be updated to a multiprocessor system by only plugging a CPU, and the plugged CPU can be different from the original CPU.
Description
The invention relates to a kind of multicomputer system with the uniprocessor chip upgrading.
With work continuous progress of computer technology and continually developing of central processor unit (CPU), no matter be that computermaker or computer user face a puzzlement greatly, that is exactly: be the computer of up-to-date machine when releasing at first or buying originally, between several years, fall behind and become the machine that is out of step with the times, for example use the personal computer system of 286CPU, be best illustration.
Certainly, the computer of old model is not to use, but in order to cooperate the development of relevant software and hardware, the user usually must manage to upgrade its outfit, could match with relevant environment.Therefore, the user must face following upgrade problem: how (1) is adapted to the renewal (by 286,386 to 486, and even in the future the P5 that is about to release of INTEL Corp. (promptly 586)) of CPU, and promotes itself all computer equipment accordingly; (2) be the computer of single processor system originally, when deposited needs not, how to be extended for the computer system of multiprocessor.
Address the above problem, constantly buy new computer machine yes a unpractical practice.In order to adapt to the continual renovation of CPU, the practice that generally can take at present has two kinds, and first kind is that the circuit board relevant with CPU all changed, not only be not inconsistent economic benefit thus, and for the user, must contact with former sale manufacturer, also very inconvenient.The another kind of practice is proposed by Acer, and its solution is to settle the circuit board of CPU to give particular design, and in the time of upgrading CPU, with the predeterminated position on the new CPU insertion circuit board, and old CPU is promptly with lost efficacy (disabled).Second method is good than first method, because can change the entire circuit plate, but the method is still undesirable, and is because (1) lost efficacy old CPU, very unfortunate; (2) the method can not solve the upgrade problem that is extended to multicomputer system by single processor system.
Understand and describedly extend to the problem of multicomputer system, must understand present single processor system and the difference between the multicomputer system earlier by single processor system.Fig. 1 illustrates an example of known single processor system, comprising a CPU11 is arranged, a cpu bus 12,13, one peripheral bus of a local bus (be depicted as EISA bus, but also can be ISA or VISA bus) 14, an interior periphery bus (XD bus) 15, CPU one local bus interface 16 is arranged between cpu bus and local bus, part-eisa bus interface 17 is arranged between local bus and eisa bus, between ETSA bus and XD bus, EISA-XD bus interface 18 is arranged.There is a system controller 19 to link up mutually with cpu bus 12 and local bus 13.Other has a bus controller 20 and local bus 13, and eisa bus 14 is linked up mutually with XD bus 15.In bus controller 20, include a coprocessor interface 21, when coprocessor mistake (coprocessor error) takes place among the CPU11 when, CPU11 together between the processor interface 21 by means of coprocessor mistake (FERR*) signal wire 24 with ignore mistake (IGNNE*) signal wire 25 and link up mutually.This moment, the coprocessor interface 21 produced interrupt request (interrupt request), was sent to new input end in IRQ13 number of interruptable controller 22.Interruptable controller 22 receive simultaneously by eisa bus 14 a plurality of interruptions inputs of coming (IRQ1, IRQ3 ... IRQ12, IRQ14 and IRQ15), these interruptions such as from printer, Winchester disk drive ... or the like; A moderator (not shown) is arranged in the inside of interruptable controller 22, this moderator is arbitrated each interrupt request, after judging priority ranking, interruptable controller 22 is sent interruptive command (interrupt command) via INT signal wire 26 and is given CPU11, carries out interruption routine by CPU11 then.
Figure 2 shows that an example of multicomputer system, comprising two CPU31,41 are arranged, each CPU all has a relevant cpu bus 32,42, and they are linked up with multiprocessor bus 34 by a processor bus interface 33,43 respectively.With single processor system similarly, also include a system controller 50, interruptable controller 51 and eisa bus 38, XD bus 39 and multiprocessor-eisa bus interface 48, EISA-XD bus interface 49 in the multicomputer system.
Two CPU31,41 respectively have its corresponding control port 35,45 processor interface 36,46 together, and CPU41 also has an interrupt vector port 47.Similar in coprocessor interface 36,46 and CPU31,41 the mode that links and the aforementioned single processor system, so needn't give unnecessary details at this.
Because the peripheral I/O of a CPU and system directly relevant (its reason will not describe in detail at this, can consult and the relevant document of multicomputer system design) only can be arranged in multicomputer system, therefore difference slightly in two CPU31,41 interruption arrangement.When CPU31 wants interrupts of CPU 41 (except the interruption that is caused because of the coprocessor mistake, CPU31 is unique interruption source of CPU41), CPU31 writes in the control port 45 of CPU41, after CPU41 receives interruptive command, just can from interrupt vector end mouth 47, obtain required information and carry out necessary interruption routine according to the data in the control port.On the other hand, when CPU41 wants interrupts of CPU 31, CPU41 must write CPU41 equally when wanting interrupts of CPU 31, CPU41 must write in the control port 35 of CPU31 equally, but because CPU41 is not unique interruption source of CPU31, so CPU41 must be through the arbitration of interruptable controller 51 to the interruption of CPU31.As shown in the figure, CPU41 inputs in the interruptable controller 51 through the IRQ13 input end the interrupt request of CPU31.After arbitration, interruptable controller is sent interruptive command and is given CPU31, and CPU31 just carries out corresponding interruption routine according to interruptable controller 51 and the data in the control port 35 afterwards.
In above explanation and accompanying drawing, omitted storer and part that some are less important, because the maximum difference of single processor system and multicomputer system, be the difference of each CPU interrupt mode.
By as can be seen above, extending to multicomputer system by single processor system is difficult really.For the present general solution of this problem is to adopt the structure of Fig. 2, on the main frame motherboard, reserve two cpu interface card insertion grooves, and will be produced on two circuit boards 30,40 with CPU31,41 relevant circuit, when only being inserted with a cpu pcb 30 in two insertion grooves, just be single processor system, and when needs expand, can purchase another piece cpu pcb, be inserted in second insertion groove, just constitute multicomputer system.The shortcoming of the method is: the user still must contact with former sale manufacturer, and must purchase another piece cpu pcb that is complementary with original cpu pcb; Not only cost is higher thus, and when original CPU has fallen behind, and the user may find required material and can't reach the purpose of expansion.In other words, except having all unfavorable factors on the financial cost when the expanding system, the method can not adapt to the upgrade problem that solves CPU.
In view of this, a project of the present invention is that a kind of multicomputer system that utilizes the uniprocessor chip upgrading will be provided.This system has the system architecture of uniprocessor, but as long as by inserting a cpu package, just can be transformed into multicomputer system.
Another purpose of the present invention is that a kind of multicomputer system that utilizes the uniprocessor chip upgrading will be provided, this system is when the multiprocessor state, two cpu packages wherein needn't be symmetrical, and can be the ad eundem CPU that different manufacturers is produced, frequency is different, or be that (for example one for 486CPU for the CPU of different brackets, one is P5CPU), as long as used CPU meets some pacing items.
Another purpose of the present invention is that a kind of multicomputer system that utilizes the uniprocessor chip upgrading will be provided, when adapting to the renewal of CPU, can in this system, directly insert the cpu package of new grade, so, except making system upgrade, and still can keep original cpu package, and system is transformed into multicomputer system by single processor system simultaneously.
A further object of the present invention is that a kind of multicomputer system that utilizes the uniprocessor chip upgrading will be provided, and this system compares with the multicomputer system (for example Fig. 2) of known technology, has the structure of greatly simplifying.
A kind of multicomputer system that utilizes the uniprocessor chip upgrading of the present invention comprises:
First central processing unit, second central processing unit, bus unit, bus interface devices, system controller;
Bus unit comprises cpu bus, local bus, peripheral bus and interior periphery bus;
Bus interface devices comprises CPU-local bus interface, part-peripheral bus interface, periphery-interior periphery bus interface;
It is characterized in that, also comprise a processor change-over circuit, bus controller, two above central processing units, a CPU control port, second or more central processing unit control ports, second or more CPU interrupt vector ports, second or the more coprocessor interface relevant with second or more central processing units;
Described first central processing unit, second or more a plurality of central processing unit be connected with cpu bus respectively;
Described processor change-over circuit is connected with system controller, and they are connected again between cpu bus and the local bus;
Bus controller is connected with local bus, peripheral bus and interior periphery bus;
Described bus controller includes coprocessor interface, moderator and interruptable controller, when first central processing unit produces the coprocessor mistake, the coprocessor interface receives the coprocessor rub-out signal next by first central processing unit, and output is ignored rub-out signal to first central processing unit, and the coprocessor interface output signal is given moderator, moderator output arbitration income value is given interruptable controller, interruptable controller is according to arbitration income value and the signal that come by peripheral bus, thereby judges whether to send signal interruption first central processing unit;
Described processor change-over circuit in order to receiving the signal that is come by system controller and to distribute to one of described central processing unit, and receives each central processing unit through cpu bus and the signal that comes and send system controller to;
The one CPU control port comprises importation and output, and the importation receives the signal next by the interior periphery bus, and its output is connected to output and is connected to bus controller; Output receives signal that is come by the importation and the processor error signal of being come by first central processing unit, and its output is connected to the interior periphery bus;
Moderator in the described bus controller also receives the signal that is come by the importation of a CPU control port except that receiving the signal next by the coprocessor interface, after arbitration, the output income value is to interruptable controller;
Described second or more coprocessor interfaces, with second or more central processing units through second or more CPU coprocessor rub-out signal lines with ignore the rub-out signal line and be connected, described second or more coprocessor interfaces have one to interrupt output;
Second or more CPU interrupt vector ports, be connected with the interior periphery bus;
Second or more CPU control ports, be connected with the interior periphery bus, and have one to interrupt output;
Described second or the interruption of more coprocessor interfaces output with second the interruption output of more CPU control ports through or be connected after, input to second or more central processing units of correspondence.
Described multicomputer system is characterized in that, also comprises a coprocessor, and this coprocessor is connected with cpu bus, and the moderator in its coprocessor rub-out signal line and the bus controller and the output of a CPU control port are connected.
In the said structure, can on cpu bus, add a coprocessor of producing, to promote the arithmetic capability of system by WEITEK company.In addition, but coprocessor interface, moderator and interruptable controller in the bus controller all independent separate come out, under the situation that interruptable controller is separated, the 2nd CPU interrupts the look-at-me of a CPU, can directly be connected with interruptable controller, or, just be connected with interruptable controller still by behind coprocessor interface and the moderator.Under the situation of set handling device change-over circuit not, also can implement the present invention by other arrangements again.
Above-mentioned and other purpose of the present invention, feature and advantage, can by following to preferred embodiment explanation and consult accompanying drawing and obtain clearer notion, in the accompanying drawing:
Fig. 1 illustrates an example of known single processor system;
Fig. 2 illustrates an example of known multicomputer system;
Fig. 3 illustrates first embodiment that utilizes the multicomputer system of uniprocessor chip upgrading of the present invention;
Fig. 4 illustrates second of the multicomputer system that utilizes uniprocessor chip upgrading of the present invention and buys and execute example;
Fig. 5 illustrates the 3rd embodiment that utilizes the multicomputer system of uniprocessor chip upgrading of the present invention.
The detailed description of preferred embodiment
Below we illustrate preferred embodiment of the present invention with reference to Fig. 3-5.
Fig. 3 illustrates the first embodiment of the present invention, comprising two CPU11A and 11B are arranged.In the system, the element of label 12 to 19,24 to 26 is identical with corresponding element function among Fig. 1, does not just give unnecessary details at this.
As previously mentioned, only can there be a CPU directly relevant in the multicomputer system, therefore be necessary for each CPU and arranges different interrupt modes with the I/O of system.In the present embodiment, be that a CPU11A arranges that a control port 27 is arranged (dashed rectangle of below among the figure), this control port 27 is connected with interior periphery bus (XD bus) 15.For convenience of description, we are divided into input (27A) and output (27B) two parts with control port 27.When CPU11B wanted interrupts of CPU 11A, CPU11B just write among the importation 27A of control port 27; Control port 27 is sent immediately and is given bus controller 20 to the interrupt request singal of a CPU11A.In the bus controller 20 except that including a coprocessor interface 21 and interruptable controller 22 as described above, other includes an IRQ13 moderator 23, this moderator 23 receives by coprocessor interface 21 and the signal that is come by control port 27, behind the arbitration decision priority ranking, send into again in the IRQ13 input end of interruptable controller 22.So interruptable controller 22 is sent interruptive command and is given CPU11A.CPU11A can learn just that according to interrupt vector (interruptvector) data of interruptable controller 22 this interruption is by the IRQ13 input end, or by other interruption sources on the peripheral bus (eisa bus) 14.If by the IRQ13 input end, then CPU11A is again according to the coprocessor mistake input value 24A among the output 27B of control port 27, just this interruption of decidable is sent by CPU11B, or produced by self coprocessor mistake.
On the other hand, when CPU11A wants interrupts of CPU 11B, as long as write in the control port 29 of CPU11B; Because except the coprocessor mistake of CPU11B self, CPU11A is unique interruption source of CPU11B, thereby CPU11B can judge the source of interruption easily, and carries out corresponding interruption routine.
The distribution of portfolio between relevant two CPU then is to carry out by a processor change-over circuit 19A.This change-over circuit 19A receives the business information next by system controller 19, and it is distributed to CPU11A or CPU11B by cpu bus 12.On the other hand, when two CPU will feed back to system controller 19, also be after integrating via change-over circuit 19A earlier, to send system controller 19 again to.Therefore, with regard to the viewpoint of system controller 19, can be considered as only in the face of a CPU.
Said structure is compared with known multicomputer system as Fig. 2, has following advantage: (1) has reduced the relevant cpu bus 32,42 of each CPU itself, and corresponding multiprocessor interface 33,43, therefore the structure of simplified system greatly; When (2) being upgraded to multicomputer system,, and needn't buy more whole C PU circuit board as long as add second CPU11B by single processor system; (3) two CPU11A, 11B needn't be identical label, even must not be the CPU of ad eundem, as long as the logical protocol of the equal energy of two CPU coupled system itself.
Fig. 4 illustrates an alternative embodiment of the invention.Because the arithmetic capability of CPU itself has some restriction, therefore in the single processor system of known technology, once there was the people on cpu bus 12, to add a coprocessor of producing in addition by WEITK company, handle some computing to assist CPU.Fig. 2 and for example, in multiprocessing system, also the someone adds this kind coprocessor 60A, 60B.In the embodiment shown in fig. 4, we provide this WEITEK coprocessor 60 too.The output 28 of the coprocessor rub-out signal line 61 (61A) of WEITEK coprocessor and CPU input control port 27A through or be connected after, in the input IRQ13 moderator 23, signal wire 61B then with the coprocessor rub-out signal line 24 (24A) of CPU11A through or after door is connected, import among the CPU output control terminal mouth 27B, when having treated that the coprocessor mistake produces, interrupt a CPU11A and handled through aforementioned similar process.
Fig. 5 illustrates the third embodiment of the present invention, comprising two CPU311A (P1) and 311B (P2) are arranged.Multicomputer system 300 comprises a local bus (Local Bus) 312, has address bus 312A, data bus 312B and control bus 312C; A peripheral bus (be illustrated as eisa bus, but also can be ISA or VISA bus) 313 also has address, data and controls three parts, and label is 313A, 313B and 313C respectively.Other has an interior periphery bus (XD Bus) 314.An EISA interface 315 is arranged between local bus 312 and peripheral bus 313,312A on the Loca1 Bus 312 and 312B bus signals are changed on signal 315C and 315D to the EISA Bus 313 by signal 315A and signal 315B.One XD interface 316 is arranged between EISABus and XD Bus, can the data-signal 313C on the EISA Bus 313 be changed into signal 316B and XD Bus 314 communications by signal 316A.
Have a system controller (SYSC) 317 via signal 318 with 319 with Local Bus on the address link to each other with control signal 312A and 312C, link to each other with control signal 313C on the EISA Bus313 simultaneously via signal 320.Other has a bus controller (BUSC) 321, link up with SYSC317 via signal 324, and by signal 322 with 323 with EISA Bus on address and control signal 313A be connected with 313C, accept the interrupt request singal 326 of EISA Bus 313 simultaneously.
As previously mentioned, multicomputer system only can have a CPU directly relevant with the I/O of system, so must link up interrupting between processor P 1 and P2.When P2 will interrupt P1, P2 just write a specific value via signal 331 and issues orders to the control port 330 of P1, and this control port 330 is promptly sent signal 328 to BUSC321, informed desire interruption P1.This signal 328 is promptly identical with WINT signal 28 among Fig. 3, is the source of IRQ13.BUSC321 just can encourage its inner IRQ13 signal after receiving WINT signal 328, after the moderator (not shown) judges that right of priority is obtained by IRQ13, give P1 so BUSC321 sends look-at-me INT1 325.The interrupt vector that P1 provides according to BUSC321 (Interrup vector) is removed to carry out interrupt service routine (Interrupt Service Routine) to the address of appointment.
Similarly, when if P1 will interrupt P2, can write a specific value via signal 333 issues orders to P2 control port 332, P2 has learnt via signal INT2 334 and has interrupted, then under the control of SYSC317, read interrupt vector through signal 336 by P2 interrupt vector port 335, and carry out corresponding interrupt service routine.
All addresses between P1 and the P2 and data and a part of control signal homogeneous phase are connected together and are put on the Local Bus 312 again.This signal is respectively 326,327 and 329.A part of control signal 338 between P1 and P2 and 339 can be handled via a local bus interface (LocalBus Interface) 337 earlier in addition, becomes signal 340 again and delivers on the local bus 312.This interface 337 can arbitrate P1 and P2 uses the right of local bus 312, and is responsible for spying upon the action of (snoop) when arbitrary CPU starting memory cycle (memory cycle).
Also include a ROM BIOS 348 in the native system 300, link up with XDBus 314 with signal 349.One EISA element 350 (for example being hard disk controller, floppy disk controller, Ethernet etc.) is connected with 313A, 313B, 313C on the EISA Bus by signal 351,352,353.Other has a system storage (system memory) 341, links up with data 312B on the local bus through signal 342, and accepts the control of SYSC317 through signal 343.Also have a system cache (system cache), link to each other with address and data-signal on the Local Bus with 346 by signal 345, and accept the control of SYSC 317 by signal 347.In each embodiment of the above, the internal storage of CPU is preferably rewriting cache memory (Write-back cache).
If necessary, can on partial circuit, add impact damper in the system, so that adjust the time difference.But itself can fully implement the system shown in the described embodiment.
Believe and can obtain to understand fully by above explanation content of the present invention.But it should be noted that above-mentioned preferred embodiment only is the usefulness for explanation, protection scope of the present invention should be determined by the scope of claims.
Claims (15)
1. multicomputer system that utilizes uniprocessor chip upgrading comprises:
First central processing unit, second central processing unit, bus unit, bus interface devices, system controller;
Bus unit comprises cpu bus, local bus, peripheral bus and interior periphery bus;
Bus interface devices comprises CPU-local bus interface, part-peripheral bus interface, periphery-interior periphery bus interface;
It is characterized in that, also comprise a processor change-over circuit, bus controller, two above central processing units, a CPU control port, second or more central processing unit control ports, second or more CPU interrupt vector ports, second or the more coprocessor interface relevant with second or more central processing units;
Described first central processing unit, second or more a plurality of central processing unit be connected with cpu bus respectively;
Described processor change-over circuit is connected with system controller, and they are connected again between cpu bus and the local bus;
Bus controller is connected with local bus, peripheral bus and interior periphery bus;
Described bus controller includes coprocessor interface, moderator and interruptable controller, when first central processing unit produces the coprocessor mistake, the coprocessor interface receives the coprocessor rub-out signal next by first central processing unit, and output is ignored rub-out signal to first central processing unit, and the coprocessor interface output signal is given moderator, moderator output arbitration income value is given interruptable controller, interruptable controller is according to arbitration income value and the signal that come by peripheral bus, thereby judges whether to send signal interruption first central processing unit;
Described processor change-over circuit in order to receiving the signal that is come by system controller and to distribute to one of described central processing unit, and receives each central processing unit through cpu bus and the signal that comes and send system controller to;
The one CPU control port comprises importation and output, and the importation receives the signal next by the interior periphery bus, and its output is connected to output and is connected to bus controller; Output receives signal that is come by the importation and the processor error signal of being come by first central processing unit, and its output is connected to the interior periphery bus;
Moderator in the described bus controller also receives the signal that is come by the importation of a CPU control port except that receiving the signal next by the coprocessor interface, after arbitration, the output income value is to interruptable controller;
Described second or more coprocessor interfaces, with second or more central processing units through second or more CPU coprocessor rub-out signal lines with ignore the rub-out signal line and be connected, described second or more coprocessor interfaces have one to interrupt output;
Second or more CPU interrupt vector ports, be connected with the interior periphery bus;
Second or more CPU control ports, be connected with the interior periphery bus, and have one to interrupt output;
Described second or the interruption of more coprocessor interfaces output with second the interruption output of more CPU control ports through or be connected after, input to second or more central processing units of correspondence.
2. multicomputer system as claimed in claim 1, it is characterized in that, also comprise a coprocessor, this coprocessor is connected with cpu bus, and the moderator in its coprocessor rub-out signal line and the bus controller and the output of a CPU control port are connected.
3. multicomputer system as claimed in claim 1 or 2 is characterized in that, the moderator that the output of the importation of a described CPU control port is connected to output and is connected to described bus controller.
4. as each described multicomputer system among the claim 1-2, it is characterized in that described each central processing unit has a rewriting cache memory.
5. multicomputer system that utilizes uniprocessor chip upgrading comprises:
First central processing unit, second central processing unit, bus unit, bus interface devices, system controller;
Bus unit comprises local bus, peripheral bus and interior periphery bus;
Bus interface devices comprises local bus interface, part-peripheral bus interface, periphery-interior periphery bus interface;
It is characterized in that, also comprise: a bus controller, a system storage, one the one CPU control port, one the 2nd CPU control port and one the 2nd CPU interrupt vector port;
Local bus is connected with first central processing unit, second central processing unit, system storage and system controller, and the data-signal of first and second processor, address signal and part control signal are directly received local bus; Local bus comprises control, data, address bus;
The one CPU control port is connected with interior periphery bus and bus controller respectively, and the 2nd CPU control port is connected with the interior periphery bus and second central processing unit respectively; The 2nd CPU interrupt vector port is connected with the interior periphery bus;
Described peripheral bus, be connected with at least one peripheral device relevant with bus controller and permission with peripheral bus, bus controller is provided with a plurality of confessions peripheral device request relevant with peripheral bus and interrupts the peripheral bus relevant peripheral device interrupt request singal input end that first processor is used, and a specific interruption request signal input end;
First processor utilize system controller and via local bus with access data in system memory, and utilize system controller and bus controller to be connected in the data of the peripheral bus relevant peripheral device on the peripheral bus with access;
Second processor utilize system controller and via the local bus access data in system storage, and interrupt the interrupt request singal of first processor to specific interruption request signal input end by sending one, first processor is interrupted in request, utilizes system controller and bus controller to be connected the data of the peripheral bus relevant peripheral device on the peripheral bus with access by first processor.
6. multicomputer system as claimed in claim 5 is characterized in that, also comprises: a first processor socket in order to the first processor of planting, one second processor socket in order to one second processor of planting; The described first processor and second processor are connected with described local bus through respective socket, and the data-signal of first and second processor, address signal and part control signal are directly received described local bus;
Described peripheral bus is with described bus controller and allow with at least one peripheral device relevant with peripheral bus and be connected that bus controller is provided with a plurality of confessions peripheral device request relevant with peripheral bus and interrupts a peripheral bus relevant peripheral device interrupt request singal input end and the specific interruption request signal input end that first processor is used.
7. multicomputer system as claimed in claim 5 is characterized in that, described bus controller is provided with the request of common point reason device and interrupts the common processor interrupt request singal input end that first processor is used;
Described second central processing unit utilize system controller and via described local bus with access data in described system storage, and interrupt the common processor interrupt request singal input end of the interrupt request singal of first processor to described bus controller by sending one, by the interrupt request first processor, utilize system controller and bus controller to be connected in the data of the peripheral bus relevant peripheral device on the peripheral bus with access by first processor.
8. as each described multicomputer system among the claim 5-7, it is characterized in that described each central processing unit has a rewriting cache memory.
9. multicomputer system as claimed in claim 5 is characterized in that, also comprises:
System board;
The described first processor socket and second processor socket directly are disposed at system board;
When the first processor socket is plugged with first processor, when second processor socket is not planted second processor, by first processor utilize described system controller via described local bus access data in described system storage; When the first processor socket is plugged with first processor and second processor socket when also being plugged with second processor, then multiprocessing system system utilize system controller by in the first processor and second processor any selectively and via the local bus access data in system storage.
10. multicomputer system as claimed in claim 5 is characterized in that, also comprises:
Processor module;
The described first processor socket and second processor socket directly are disposed at processor module.
11. multicomputer system as claimed in claim 5, it is characterized in that, comprise the coprocessor interface that an interrupt arbitrage device and makes a mistake in order to inside coprocessor that cooperate to handle first processor in the described bus controller, the interrupt request input end of bus controller comprises a plurality of peripheral device interrupt request singal input end and specific interruption request input ends that peripheral device request interruption first processor is used that are specific to, it is to interrupt the signal of first processor to this specific interruption request signal input end by producing one that first processor is interrupted in the second processor request, via the arbitration of interrupt arbitrage device, whether send the signal interruption first processor with decision.
12., it is characterized in that described specific interruption request input end is also in order to interrupt the interrupt request singal that first processor is used as a ppu request of accepting from described first processor as multicomputer system as described in the claim 11.
13., it is characterized in that described specific interruption request signal input end is the IRQ13 leg of an interruptable controller as each described multicomputer system among claim 5-7 or the 9-12.
14. multicomputer system as claimed in claim 8 is characterized in that, described specific interruption request signal input end is the IRQ13 leg of an interruptable controller.
15. multicomputer system as claimed in claim 3 is characterized in that, described each central processing unit has a rewriting cache memory.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN93102406A CN1047246C (en) | 1993-02-20 | 1993-02-20 | Multi-processor system upgraded by addition of single-processor chip |
| US08/085,125 US5493655A (en) | 1993-02-20 | 1993-06-30 | Method and apparatus for upgrading a data processing system from a single processor system to a multiprocessor system |
| EP93114735A EP0617376A1 (en) | 1993-02-20 | 1993-09-14 | Upgradeable data processing system |
| KR1019930019703A KR940020230A (en) | 1993-02-20 | 1993-09-25 | Upgradeable Data Processing System |
| JP5316139A JPH06301653A (en) | 1993-02-20 | 1993-12-16 | Data processor capable of being graded up |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN93102406A CN1047246C (en) | 1993-02-20 | 1993-02-20 | Multi-processor system upgraded by addition of single-processor chip |
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| CN1091538A CN1091538A (en) | 1994-08-31 |
| CN1047246C true CN1047246C (en) | 1999-12-08 |
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| CN93102406A Expired - Fee Related CN1047246C (en) | 1993-02-20 | 1993-02-20 | Multi-processor system upgraded by addition of single-processor chip |
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| KR0140571B1 (en) * | 1995-01-19 | 1998-07-01 | 김광호 | Multiprocessor system with bus control means |
| CN101770362B (en) * | 2009-01-06 | 2013-04-03 | 中国科学院计算技术研究所 | Distributed dynamic process generating unit meeting System C processor |
| WO2012060816A1 (en) * | 2010-11-01 | 2012-05-10 | Hewlett-Packard Development Company, L.P. | Multi-processor computer systems and methods |
| CN104007782A (en) * | 2013-02-22 | 2014-08-27 | 宏碁股份有限公司 | Electronic subsystem |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0240667A2 (en) * | 1986-03-12 | 1987-10-14 | Hitachi, Ltd. | Processor |
| US4870570A (en) * | 1983-01-24 | 1989-09-26 | Sharp Kabushiki Kaisha | Control system for multi-processor |
-
1993
- 1993-02-20 CN CN93102406A patent/CN1047246C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4870570A (en) * | 1983-01-24 | 1989-09-26 | Sharp Kabushiki Kaisha | Control system for multi-processor |
| EP0240667A2 (en) * | 1986-03-12 | 1987-10-14 | Hitachi, Ltd. | Processor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1091538A (en) | 1994-08-31 |
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