CN104714898B - A kind of distribution method and device of Cache - Google Patents
A kind of distribution method and device of Cache Download PDFInfo
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- CN104714898B CN104714898B CN201310692431.4A CN201310692431A CN104714898B CN 104714898 B CN104714898 B CN 104714898B CN 201310692431 A CN201310692431 A CN 201310692431A CN 104714898 B CN104714898 B CN 104714898B
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Abstract
The present invention is suitable for adjustment cache field, provides a kind of distribution method and device of Cache, this method includes：Obtain the Cache miss rates for the process number that the Cache miss rates register is recorded；Judge whether the Cache miss rates of the process number are higher than preset Cache miss rates threshold value；If the Cache miss rates of the process number are higher than preset Cache miss rates threshold value, adjustment Cache group echos register, process number register increase the process number and correspond to storage group.The present invention distributes the size in the spaces Cache by the miss rate of each process, can effectively reduce the case where data of the same process are replaced as often as possible because being stored in unordered different groups；By the way that register group area is arranged inside hardware, the size of the Cache of each process is adjusted according to hardware internal register group area's data, adjustment is much sooner, more efficient.
Description
Technical field
The invention belongs to cache field more particularly to the distribution methods and device of a kind of Cache.
Background technology
Requirement with Modern Electronic equipment to processor performance is higher and higher so that the internal structure of optimized processor
Become more and more important.In order to improve the operational efficiency of processor, the time that processor accesses main memory is reduced, in processor and master
Cache memory (Cache) is introduced between depositing.By the way that by the more data of processor access times, temporarily storage is placed on
Cache, since the read or write speed of Cache is more much higher than main memory, close to the speed of processor, hence for raising processor
Efficiency have extremely important effect.
By introducing Cache so that processor with the acquisition data of higher efficiency, can improve the operation effect of processor
Rate.However, since the capacity of Cache is far smaller than the capacity of main memory, and a part of number of main memory can only be stored in Cache
According to so that it needs to establish certain mapping relations between Cache and main memory, it, can be first true in Cache before processor accesses main memory
It is fixed whether to have data hit, it needs to access main memory if being not hit by.Therefore, the shortage of data in Cache is reduced as far as possible,
To improve the speed that processor obtains data.
The use of the mapping mode between more Cache and main memory is at present road group relationship maps strategy, by Cache according to
Main memory size of mutually going together divides the identical storage group of multiple sizes, and the data in a line main memory can only store fixed several
It in Cache storage groups, but is storable in storage group in arbitrary Cache rows, since processor handles the number of different programs
According to when, the access to main memory is not uniform, and a part of data be easy to causeing in Cache are often replaced, and certain parts
Data but seldom access, be unfavorable for increase Cache hit rate and improve processor performance.
Invention content
The purpose of the present invention is to provide a kind of distribution methods of Cache, to solve the prior art due to processor processing
Uneven to the access of main memory when the data of different programs, a part of data be easy to causeing in Cache are often replaced,
And the data of certain parts the problem of seldom accessing, to increase the hit rate of Cache and improve the performance of processor.
The implementation method of the present invention is as follows：Cache memories are included several sizes by a kind of distribution method of Cache
Identical storage group, the storage group include data and status storage area, address tag memory block and register group area, described
Register group area includes processor process number register, Cache miss rates register and Cache group echo registers, the side
Method includes：
Obtain the Cache miss rates for the process number that the Cache miss rates register is recorded；
Judge whether the Cache miss rates of the process number are higher than preset Cache miss rates threshold value；
If the Cache miss rates of the process number are higher than preset Cache miss rates threshold value, Cache group echos are adjusted
Register, process number register increase the process number and correspond to storage group.
Another object of the present invention is to provide a kind of distributors of Cache, which is characterized in that Cache memory packets
The identical storage group of several sizes is included, the storage group includes data and status storage area, address tag memory block and posts
Storage group area, the register group area include processor process number register, Cache miss rates register and Cache group echos
Register, described device include：
Acquiring unit, the Cache miss rates for obtaining the process number that the Cache miss rates register is recorded；
Judging unit, for judging whether the Cache miss rates of the process number are higher than preset Cache miss rates threshold
Value；
The first adjustment unit, if the Cache miss rates for the process number are higher than preset Cache miss rates threshold
Value, adjustment Cache group echos register, process number register increase the process number and correspond to storage group.
In the present invention, Cache memories include the identical storage group of several sizes, include place in each storage group
Device process number register, Cache miss rates register and Cache group echo registers are managed, by by Cache miss rate registers
The Cache miss rates of the process number recorded, judge whether the Cache miss rates of the process number lack higher than preset Cache
Mistake rate threshold value adjusts Cache group echos if the Cache miss rates of the process number are higher than preset Cache miss rates threshold value
Register, process number register increase the process number and correspond to storage group.The present invention based on hardware internal process number by being known
Not different processes distributes the size in the spaces Cache according to the miss rate of each process, can effectively reduce the same process
The case where data are replaced as often as possible because being stored in unordered different groups；Secondly, the present invention inside hardware by being arranged
Register group area adjusts the size of the Cache of each process, relative to software root by hardware internal register group area's data
The method for adjusting Cache according to application program responds much sooner, regulated efficiency higher.
Description of the drawings
Fig. 1 is the data division schematic diagram that first embodiment of the invention provides Cache memories；
Fig. 2 is the implementation flow chart of the distribution method for the Cache that first embodiment of the invention provides；
Fig. 3 is the implementation flow chart of the distribution method for the Cache that second embodiment of the invention provides；
Fig. 4 is the structural schematic diagram of the distributor for the Cache that third embodiment of the invention provides.
Specific implementation mode
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Cache miss rates described in the embodiment of the present invention, when being that finger processor reads instruction or data, data fail
The probability hit in Cache.Processor described in the embodiment of the present invention is when handling practical programs, according in hardware inside processor
The effective address of portion's process number conversion process number is actual address, wherein the hardware internal process number can be used for reading instruction
It is stored with data, there are correspondences with the address of the program of actual motion in main memory.Since an application program often accounts for
With one or several hardware internal process number, the resource of its occupancy Cache is adjusted by the way that hardware internal process number is whole,
The case where data of the same process are replaced as often as possible because being placed in unordered different groups can be effectively reduced.The present invention
The distribution method of the Cache, Cache memories include the identical storage group of several sizes, and the storage group includes number
According to and status storage area, address tag memory block and register group area, the register group area include processor process number deposit
Device, Cache miss rates register and Cache group echo registers, the method includes：
Obtain the Cache miss rates for the process number that the Cache miss rates register is recorded；
Judge whether the Cache miss rates of the process number are higher than preset Cache miss rates threshold value；
If the Cache miss rates of the process number are higher than preset Cache miss rates threshold value, Cache group echos are adjusted
Register, process number register increase the process number and correspond to storage group.
Cache memories include the identical storage group of several sizes, include processor process number in each storage group
Register, Cache miss rates register and Cache group echo registers, the process number recorded by Cache miss rate registers
Cache miss rates, judge the process number Cache miss rates whether be higher than preset Cache miss rates threshold value, if institute
The Cache miss rates for stating process number are higher than preset Cache miss rates threshold value, and adjustment Cache group echos register, process number are posted
Storage increases the process number and corresponds to storage group.The present invention is by identifying different processes, root based on hardware internal process number
According to the size in the spaces miss rate distribution Cache of each process, the data of the same process can be effectively reduced because being stored in nothing
The case where being replaced as often as possible in the different groups of sequence；Secondly, the present invention is passed through by the way that register group area is arranged inside hardware
Hardware internal register group area's data adjust the size of the Cache of each process, are adjusted according to application program relative to software
The method of whole Cache responds much sooner, regulated efficiency higher.
Embodiment one：
In embodiments of the present invention, Cache memories include the identical storage group of several sizes, are wrapped in the storage group
Data and status storage area, address tag memory block and register group area are included, the register group area includes processor process number
Register, Cache miss rates register and Cache group echo registers.
As shown in Figure 1, Cache memories are divided into data and status storage area, address tag memory block and corresponding three
A register group area, wherein for storing data with memory state, address tag memory block is used for for data and status storage area
The hit of address is compared, and three register definitions are as follows：
1) processor process number register：Processor process number for the storage group for storing current Cache, for distinguishing
The label of different processes.
2) Cache miss rates register：The Cache miss rate values for recording currently stored group in real time can be used for calculating current
Process corresponds to average Cache miss rates size when multiple storage groups.
3) Cache group echos register：The group echo of the storage group of the Cache of dynamic adjustment current process number, for knowing
Different storage group under the not same process number.
Under normal conditions, the bit wide of hardware process number is 8, can independently indicate 256 different processes.With 64K words
For the Cache for saving data space, each Cache rows are made of 64 bytes, and Cache can be divided into 128 storage groups,
Each storage group is made of 8 row Cache rows（The size of each Cache storages group can be adjusted according to actual conditions, can such as be incited somebody to action
Cache is divided into 64 storage groups, and each storage group is made of 16 rows）.
It is of the present invention Fig. 2 shows the implementation process of the distribution method of the Cache of first embodiment of the invention offer
The distribution method of Cache includes：
In step s 201, the Cache miss rates for the process number that the Cache miss rates register is recorded are obtained.
Specifically, the Cache miss rates register is used to record the missing of multiple storage groups corresponding to each process
Rate, in processor instruction fetch or access data manipulation, the hardware address for generating the data for needing to operate accordingly enters
Cache searches the corresponding process number of the hardware address, it may be determined that and the process number whether there is in Cache, if into
Journey number is present in Cache, then reports that Cache is hit, and indicates the data that the hardware address is stored in Cache, processor
It can be operated in Cache.On the contrary, if process number is not present in Cache, miss is reported, indicate do not have in Cache
The data of the hardware address are stored, in this case, the Cache of the process number are recorded by Cache miss rate registers
Miss rate.
In step S202, judge whether the Cache miss rates of the process number are higher than preset Cache miss rates threshold
Value.
Specifically, the Cache miss rates threshold value, can be adjusted according to the not used spaces Cache, work as Cache
In not used space it is more when, the Cache miss rates threshold value can be adjusted to smaller accordingly, when in the Cache
When not used space is less, the Cache miss rates threshold value can be increased accordingly.
In step S203, if the Cache miss rates of the process number are higher than preset Cache miss rates threshold value, adjust
Whole Cache group echos register, process number register increase the process number and correspond to storage group.
When the Cache miss rates of the process number are higher than preset Cache miss rates threshold value, then it represents that current process institute
The data of the corresponding storage group missing in Cache are more, need to further increase storage group to reduce missing, raising process
Number corresponding data hit.
Wherein, increase storage group by changing the Cache group echos register for needing newly-increased storage group, process number deposit
Device so that the storage group newly increased corresponds to the process number and distinguishes the different storage groups under same process.
The embodiment of the present invention includes the identical storage group of several sizes by Cache memories, in each storage group
Including processor process number register, Cache miss rates register and Cache group echo registers, by by Cache miss rates
Whether the Cache miss rates for the process number that register is recorded judge the Cache miss rates of the process number higher than preset
Cache miss rate threshold values, if the Cache miss rates of the process number are higher than preset Cache miss rates threshold value, adjustment
Cache group echos register, process number register increase the process number and correspond to storage group.The embodiment of the present invention is hard by being based on
Part internal process number identifies different processes, and the size in the spaces Cache is distributed according to the miss rate of each process, can be effective
Reduce the case where data of the same process are replaced as often as possible because being stored in unordered different groups；Secondly, the present invention is logical
It crosses register group area is set inside hardware, the Cache of each process is adjusted by hardware internal register group area's data
Size, the method for adjusting Cache according to application program relative to software respond much sooner, regulated efficiency higher.
Embodiment two：
Fig. 3 shows the implementation process of the distribution method for the Cache that second embodiment of the invention provides, Cache memories
Including the identical storage group of several sizes, the storage group include data and status storage area, address tag memory block and
Register group area, the register group area include processor process number register, Cache miss rates register and Cache groups mark
Remember register, the Cache memories further include minimum miss rate register, and details are as follows for the distribution method of the Cache：
In step S301, the process belonging to the hardware address in Cache with the presence or absence of the data of the operation is judged
Number.
Before this step, it needs the hardware address of the data operated to enter in Cache memories, is stored in Cache
Search whether that there are the process numbers belonging to the hardware address of the data of the operation in device.By checking that processor process number is deposited
Whether device obtains the process number of each storage group of current Cache, after being compared judgement, can obtain depositing in current Cache
In the process number searched.
In step s 302, it if there is no the process number belonging to the hardware address in Cache memories, distributes new
The corresponding data of the process number are written in storage group.
There is no when the process number belonging to the hardware address in Cache memories, then explanation is in Cache memories
Current point in time does not have the corresponding data of the process number in Cache memories, need to distribute new storage group write-in it is described into
The corresponding data of journey number.
Wherein, whether the new storage group, can search has not used storage group in current Cache memories, choosing
Take the not used storage group that the corresponding data of the process number are written.
If not having not used storage group in Cache memories, least recently used storage group can be searched, is made
For the storage group of the corresponding data of the process number is written.
In step S303, if there are the process number belonging to the hardware address in Cache memories, obtain described in
The Cache miss rates for the process number that Cache miss rate registers are recorded.
The Cache miss rates are recorded by Cache miss rate registers, can be directly by Cache miss rate registers
Middle reading data.
When corresponding to a storage group for process number, the Cache miss rates recorded by the storage group are the process
Number miss rate.
When corresponding to multiple storage groups for process number, the process number for obtaining the Cache miss rates register record
Cache miss rate steps be：
According to the process number that the Cache miss rates register records, the corresponding multiple storage groups of the process number are inquired；
According to the corresponding multiple storage groups of the process number of the inquiry, the Cache miss rates of the multiple storage group are obtained
Average value, the Cache miss rates as the process number.
In step s 304, judge whether the Cache miss rates of the process number are higher than preset Cache miss rates threshold
Value.
In step S305, if the Cache miss rates of the process number are higher than preset Cache miss rates threshold value, adjust
Whole Cache group echos register, process number register increase the process number and correspond to storage group.
Wherein, the adjustment Cache group echos register, the process number register increase process number correspond to storage group step
Suddenly, it specifically may include following steps：
In step S3051, search in Cache memories whether also have not used storage group；
In step S3052, if there is not used storage group in the Cache memories, Cache group echos are adjusted
Register, process number register are that the process number distributes new storage group.
In step S3053, if there is no not used storage group in the Cache memories, search minimum recently
Storage group corresponding to the process number used；
In step S3054, it is higher than preset Cache miss rates using the storage group of the lookup as Cache miss rates
The storage group of the process number of threshold value newly increased.
In addition, the embodiment of the present invention can also include recording in each period depositing for minimum miss rate by miss rate register
Storage group.When Cache data lines are replaced, if the Cache miss rates of the process number are less than preset Cache miss rates threshold
Value, then to the storage group of the miss rate minimum in the process number, by searching for the data line at least used in the storage group
As replacement data row.
It is in place of the difference of the embodiment of the present invention and embodiment one, by having been searched whether in Cache memories pair
The process number answered, can be for not having the data of the process number directly to distribute new storage group, for institute in Cache memories
When stating the Cache miss rates of process number less than preset Cache miss rates threshold value, by recording minimum miss rate in each period
Minimum storage group, it is fast by register by searching for the data line that the data behavior at least used in the storage is made to replace
Speed positioning, improves and replaces efficiency.
Embodiment three：
Fig. 4 shows the structural schematic diagram of the distributor for the Cache that third embodiment of the invention provides, and details are as follows：
The distributor of Cache described in the embodiment of the present invention, Cache memories therein include that several sizes are identical
Storage group, the storage group include data and status storage area, address tag memory block and register group area, the register
Group area includes that processor process number register, Cache miss rates register and Cache group echo registers, described device include：
Acquiring unit 401, the Cache miss rates for obtaining the process number that the Cache miss rates register is recorded；
Judging unit 402, for judging whether the Cache miss rates of the process number are higher than preset Cache miss rates
Threshold value；
The first adjustment unit 403, if the Cache miss rates for the process number are higher than preset Cache miss rates
Threshold value, adjustment Cache group echos register, process number register increase the process number and correspond to storage group.
Optionally, the acquiring unit 401 includes：
Subelement is inquired, the process number for being recorded according to the Cache miss rates register inquires the process number pair
The multiple storage groups answered；
Subelement is obtained, for the corresponding multiple storage groups of process number according to the inquiry, obtains the multiple storage
The average value of the Cache miss rates of group, the Cache miss rates as the process number.
Optionally, the Cache memories further include minimum miss rate register, and described device further includes：
Recording unit, the storage group for recording minimum miss rate in each period by miss rate register；
Replacement unit is searched, if the Cache miss rates for the process number are higher than preset Cache miss rates threshold
Value, then to the storage group of the miss rate minimum in the process number, by searching for the data line at least used in the storage group
As replacement data row.
Further, described device further includes：
Searching unit, for searching in Cache memories whether also have not used storage group；
Second adjustment unit adjusts Cache groups if for having not used storage group in the Cache memories
Flag register, process number register are that the process number distributes new storage group.
Described device of the embodiment of the present invention is corresponding with method described in embodiment one and embodiment two, is not repeated herein
It repeats.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement etc., should all be included in the protection scope of the present invention made by within refreshing and principle.
Claims (8)
1. a kind of distribution method of Cache, which is characterized in that Cache therein includes the identical storage group of several sizes, institute
It includes data and status storage area, address tag memory block and register group area to state storage group, and the register group area includes
Processor process number register, Cache miss rates register and Cache group echo registers, the method includes：
The register group area is the hardware internal register group area by being arranged inside hardware；
Obtain the Cache miss rates for the process number that the Cache miss rates register is recorded；
Judge whether the Cache miss rates of the process number are higher than preset Cache miss rates threshold value；
If the Cache miss rates of the process number are higher than preset Cache miss rates threshold value, adjustment Cache group echos deposit
Device, process number register increase the process number and correspond to storage group；
Wherein, the Cache miss rate steps of the process number for obtaining the Cache miss rates register record are：
According to the process number that the Cache miss rates register records, the corresponding multiple storage groups of the process number are inquired；
According to the corresponding multiple storage groups of the process number of the inquiry, the flat of the Cache miss rates of the multiple storage group is obtained
Mean value, the Cache miss rates as the process number.
2. method according to claim 1, which is characterized in that the Cache further includes minimum miss rate register, described to sentence
The Cache miss rates of the disconnected process number whether higher than after preset Cache miss rates threshold step, also wrap by the method
It includes：
The storage group of minimum miss rate in each period is recorded by miss rate register；
When Cache data lines are replaced, if the Cache miss rates of the process number are less than preset Cache miss rates threshold value,
Then to the storage group of the miss rate minimum in the process number, the data line at least used in the storage group is searched as replacement
Data line.
3. method according to claim 1, which is characterized in that if the Cache miss rates of the process number are higher than pre-
If Cache miss rate threshold values, adjustment Cache group echos register, process number register increase the process number and correspond to storage
Organizing step includes：
It searches in Cache and whether also has not used storage group；
If there is not used storage group in the Cache, Cache group echos register, process number register are adjusted as institute
It states process number and distributes new storage group.
4. method according to claim 3, which is characterized in that whether also have not used storage group in the lookup Cache
Later, the method further includes：
If there is no not used storage group in the Cache, the storage corresponding to least recently used process number is searched
Group；
It is newly-increased higher than the process number of preset Cache miss rates threshold value using the storage group of the lookup as Cache miss rates
The storage group added.
5. method according to claim 1, which is characterized in that recorded in the acquisition Cache miss rates register
Process number Cache miss rates the step of before, the method further includes：
Judge the process number belonging to the hardware address of the data in Cache with the presence or absence of operation；
If there is no the process numbers belonging to the hardware address in Cache, distributes new storage group and the process number pair is written
The data answered；
If there are the process number belonging to the hardware address in Cache, it is transferred to and obtains Cache miss rates register institute
The step of Cache miss rates of the process number of record.
6. a kind of distributor of Cache, which is characterized in that Cache therein includes the identical storage group of several sizes, institute
It includes data and status storage area, address tag memory block and register group area to state storage group, and the register group area includes
Processor process number register, Cache miss rates register and Cache group echo registers, described device include：
The register group area is the hardware internal register group area by being arranged inside hardware；
Acquiring unit, the Cache miss rates for obtaining the process number that the Cache miss rates register is recorded；
Judging unit, for judging whether the Cache miss rates of the process number are higher than preset Cache miss rates threshold value；
The first adjustment unit is adjusted if the Cache miss rates for the process number are higher than preset Cache miss rates threshold value
Whole Cache group echos register, process number register increase the process number and correspond to storage group；
Wherein, the acquiring unit includes：
Subelement is inquired, it is corresponding to inquire the process number for the process number for being recorded according to the Cache miss rates register
Multiple storage groups；
Subelement is obtained, for the corresponding multiple storage groups of process number according to the inquiry, obtains the multiple storage group
The average value of Cache miss rates, the Cache miss rates as the process number.
7. device according to claim 6, which is characterized in that the Cache further includes minimum miss rate register, the dress
It sets and further includes：
Recording unit, the storage group for recording minimum miss rate in each period by miss rate register；
Replacement unit is searched, if the Cache miss rates for the process number are less than preset Cache miss rates threshold value,
To the storage group of the miss rate minimum in the process number, the data line at least used in the storage group is searched as replacement number
According to row.
8. device according to claim 6, which is characterized in that described device further includes：
Searching unit, for searching in Cache whether also have not used storage group；
Second adjustment unit, if for there is not used storage group in the Cache, adjust Cache group echos register,
Process number register is that the process number distributes new storage group.
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| CN108255601B (en) * | 2016-12-29 | 2021-01-15 | 华为技术有限公司 | Method and device for allocating LLC resources |
| CN110443360B (en) * | 2017-06-16 | 2021-08-06 | 上海兆芯集成电路有限公司 | Method for operating a processor |
| CN111506521B (en) * | 2019-01-31 | 2023-10-20 | 华为技术有限公司 | Memory, data request writing method and controller |
| CN114356588B (en) * | 2022-03-18 | 2022-06-17 | 苏州云途半导体有限公司 | Data preloading method and device |
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| CN102521153A (en) * | 2011-12-07 | 2012-06-27 | 华中科技大学 | Method for distributing shared buffer of multi-core processor |
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Non-Patent Citations (1)
| Title |
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| 嵌入式系统中低功耗可重构Cache的研究与设计;刘清;《中国优秀硕士学位论文全文数据库 信息科技辑》;20130615(第6期);第2章-第5章 * |
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