CN104714854A - Fault tolerant circuit for solving RapidIO bus link response packet losing - Google Patents
Fault tolerant circuit for solving RapidIO bus link response packet losing Download PDFInfo
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- CN104714854A CN104714854A CN201310689798.0A CN201310689798A CN104714854A CN 104714854 A CN104714854 A CN 104714854A CN 201310689798 A CN201310689798 A CN 201310689798A CN 104714854 A CN104714854 A CN 104714854A
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Abstract
The invention relates to a fault tolerant circuit for solving RapidIO bus link response packet losing. Only a lost data packet and other data packets after the lost data packet can be retransmitted, and the communication efficiency of a RapidIO bus when link response packet losing occurs is improved. According to the fault tolerant circuit, a data storage circuit, a data comparing circuit and a data packet transmitting circuit are additionally arranged inside a circuit body, and the data storage circuit is connected with the data packet transmitting circuit through the data comparing circuit. Whether the response packet of the current data packet is lost or not can be rapidly detected, the lost data packet can be retransmitted during losing, and therefore the communication efficiency of the RapidIO bus when link response packet losing occurs can be greatly improved.
Description
Technical field
The invention belongs to computer hardware technology field, be specifically related to the fault tolerable circuit and the repeating method that solve RapidIO bus links respond packet loss.
Background technology
RapidIO bus, when communicating continuously with its link partner, has the less situation that may occur link response packet loss.Traditional solution is: when having detected that respond packet is lost, then package from first data of this frame, all request bags all retransmit, respond packet all abandons, although can deal with problems like this, have a strong impact on the communication efficiency of RapidIO bus, cause its traffic rate significantly to reduce.
Summary of the invention
In order to solve the problems referred to above mentioned in background technology, the invention provides a kind of fault tolerable circuit and the repeating method that solve RapidIO bus links respond packet loss, can other packets only after the packet of retransmission of lost and lost data packets, improve the communication efficiency of RapidIO bus when there is link response packet loss.
Technical solution of the present invention is:
Solve the fault tolerable circuit that RapidIO bus links respond packet is lost, its special character is: comprise data comparison circuit and data packet transmission circuit that data storage circuitry, the transmission ID of request bag stored by data storage circuitry and the transmission ID of respond packet that receives from RapidIO bus compare; The transmission ID output terminal of data storage circuitry is connected with data packet transmission circuit by data comparison circuit, and the data output end of data storage circuitry is connected with data packet transmission circuit.
Data storage circuitry comprises FIFO and data storage management circuit, and data storage management circuit is connected with data comparison circuit by FIFO.
Data packet transmission circuit comprises MUX and the RapidIO interface circuit of the output terminal being connected to data comparison circuit in turn.
Data comparison circuit is comparer.
Solve the repeating method that RapidIO bus links respond packet is lost, its special character is: comprise the following steps:
(1) request bag is sent to data storage circuitry by main frame, and after data storage circuitry arranges data, the key parameter of request bag will be stored in data storage circuitry; Key parameter comprises address, data, transmission ID and data length; Meanwhile, the data in key parameter are sent in data packet transmission circuit, and data packet transmission circuit carries out normal data transmit operation;
(2) data comparison circuit waits for that RapidIO bus links beams back respond packet, after data comparison circuit receives the respond packet that RapidIO bus links beams back, data comparison circuit extracts the transmission ID returned in respond packet, and compares with the transmission ID be stored in data storage circuitry in step 1;
(3) when comparative result is consistent, data comparison circuit outputs control signals to data packet transmission circuit, and the key parameter in data storage circuitry will be dropped;
When comparative result is inconsistent, data comparison circuit outputs control signals to data packet transmission circuit, and from data storage circuitry, take out the key parameter of step 1 storage, and data packet transmission circuit is set up the packet lost and also completed transmission.
The invention has the advantages that: the present invention increases data storage circuitry, data comparison circuit and data packet transmission circuit at inside circuit, whether the respond packet that can detect rapidly current data packet loses, and when losing the packet of retransmission of lost, thus greatly improve the communication efficiency of RapidIO bus when there is link response packet loss.
Accompanying drawing explanation
Fig. 1 is schematic block circuit diagram of the present invention;
Fig. 2 is the physical circuit figure of fault tolerable circuit of the present invention;
Fig. 3 is the preferred embodiment configuration diagram of system provided by the present invention.
Embodiment
As Fig. 1, a kind of fault tolerable circuit solving RapidIO bus links respond packet and lose, comprises data storage circuitry, data comparison circuit and data packet transmission circuit; Data storage circuitry is connected with data packet transmission circuit by data comparison circuit.
As Fig. 2, data storage circuitry comprises 64 bit wides, 512 dark FIFO and data storage management circuit, and data storage management circuit is connected with data comparison circuit by FIFO.
The function of data storage management circuit is: when main frame normally sends request bag, by the address of transmission data, data, transmission ID, data length composition storage of array in FIFO.
Data comparison circuit comprises comparer, and data comparison circuit can be 8 bit comparators, when receiving the transmission ID of request bag and the transmission ID of respond packet that store from data storage circuitry, comparing, and exporting comparative result to data packet transmission circuit;
Data packet transmission circuit, existing data packet transmission circuit can be adopted, it is when receiving the comparative result that data comparison circuit exports, according to result, if comparative result is equal, data packet transmission circuit does not do any operation, if comparative result is unequal, according to the data framing again of the respond packet that data storage circuitry sends, and send repeat requests, notification data memory circuit carries out read operation, data are delivered to data packet transmission circuit and carry out framing transmission, until the FIFO in data storage circuitry is read sky.
Solve the repeating method that RapidIO bus links respond packet is lost, it is characterized in that: comprise the following steps:
(1) request bag is sent to the data storage management circuit of data storage circuitry by main frame, and after data storage management circuit arranges data, the key parameter of request bag will be stored in FIFO; Key parameter comprises address, data, transmission ID and data length; Meanwhile, the data in key parameter are sent in the MUX of data packet transmission circuit, and RapidIO interface circuit carries out normal data transmit operation;
(2) data comparison circuit waits for that RapidIO bus links beams back respond packet, after data comparison circuit receives the respond packet that RapidIO bus links beams back, data comparison circuit extracts the transmission ID returned in respond packet, and compares with the transmission ID be stored in FIFO in step 1;
(3) when comparative result is consistent, data comparison circuit exports the MUX of control signal 0 to data packet transmission circuit, and is abandoned by the key parameter in FIFO;
When comparative result is inconsistent, indicate data-bag lost, data comparison circuit exports control signal 1 to MUX, and takes out the key parameter of step 1 storage from FIFO, and RapidIO interface circuit is again set up the packet of loss and resend till FIFO is read sky.
Fig. 3 is the preferred embodiment configuration diagram of system provided by the present invention, and be the inner RapidIO interface 1394 bus protocol process chip sketch using universal data interface, in figure, namely RapidIO fault tolerable circuit adopts the circuit in the present invention.
Claims (5)
1. solve the fault tolerable circuit that RapidIO bus links respond packet is lost, it is characterized in that: comprise data comparison circuit and data packet transmission circuit that data storage circuitry, the transmission ID of request bag stored by data storage circuitry and the transmission ID of respond packet that receives from RapidIO bus compare; The transmission ID output terminal of data storage circuitry is connected with data packet transmission circuit by data comparison circuit, and the data output end of data storage circuitry is connected with data packet transmission circuit.
2. the fault tolerable circuit of solution RapidIO bus links respond packet loss according to claim 1, is characterized in that: data storage circuitry comprises FIFO and data storage management circuit, and data storage management circuit is connected with data comparison circuit by FIFO.
3. the fault tolerable circuit of solution RapidIO bus links respond packet loss according to claim 1 and 2, is characterized in that: data packet transmission circuit comprises MUX and the RapidIO interface circuit of the output terminal being connected to data comparison circuit in turn.
4. the fault tolerable circuit of solution RapidIO bus links respond packet loss according to claim 3, is characterized in that: data comparison circuit is comparer.
5. solve the repeating method that RapidIO bus links respond packet is lost, it is characterized in that: comprise the following steps:
(1) request bag is sent to data storage circuitry by main frame, and after data storage circuitry arranges data, the key parameter of request bag will be stored in data storage circuitry; Key parameter comprises address, data, transmission ID and data length; Meanwhile, the data in key parameter are sent in data packet transmission circuit, and data packet transmission circuit carries out normal data transmit operation;
(2) data comparison circuit waits for that RapidIO bus links beams back respond packet, after data comparison circuit receives the respond packet that RapidIO bus links beams back, data comparison circuit extracts the transmission ID returned in respond packet, and compares with the transmission ID be stored in data storage circuitry in step 1;
(3) when comparative result is consistent, data comparison circuit outputs control signals to data packet transmission circuit, and the key parameter in data storage circuitry will be dropped;
When comparative result is inconsistent, data comparison circuit outputs control signals to data packet transmission circuit, and from data storage circuitry, take out the key parameter of step 1 storage, and data packet transmission circuit is set up the packet lost and also completed transmission.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310689798.0A CN104714854A (en) | 2013-12-14 | 2013-12-14 | Fault tolerant circuit for solving RapidIO bus link response packet losing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310689798.0A CN104714854A (en) | 2013-12-14 | 2013-12-14 | Fault tolerant circuit for solving RapidIO bus link response packet losing |
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| CN104714854A true CN104714854A (en) | 2015-06-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310689798.0A Pending CN104714854A (en) | 2013-12-14 | 2013-12-14 | Fault tolerant circuit for solving RapidIO bus link response packet losing |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111478814A (en) * | 2020-04-09 | 2020-07-31 | 中国电子科技集团公司第五十八研究所 | Anti-interference RapidIO exchanger data exchange implementation method |
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| US4916704A (en) * | 1987-09-04 | 1990-04-10 | Digital Equipment Corporation | Interface of non-fault tolerant components to fault tolerant system |
| US20090196220A1 (en) * | 2006-01-23 | 2009-08-06 | Ntt Docomo, Inc. | Mobile communication apparatus |
| CN101521586A (en) * | 2008-02-28 | 2009-09-02 | 株式会社Ntt都科摩 | Multicast method in wireless local area network |
| CN101714915A (en) * | 2009-11-02 | 2010-05-26 | 清华大学 | Data retransmission method and system |
| CN102883466A (en) * | 2011-07-15 | 2013-01-16 | 中国科学院深圳先进技术研究院 | Data dissemination method in wireless sensor network |
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2013
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4916704A (en) * | 1987-09-04 | 1990-04-10 | Digital Equipment Corporation | Interface of non-fault tolerant components to fault tolerant system |
| US20090196220A1 (en) * | 2006-01-23 | 2009-08-06 | Ntt Docomo, Inc. | Mobile communication apparatus |
| CN101521586A (en) * | 2008-02-28 | 2009-09-02 | 株式会社Ntt都科摩 | Multicast method in wireless local area network |
| CN101714915A (en) * | 2009-11-02 | 2010-05-26 | 清华大学 | Data retransmission method and system |
| CN102883466A (en) * | 2011-07-15 | 2013-01-16 | 中国科学院深圳先进技术研究院 | Data dissemination method in wireless sensor network |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111478814A (en) * | 2020-04-09 | 2020-07-31 | 中国电子科技集团公司第五十八研究所 | Anti-interference RapidIO exchanger data exchange implementation method |
| CN111478814B (en) * | 2020-04-09 | 2022-05-17 | 中国电子科技集团公司第五十八研究所 | Anti-interference RapidIO exchanger data exchange implementation method |
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Application publication date: 20150617 |