CN104701240A - Method for preparing high-k dielectric layer - Google Patents
Method for preparing high-k dielectric layer Download PDFInfo
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- CN104701240A CN104701240A CN201510149025.2A CN201510149025A CN104701240A CN 104701240 A CN104701240 A CN 104701240A CN 201510149025 A CN201510149025 A CN 201510149025A CN 104701240 A CN104701240 A CN 104701240A
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Abstract
The invention provides a method for preparing a high-k dielectric layer. The method for preparing the high-k dielectric layer comprises the steps of 1 pre-cleaning a semiconductor silicon substrate, 2 executing growth of a SiO2 or SiON layer, 2 depositing the high-k dielectric layer and 4 conducting annealing treatment on the high-k dielectric layer, wherein mixed gas of O2, HC1 and N2 serves as annealing gas. In the annealing treatment of the step 4, the process temperature ranges from 400 DEG C to 800 DEG C, N2 flow ranges from 10 S1m to 50 S1m, O2 flow ranges from 1 S1m to 10 S1m, HC1 flow ranges from 0.02 S1m to 0.5 S1m, and process time is 0.2 to 5 minutes.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of method for the preparation of high k (high-k) dielectric layer.
Background technology
Along with the develop rapidly of very lagre scale integrated circuit (VLSIC) (VLSI) and ultra large scale integrated circuit (ULSI), the size of MOS device constantly reduces.For increasing the reaction speed of device, improving the capacity of drive current and storage capacitance, in device, the thickness of gate oxide constantly reduces.But thing followed two problems becomes the key factor hindering integrated circuit to further develop: leak electricity and puncture.When gate oxide thickness lower than
due to quantum tunneling effect, charge carrier can flow through this ultra-thin gate dielectric, and charge carrier tunnelling probability exponentially rises along with the minimizing of the thickness of oxide layer.When MOSFET in integrated circuit works, electric charge flows through device to be caused producing defect at gate dielectric layer and SiO2/Si interface, and when critical defective density reaches, gate dielectric layer punctures, and causes component failure.Below technology node to 45 nanometers, traditional SiON gate medium can not meet the electric leakage of device and puncture requirement, and not only because the excessive device that causes that leaks electricity cannot normally work, and time breakdown (TDDB) can not meet reliability requirement.
From the formula of drive current and gate capacitance, gate capacitance is larger, and drive current is larger; And gate dielectric layer dielectric constant is larger, gate capacitance is larger.
I
D～μ/L
g*C
ox(V
DD-V
TH)
2
C
ox＝kA/d
Wherein I
dfor drive current, μ is carrier mobility, L
gfor grid length, C
oxfor gate capacitance, V
dDfor operating voltage, V
tHfor threshold voltage, k is gate dielectric layer dielectric constant, and A is device area, and d is gate dielectric layer thickness.
Therefore, need a kind of alternative gate dielectric layer material, not only will have enough thick actual (real) thickness to reduce leakage current density and to strengthen time breakdown (TDDB) reliability requirement, and high grid capacitance can be provided to increase drive current.In order to achieve the above object, the dielectric constant that the gate dielectric layer material substituted has needs the dielectric constant higher than traditional silicon oxynitride (SiON).Therefore below 45 nm technology node, in the urgent need to adopting novel high-k gate dielectric if the oxide of Hf base, Zr or Al is to replace SiON.
Because high-k gate dielectric material is mainly based on metal oxide, must the existence of aerobic in preparation process, and the reaction of oxygen and silicon can form the interface oxide layer of silicon dioxide or silicide between high-k dielectric layer and silicon substrate, the existence due to this oxide layer makes reducing of oxide equivalent thicknesses (EOT) become difficulty.In order to suppress the generation of this oxide layer, need before high-k dielectric layer deposition, grow one deck high-quality ultra-thin Si O2 or SiON layer.
The preparation flow that high-k gate dielectric is conventional is: first carry out front cleaning; Perform ultra-thin Si O2 or SiON layer growth subsequently; After this high-k dielectric layer deposition is carried out; Perform high-k dielectric layer after annealing process (PostAnneal) subsequently, wherein by N
2, N
2o, NO, O
2or its gaseous mixture is as anneal gas.
But in the preparation method of the high-k gate dielectric of prior art, the concentration of metal ions in high-k dielectric layer and high k boundary layer is higher, and existing defects in high k boundary layer.
Summary of the invention
Technical problem to be solved by this invention is for there is above-mentioned defect in prior art, provides a kind of concentration of metal ions that can reduce in high k boundary layer higher and eliminates the method for the preparation of high-k dielectric layer of existing defects in high k boundary layer.
In order to realize above-mentioned technical purpose, according to the present invention, providing a kind of method for the preparation of high-k dielectric layer, comprising: first step, for carrying out front cleaning to bulk silicon substrate; Second step, for performing SiO
2or SiON layer growth; Third step, for depositing high-k dielectric layer; 4th step, for carrying out annealing in process, wherein by O to high-k dielectric layer
2, HCl and N
2gaseous mixture as anneal gas.
Preferably, described high-k dielectric layer is high k gate dielectric layer.
Preferably, technological temperature is 600 DEG C, N
2flow is 20Slm, O
2flow is 5Slm, HCl flow is 0.1Slm, and the process time is 0.5min.
Preferably, third step deposition high-k dielectric layer thickness between
extremely
between.
Preferably, the thickness of the high-k dielectric layer of third step deposition is
Preferably, high-k dielectric layer is HfO
2layer, ZrO
2layer or Al
2o
3layer;
Preferably, the SiO of second step growth
2or the thickness of SiON layer between
extremely
between.
Preferably, the SiO of second step growth
2or the thickness of SiON layer is
Preferably, in a first step, clean before using acid tank to carry out high k to bulk silicon substrate.
Preferably, described bulk silicon substrate comprises N/P well structure and shallow trench isolation from sti structure.
The present invention introduces HCl to the defect reducing metal ion in the high k boundary layer concentration such as (Na+ and K+ metal ion) and repair in high-k dielectric layer in the process of high-k dielectric layer after annealing, and can also reduce Si/SiO in high k boundary layer simultaneously
2the interfacial state at interface.And Cl ion also can volatilize in a gaseous form with Na/K ionic reaction in high k boundary layer, reaches the effect reducing Na/K ion concentration; Cl ion can eliminate Si/SiO in boundary layer
2the dangling bonds of interface, reach and reduce Si/SiO
2the effect of interfacial state.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 schematically shows according to the preferred embodiment of the invention for the preparation of the flow chart of the method for high-k dielectric layer.
It should be noted that, accompanying drawing is for illustration of the present invention, and unrestricted the present invention.Note, represent that the accompanying drawing of structure may not be draw in proportion.Further, in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention clearly with understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
Fig. 1 schematically shows according to the preferred embodiment of the invention for the preparation of the flow chart of the method for high-k dielectric layer.Such as, described high-k dielectric layer is high k gate dielectric layer.
As shown in Figure 1, comprise for the preparation of the method for high-k dielectric layer according to the preferred embodiment of the invention:
First step S1, for carrying out front cleaning to bulk silicon substrate; Preferably, clean before using acid tank to carry out high k to bulk silicon substrate; Such as, described bulk silicon substrate comprises N/P well structure and shallow trench isolation from sti structure, follow-uply can carry out the formation of high k gate dielectric layer thus;
Second step S2, for performing ultra-thin Si O
2or SiON layer growth; Preferably, SiO
2or the thickness of SiON layer between
extremely
between; Further preferably, SiO
2or the thickness of SiON layer is
Particularly, such as, in second step S2, utilize original position moisture-generation process (in-situ steamgeneration, ISSG) to grow SiON layer, wherein technological temperature is 900 DEG C, and process gas is N
2o+H
2+ N
2.
Such as, in second step S2, utilize DPN (Decoupled Plasma Nitridation) technique to grow SiON layer, wherein process conditions are ePRF 900W, and process gas is N
2.
Such as, in second step S2, utilize PNA (Post NitridationAnneal) technique to grow SiON layer, wherein technological temperature is 1100 DEG C, and process gas is N
2o+N
2.
Third step S3, for depositing high-k dielectric layer; Preferably, high-k dielectric layer is HfO
2layer, ZrO
2layer or Al
2o
3layer.And, preferably, the thickness of high-k dielectric layer between
extremely
between.Further preferably, the thickness of high-k dielectric layer is
4th step S4, for carrying out annealing in process, wherein by O to high-k dielectric layer
2, HCl and N
2gaseous mixture as anneal gas.Preferably, in annealing in process, technological temperature is 600 DEG C, N
2flow is 20Slm, O
2flow is 5Slm, HCl flow is 0.1Slm, and the process time is 0.5min.
The present invention introduces HCl to the defect reducing metal ion in the high k boundary layer concentration such as (Na+ and K+ metal ion) and repair in high-k dielectric layer in the process of high-k dielectric layer after annealing, and can also reduce Si/SiO in high k boundary layer simultaneously
2the interfacial state (Dit) at interface.And Cl ion also can volatilize in a gaseous form with Na/K ionic reaction in high k boundary layer, reaches the effect reducing Na/K ion concentration; Cl ion can eliminate Si/SiO in boundary layer
2the dangling bonds of interface, reach and reduce Si/SiO
2the effect of interfacial state.
In addition, it should be noted that, unless stated otherwise or point out, otherwise the term " first " in specification, " second ", " the 3rd " etc. describe only for distinguishing each assembly, element, step etc. in specification, instead of for representing logical relation between each assembly, element, step or ordinal relation etc.
Be understandable that, although the present invention with preferred embodiment disclose as above, but above-described embodiment and be not used to limit the present invention.For any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the technology contents of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1., for the preparation of a method for high-k dielectric layer, it is characterized in that comprising:
First step, for carrying out front cleaning to bulk silicon substrate;
Second step, for performing SiO
2or SiON layer growth;
Third step, for depositing high-k dielectric layer;
4th step, for carrying out annealing in process, wherein by O to high-k dielectric layer
2, HCl and N
2gaseous mixture as anneal gas.
2. the method for the preparation of high-k dielectric layer according to claim 1, is characterized in that, described high-k dielectric layer is high k gate dielectric layer.
3. the method for the preparation of high-k dielectric layer according to claim 1 and 2, is characterized in that, in the annealing in process of the 4th step, technological temperature is 400 ~ 800 DEG C, N
2flow is 10 ~ 50Slm, O
2flow is 1 ~ 10Slm, HCl flow is 0.02 ~ 0.5Slm, and the process time is 0.2 ~ 5min; Preferably, technological temperature is 600 DEG C, N
2flow is 20Slm, O
2flow is 5Slm, HCl flow is 0.1Slm, and the process time is 0.5min.
4. the method for the preparation of high-k dielectric layer according to claim 1 and 2, is characterized in that, third step deposition high-k dielectric layer thickness between
extremely
between.
5. the method for the preparation of high-k dielectric layer according to claim 3, is characterized in that, the thickness of the high-k dielectric layer of third step deposition is
6. the method for the preparation of high-k dielectric layer according to claim 1 and 2, is characterized in that, high-k dielectric layer is HfO
2layer, ZrO
2layer or Al
2o
3layer.
7. the method for the preparation of high-k dielectric layer according to claim 1 and 2, is characterized in that, the SiO of second step growth
2or the thickness of SiON layer between
extremely
between.
8. the method for the preparation of high-k dielectric layer according to claim 1 and 2, is characterized in that, the SiO of second step growth
2or the thickness of SiON layer is
9. the method for the preparation of high-k dielectric layer according to claim 1 and 2, is characterized in that, in a first step, cleans before using acid tank to carry out high k to bulk silicon substrate.
10. the method for the preparation of high-k dielectric layer according to claim 1 and 2, is characterized in that, described bulk silicon substrate comprises N/P well structure and shallow trench isolation from sti structure.
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|---|---|---|---|
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105047553A (en) * | 2015-08-26 | 2015-11-11 | 上海华力微电子有限公司 | Surface treatment method for depositing high-dielectric value gate medium layer |
| CN105304691A (en) * | 2015-10-14 | 2016-02-03 | 上海华力微电子有限公司 | Method for preparing interface layer of high-K dielectric layer |
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| US20040029398A1 (en) * | 2002-08-07 | 2004-02-12 | Kong-Soo Lee | Methods of forming gate oxide films in integrated circuit devices using wet or dry oxidization processes with reduced chloride |
| CN1604278A (en) * | 2003-10-01 | 2005-04-06 | 台湾积体电路制造股份有限公司 | A method for treating a gate structure |
| US20070001244A1 (en) * | 2001-08-27 | 2007-01-04 | Renesas Technology Corporation | Semiconductor device and manufacturing method thereof |
| CN102915917A (en) * | 2011-08-03 | 2013-02-06 | 中国科学院微电子研究所 | Preparation method of complementary metal oxide semiconductor field effect transistor |
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2015
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Patent Citations (5)
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|---|---|---|---|---|
| KR20020009213A (en) * | 2000-07-25 | 2002-02-01 | 윤종용 | Method for forming dual-gate oxide layer in semiconductor device |
| US20070001244A1 (en) * | 2001-08-27 | 2007-01-04 | Renesas Technology Corporation | Semiconductor device and manufacturing method thereof |
| US20040029398A1 (en) * | 2002-08-07 | 2004-02-12 | Kong-Soo Lee | Methods of forming gate oxide films in integrated circuit devices using wet or dry oxidization processes with reduced chloride |
| CN1604278A (en) * | 2003-10-01 | 2005-04-06 | 台湾积体电路制造股份有限公司 | A method for treating a gate structure |
| CN102915917A (en) * | 2011-08-03 | 2013-02-06 | 中国科学院微电子研究所 | Preparation method of complementary metal oxide semiconductor field effect transistor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105047553A (en) * | 2015-08-26 | 2015-11-11 | 上海华力微电子有限公司 | Surface treatment method for depositing high-dielectric value gate medium layer |
| CN105304691A (en) * | 2015-10-14 | 2016-02-03 | 上海华力微电子有限公司 | Method for preparing interface layer of high-K dielectric layer |
| CN105304691B (en) * | 2015-10-14 | 2018-07-20 | 上海华力微电子有限公司 | The method for being used to prepare the boundary layer of high-K dielectric layer |
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Application publication date: 20150610 |
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