CN104700044A - Anti-failure injection attacking method and device for interchange of input and output of registers - Google Patents
Anti-failure injection attacking method and device for interchange of input and output of registers Download PDFInfo
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- CN104700044A CN104700044A CN201510094757.6A CN201510094757A CN104700044A CN 104700044 A CN104700044 A CN 104700044A CN 201510094757 A CN201510094757 A CN 201510094757A CN 104700044 A CN104700044 A CN 104700044A
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Abstract
The invention discloses an anti-failure injection attacking method and device for the interchange of the input and the output of registers. The anti-failure injection attacking method for the interchange of the input and output of registers comprises the following steps: S1, obtaining a first maximum data width required when an encryption algorithm is operated on the target integrated circuit; S2, obtaining a second maximum data width required when an encryption algorithm is operated on the target integrated circuit according to the first maximum data width; S3, grouping a plurality of registers required to be subjected to the interchange of input and output according to the second maximum data width; S4, modifying a plurality of circuits at the registers in each group; S5, confirming the control number of circuits subjected to data selection at the register circuits of each group; S6, confirming the data selecting rules of the circuits at the registers in each group according to the control number. Through the adoption of the anti-failure injection attacking method, the registers for storing the data of the encryption algorithm are not fixed, so that the possibility of successfully injecting failures into circuits is lowered, and the safety of the circuits is improved.
Description
Technical field
The present invention relates to Research on Integrated Circuit Security technical field, the fault-resistant injection attacks device that the fault-resistant injection attacks method of particularly a kind of register input and output exchange and a kind of register input and output are exchanged.
Background technology
The fast development of society science and technology, life is informationization, digitizing and networking increasingly.The security of people to information is also more and more paid attention to, and this also impels cipher processor to update.In order to the safety of better guarantee information, the cryptographic algorithm that cipher processor not only needs security higher, also needs to protect cipher processor itself at hardware view simultaneously.
With regard to cryptographic algorithm, for widely used Advanced Encryption Standard (AES) in the world, AES is considered to have very high security, if want to crack AES completely by mathematical way, the time of cost in billions of year, therefore will can think that existing cryptographic algorithm is safe in mathematics aspect.And at the hardware view of Cipher Processing, still in the face of very large security threat, wherein fault injection attacks is exactly the attack pattern of a kind of enforcement at hardware view, its feature is can logical value on instantaneous change encryption processor encrypted circuit, cause the transient fault of circuit, finally cause encryption processor to produce the output ciphertext of mistake, utilize some mistake to export ciphertext, assailant just likely decodes key or offers help to key attack.
Assailant is when performing fault injection attacks, first need to carry out injection test to circuit to enter, namely circuit various piece is all carried out to the injection of certain number of times, object is to determine that the fault of which part in circuit can be reflected to output terminal, the mistake producing true-to-shape exports ciphertext, and this process is called the search phase.Assailant to find in circuit can on export ciphertext produce specific effect (this kind of impact cause exporting ciphertext can victim utilize to resolve key) part after, need the injection that this partial circuit is continued, ciphertext is exported with the mistake obtaining the abundant quantity that assailant needs, after obtaining the wrong ciphertext enough needed, fault injection attacks completes, and this process is called the lasting injection stage.
In order to reduce the threat of fault injection attacks, cipher processor needs to take the measure of fault-resistant injection attacks.The mode that traditional fault-resistant injection attacks measure utilizes redundancy and compares, adds testing mechanism in circuit, detects ciphering process and whether occurs exception.Be broadly divided into: information redundancy, time redundancy and hardware redundancy.Information redundancy refers to and increases a part within hardware and realize the circuit of the linear or nonlinear function such as fault check code to detect mistake within the specific limits.Time redundancy refers to and repeats ciphering process all or in part in time, and two times result is identical just to be exported, and brings the lifting of security by the expense on the execution time.Hardware redundancy refers to copying original circuit in whole or in part, and the result comparing the two improves with this security exporting ciphertext.
Can be known by traditional redundancy countermeasure above, redundancy countermeasure works to fault existing in circuit, but do not increase the difficulty of assailant's direct fault location, in order to better fault injection attacks can be resisted, can, in the difficulty of direct fault location stage increase direct fault location, assailant be made to be difficult to successfully inject fault.The object of attack of fault injection attacks is generally ALU (ALU) on computing array and register.And relevant research shows, implements easier than ALU of register is injected, therefore, the direct fault location stage to register in data protect and just seem necessary.
Summary of the invention
The present invention is intended to solve one of technical matters in correlation technique at least to a certain extent.For this reason, one object of the present invention is to propose a kind of fault-resistant injection attacks method that can reduce the register input and output exchange of the probability that assailant is successfully injected by register pair circuit.
Another object of the present invention is the fault-resistant injection attacks device proposing a kind of register input and output exchange.
To achieve these goals, according to the fault-resistant injection attacks method that the register input and output of the embodiment of the present invention are exchanged, comprise the following steps: S1, according to the computing array scale of target integrated circuit and the interconnect mode of described computing array, obtain the first maximum data width that described target integrated circuit can run, wherein, described computing array comprises multiple basic computational ele-ment (PE), and described PE comprises the multiple MUX (MUX) be connected with ALU and the register be connected with described ALU; S2, according to described first maximum data width, obtains the second maximum data width needed when described target integrated circuit runs cryptographic algorithm; S3, divides into groups to needing the multiple registers carrying out input and output exchange according to described second maximum data width; S4, transforms the multiple register places circuit often organized, and wherein, in improved circuit, the input end of each described register is connected with output multi-channel selector switch OUT_MUX with input MUX IN_MUX respectively with output terminal; S5, determines that the multiple described IN_MUX that multiple register places circuit of often organizing is corresponding and multiple described OUT_MUX carries out the domination number of data selection; And S6, the data selection rule of the multiple described IN_MUX that multiple register places circuit of often organizing is corresponding and multiple described OUT_MUX is determined according to described domination number.
The beneficial effect of the fault-resistant injection attacks method of exchanging according to the register input and output of the embodiment of the present invention is: the register of storage encryption algorithm data can be made no longer fixing, reduce fault and be successfully injected into probability in circuit, improve the security of circuit.
Further, in one embodiment of the invention, in improved circuit, multiple ALU that each described IN_MUX is corresponding with the multiple registers often organized respectively are connected, and each described OUT_MUX is also connected with the output terminal of other register often organized respectively.
Further, in one embodiment of the invention, described domination number is produced by randomizer RNG.
Further, in one embodiment of the invention, describedly determine that the data selection rule of the multiple described IN_MUX that multiple register places circuit of often organizing is corresponding and multiple described OUT_MUX is specially according to described domination number: the data selection rule determining the multiple described IN_MUX that multiple register places circuit of often organizing is corresponding according to described domination number; And the data selection rule of corresponding multiple described OUT_MUX is determined according to the data selection rule of multiple described IN_MUX.
Further, in one embodiment of the invention, the data selection rule of the multiple described OUT_MUX that the multiple register places circuit often organized is corresponding keeps synchronous with the data selection rule of multiple described IN_MUX and changes.
Further, in one embodiment of the invention, determine needing the described multiple register carrying out input and output exchange to be to divide into groups by row or by column split according to the interconnect mode of described computing array.
Further, in one embodiment of the invention, the described multiple registers carrying out input and output exchange that need are the register storing described ALU result of calculation.
To achieve these goals, according to the fault-resistant injection attacks device that the register input and output of the embodiment of the present invention are exchanged, comprise: the first maximum data width acquisition module, for according to the computing array scale of target integrated circuit and the interconnect mode of described computing array, obtain the first maximum data width that described target integrated circuit can run, wherein, described computing array comprises multiple PE, and described PE comprises the multiple MUX be connected with ALU and the register be connected with described ALU; Second maximum data width acquisition module, for according to described first maximum data width, obtains the second maximum data width needed when described target integrated circuit runs cryptographic algorithm; Grouping module, for dividing into groups to needing the multiple registers carrying out input and output exchange according to described second maximum data width; Circuit modification module, for transforming the multiple register places circuit often organized, wherein, in improved circuit, the input end of each described register is connected with output multi-channel selector switch OUT_MUX with input MUX IN_MUX respectively with output terminal; Domination number determination module, for determining that the multiple described IN_MUX that multiple register places circuit of often organizing is corresponding and multiple described OUT_MUX carries out the domination number of data selection; And data selection rule determination module, the data selection rule of the multiple described IN_MUX that the multiple register places circuit for determining often to organize according to described domination number is corresponding and multiple described OUT_MUX.
Further, in one embodiment of the invention, in improved circuit, multiple ALU that each described IN_MUX is corresponding with the multiple registers often organized respectively are connected, and each described OUT_MUX is also connected with the output terminal of other register often organized respectively.
Further, in one embodiment of the invention, described domination number is produced by randomizer RNG.
Further, in one embodiment of the invention, described data selection rule determination module is specifically for the data selection rule of determining the multiple described IN_MUX that multiple register places circuit of often organizing is corresponding according to described domination number; And the data selection rule of corresponding multiple described OUT_MUX is determined according to the data selection rule of multiple described IN_MUX.
Further, in one embodiment of the invention, the data selection rule of the multiple described OUT_MUX that the multiple register places circuit often organized is corresponding keeps synchronous with the data selection rule of multiple described IN_MUX and changes.
Further, in one embodiment of the invention, described grouping module specifically for: determine needing the described multiple register carrying out input and output exchange to be to divide into groups by row or by column split according to the interconnect mode of described computing array.
Further, in one embodiment of the invention, the described multiple registers carrying out input and output exchange that need are the register storing described ALU result of calculation.
The beneficial effect of the fault-resistant injection attacks device exchanged according to the register input and output of the embodiment of the present invention is: the register of storage encryption algorithm data can be made no longer fixing, reduce fault and be successfully injected into probability in circuit, improve the security of circuit.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of the fault-resistant injection attacks method of exchanging according to the register input and output of the embodiment of the present invention;
Fig. 2 is computing array schematic diagram in the fault-resistant injection attacks method of exchanging according to the register input and output of the present invention's specific embodiment;
Fig. 3 is register grouping schematic diagram in the fault-resistant injection attacks method of exchanging according to the register input and output of the present invention's specific embodiment;
Fig. 4 is the data selection rule schematic diagram of IN_MUX and OUT_MUX in the fault-resistant injection attacks method of exchanging according to the register input and output of the present invention's specific embodiment;
Fig. 5 is the operating diagram of PE after transformation in the fault-resistant injection attacks method of exchanging according to the register input and output of the present invention's specific embodiment; And
Fig. 6 is the block diagram of the fault-resistant injection attacks device exchanged according to the register input and output of the embodiment of the present invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Be exemplary below by the embodiment be described with reference to the drawings, be intended to for explaining the present invention, and can not limitation of the present invention be interpreted as.
Below with reference to the accompanying drawings the fault-resistant injection attacks method that the register input and output describing the embodiment of the present invention are exchanged and the fault-resistant injection attacks device that register input and output are exchanged.
As shown in Figure 1, according to the fault-resistant injection attacks method that the register input and output of the embodiment of the present invention are exchanged, comprise the following steps:
S1, according to the computing array scale of target integrated circuit and the interconnect mode of computing array, obtain the first maximum data width that target integrated circuit can run, wherein, computing array comprises multiple PE, PE and comprises the multiple MUX be connected with ALU and the register be connected with ALU.
In one embodiment of the invention, the first maximum data width is designated as w
i.In order to express easily, w
ican in units of the number of PE.Therefore w
idepend on the interconnect mode of computing array scale and computing array.Such as, arrange if computing array is 16 row 32, and adopt the interconnected this one-way data interconnect mode of adjacent lines in the ranks, namely the data of every a line calculated after can pass to next line, so now w
i=32 (i.e. the columns of array).If interconnect mode, so w between the row of computing array employing adjacent column
ifor the line number of array, i.e. w
i=16.
Fig. 2 is computing array schematic diagram in the fault-resistant injection attacks method of exchanging according to the register input and output of the present invention's specific embodiment.As shown in Figure 2, computing array is made up of multiple PE and interconnection line therebetween, show in figure for an array scale be the computing array of 4 × 4 (4 row 4 arrange), coupled together by interconnection line between PE.Selected the data required calculation during PE work by MUX, afterwards data are passed to ALU and carry out computing, the structure of computing is stored in register, and in last register, data pass to other PE by interconnection line or export as end product.
S2, according to the first maximum data width, obtains the second maximum data width needed when target integrated circuit runs cryptographic algorithm.
In one embodiment of the invention, the second maximum data width is designated as w
a, w
aalso can in units of the number of PE.Such as concerning conventional AES-128 cryptographic algorithm, each operation of cryptographic algorithm is all for 128 bit packet data, and so the maximum data width of each step of this cryptographic algorithm is 128 bits.The process width supposing PE is 8 bits, obtains w
a=128 bit=16, bit/8.
S3, divides into groups to needing the multiple registers carrying out input and output exchange according to the second maximum data width.
The fault-resistant injection attacks method that register input and output of the present invention are exchanged may be used in cipher processor.In order to realize effective exchange of register input and output, cipher processor needs some register to divide into groups, and particularly, in one embodiment of the invention, needs the multiple registers carrying out input and output exchange can be the register of storage ALU result of calculation.It should be noted that, cipher processor as required also can using other register in computing array as the register needing grouping.
Further, in one embodiment of the invention, can determine needing the multiple registers carrying out input and output exchange to be to divide into groups by row or by column split according to the interconnect mode of computing array.Particularly, in one embodiment of the invention, if computing array adopts the interconnected this one-way data interconnect mode of adjacent lines in the ranks, multiple register grouping is divided into groups by row.Otherwise if interconnect mode between the row of computing array employing adjacent column, then multiple register divides into groups by row.Further, in one embodiment of the invention, if be divide into groups by row during the grouping of multiple register, so illustrate that the every a line of computing array has w
iindividual register stores the result of calculation of ALU.The the second maximum data width needed when running cryptographic algorithm due to target integrated circuit is w
a, for ensureing independent variation between enciphered data, the register of same a line is divided into w
agroup.During grouping, the register of same a line is numbered 1-w from left to right
i, organized into groups successively by the register of same a line afterwards, the register being such as numbered 1 enrolls the 1st group, and the register being numbered 2 enrolls the 2nd group ..., be numbered w
athe register of+1 also enrolls the 1st group, until all organized into groups by all registers, then uses the same method the register grouping of storage ALU result of calculation all in computing array.
Fig. 3 is register grouping schematic diagram in the fault-resistant injection attacks method of exchanging according to the register input and output of the present invention's specific embodiment.Have 8 PE in Fig. 3, numbering corresponds to PE1-PE8 respectively.Array shown in Fig. 3 is 2 × 4 (2 row 4 arrange) array, supposes that this array adopts the interconnect mode in the ranks of adjacent lines, then w
i=4, thus need divide into groups by row during register grouping.To the register number of dividing into groups be needed to be register 1-1 ..., register 1-4, register 2-1 ..., register 2-4.In register number, first digit represents register-bit is in which row, and second digit represents the numbering of register in this row.The the second maximum data width w needed when hypothetical target integrated circuit running cryptographic algorithm
abe 2.The result of register grouping is that it is one group that register 1-1, register 1-3 compile, and packet numbering is 1-1.It is one group that register 1-2, register 1-4 compile, and packet numbering is 1-2.The grouping situation of the second row is similar, when just packet numbering first digit is 2, is represented as the grouping of the second row.
S4, transforms the multiple register places circuit often organized, and wherein, in improved circuit, the input end of each register is connected with output multi-channel selector switch OUT_MUX with input MUX IN_MUX respectively with output terminal.
Further, in one embodiment of the invention, in improved circuit, multiple ALU that each IN_MUX can be corresponding with the multiple registers often organized respectively are connected, and each OUT_MUX can also be connected with the output terminal of other register often organized respectively.Particularly, the input of the corresponding IN_MUX of each register comes from the input that the same all registers (comprising self) organized are original with this register, and the data being finally input to register are selected by corresponding IN_MUX.The input of the corresponding OUT_MUX of each register comes from and the output of this register with all registers (comprising self) organized, and final OUT_MUX selects one and outputs in the original output target of register from the output of all registers with group.
S5, determines that multiple IN_MUX that multiple register places circuit of often organizing is corresponding and multiple OUT_MUX carries out the domination number of data selection.
In one embodiment of the invention, domination number can be produced by randomizer RNG.Namely multiple IN_MUX that the multiple register places circuit often organized is corresponding and multiple OUT_MUX carries out data selection and is driven by randomizer (RNG), it should be noted that, multiple IN_MUX that the multiple register places circuit often organized is corresponding and multiple OUT_MUX also can be driven by miscellaneous part, but in order to reach the effect of fault-resistant injection attacks, the domination number and the MUX control signal that are supplied to multiple IN_MUX and multiple OUT_MUX need to have certain randomness.Most cryptographic algorithm all adopt the account form of wheel iteration, and namely by the security performing and improve cryptographic algorithm that iterates to series of computation operation, performing once needs the operation iterated to be called to take turns.Therefore, suppose in the present invention, whenever cryptographic algorithm executes an operation taken turns, the MUX control signal of RNG exports and also changes once, in fact, as long as the generation speed of the MUX control signal of RNG meets the demand of data processing, namely during cipher processor process different pieces of information, MUX control signal changes.
S6, determines the data selection rule of multiple IN_MUX that multiple register places circuit of often organizing is corresponding and multiple OUT_MUX according to domination number.
Claim in the present invention register be not connected with IN_MUX before input source for input source, the output object component before not being connected with OUT_MUX is named and exports target.In order to ensure that encryption process is correctly carried out, in one embodiment of the invention, the data selection rule of multiple OUT_MUX that the multiple register places circuit often organized is corresponding can keep synchronous change with the data selection rule of multiple IN_MUX, so just can make still can pass to output target with the input source data of multiple register in group.
Further, in one embodiment of the invention, determine that the data selection rule of multiple IN_MUX that multiple register places circuit of often organizing is corresponding and multiple OUT_MUX and step S6 are specifically as follows according to domination number:
S61, determines the data selection rule of multiple IN_MUX that multiple register places circuit of often organizing is corresponding according to domination number.
Suppose that the quantity of multiple register in a certain group is n, then the quantity of multiple IN_MUX is n.The input of IN_MUX come from to should register with the original input of all registers (comprising self) organized, namely the quantity of input source is also n.When not adding restriction, each IN_MUX can select the data of any one in this n input source to export, so just likely there is the situation (namely there is some input sources does not have IN_MUX to select the data of this input source as output) of input source loss of data, so during design IN_MUX data selection rule, need to ensure that the data of each input source at any time have an IN_MUX select and export, simultaneously in order to reduce the complexity of control, the data output setting this n IN_MUX possible is chosen as n kind, at this moment the situation that this n kind of artificial appointment is possible is needed, the data selection rule of multiple IN_MUX that the multiple register places circuit then often organized is corresponding.
S62, determines the data selection rule of corresponding multiple OUT_MUX according to the data selection rule of multiple IN_MUX.
Fig. 4 is the data selection rule schematic diagram of IN_MUX and OUT_MUX in the fault-resistant injection attacks method of exchanging according to the register input and output of the present invention's specific embodiment.As shown in Figure 4, after register grouping, first need to carry out certain transformation to register place circuit structure in group, suppose to include 3 registers, register 1, register 2 and register 3 in the grouping of certain register.For register 1, before not transforming, the operation result of ALU1 is stored in register 1, and finally exports as OUT1.After transformation, register 1 input end and output terminal have met an IN_MUX1 and OUT_MUX1 respectively.The input data of IN_MUX1, from ALU1-ALU3, export data to register 1.The input data of OUT_MUX1, from register 1-register 3, export and export as OUT1.The control signal that IN_MUX1 and OUT_MUX1 carries out data selection is come all certainly in the output of RNG, and control signal and domination number are Integer N.The transformation at register 2 and register 3 place is similar, below repeats no more.
Further, during owing to determining that the data selection of IN_MUX and OUT_MUX is regular, regular according to IN_MUX data selection rule settings with multiple OUT_MUX data selections that register in group is corresponding, therefore the data selection rule of the multiple IN_MUX first needing multiple register places circuit of determining often to organize corresponding, the quantity of data selection rule is 3.As shown in Figure 4, the input of IN_MUX1-IN_MUX3 is from ALU1-ALU3.When not adding restriction, each IN_MUX can select the data of any one in these 3 ALU to export, so just likely there is the situation (namely there is some ALU does not have IN_MUX to select these ALU data as output) of ALU loss of data, so during design IN_MUX data selection rule, need to ensure that the data of each ALU at any time have an IN_MUX select and export, simultaneously in order to reduce the complexity of control, the data output setting these 3 IN_MUX possible is chosen as 3 kinds.At this moment need the situation that artificial appointment these 3 kinds is possible, in Fig. 4, illustrate 3 kinds of IN_MUX data selection situations.The Data Source that in the first situation, IN_MUX1, IN_MUX2, IN_MUX3 select is respectively ALU1, ALU2, ALU3.The Data Source that in the second situation, IN_MUX1, IN_MUX2, IN_MUX3 select is respectively ALU2, ALU3, ALU1.The Data Source that in the third situation, IN_MUX1, IN_MUX2, IN_MUX3 select is respectively ALU3, ALU1, ALU2.IN_MUX1, IN_MUX2, IN_MUX3 data selection rule can be obtained by these three kinds of situations and correspond to N mod 3+1, (N+1) mod 3+1, (N+2) mod 3+1 respectively.According to the data selection rule obtained, no matter what value MUX control signal N gets, and final IN_MUX data selection is all one of above-mentioned three kinds of situations.
In addition, constant in order to ensure the result of calculation outgoing position of ALU, such as: the result of ALU1 exports as OUT1.The data selection situation of OUT_MUX needs to determine according to the data selection situation of IN_MUX.The first data selection situation of IN_MUX is regular situation, therefore is described for the second data selection situation of IN_MUX.In the second data selection situation, the result of ALU1, stored in register 3, exports as OUT1 to make data in ALU1, OUT_MUX1 needs the data of mask register 3, similar, OUT_MUX2 needs the data of mask register 1, and OUT_MUX3 needs the data of mask register 2.According to the data selection situation of OUT_MUX, the data selection rule that can obtain OUT_MUX1, OUT_MUX2, OUT_MUX3 corresponds to (-N) mod 3+1, (-N+1) mod 3+1, (-N+2) mod 3+1 respectively.
The operating diagram of PE after transformation in the fault-resistant injection attacks method that Fig. 5 does not exchange according to the register input and output of the present invention's specific embodiment.Show in Fig. 5 be two registers as one group, register input and output exchange schematic diagram, wherein MUX control signal be RNG produce random bit (1 or 0).When the random number that RNG produces is 0, register 1 stores the result of calculation of ALU1, and register 2 stores the result of calculation of ALU2.When the random number that RNG produces is 1, register 1 stores the result of calculation of ALU2, and register 2 stores the result of calculation of ALU1, thus makes ALU result of calculation memory location there occurs change, reduce fault and be successfully injected into probability in circuit, improve the security of circuit.
The invention has the beneficial effects as follows: by adding the control that MUX is carried out the actual input source of register and exported target at the input end of register and output terminal, thus make the register of storage encryption algorithm data no longer fixing, reduce fault and be successfully injected into probability in circuit, improve the security of circuit.
In order to realize above-described embodiment, the present invention also proposes the fault-resistant injection attacks device that a kind of register input and output are exchanged, as shown in Figure 6, the fault-resistant injection attacks device that these register input and output are exchanged comprises: the first maximum data width acquisition module 10, second maximum data width acquisition module 20, grouping module 30, circuit modification module 40, domination number determination module 50 and data selection rule determination module 60.Wherein, first maximum data width acquisition module 10 is for according to the computing array scale of target integrated circuit and the interconnect mode of computing array, obtain the first maximum data width that target integrated circuit can run, wherein, computing array comprises multiple PE, PE and comprises the MUX be connected with ALU and the register be connected with ALU.Second maximum data width acquisition module 20, for according to the first maximum data width, obtains the second maximum data width needed when target integrated circuit runs cryptographic algorithm.Grouping module 30 is for dividing into groups to needing the multiple registers carrying out input and output exchange according to the second maximum data width.Circuit modification module 40 is for transforming the multiple register places circuit often organized, and wherein, in improved circuit, the input end of each register is connected with output multi-channel selector switch OUT_MUX with input MUX IN_MUX respectively with output terminal.Domination number determination module 50 is for determining that multiple IN_MUX that multiple register places circuit of often organizing is corresponding and multiple OUT_MUX carries out the domination number of data selection.Data selection rule determination module 60 is for the data selection rule of multiple IN_MUX corresponding to multiple register places circuit of determining often to organize according to domination number and multiple OUT_MUX.
In one embodiment of the invention, the first maximum data width is designated as w
i.In order to express easily, w
ican in units of the number of PE.Therefore w
idepend on the interconnect mode of computing array scale and computing array.Such as, arrange if computing array is 16 row 32, and adopt the interconnected this one-way data interconnect mode of adjacent lines in the ranks, namely the data of every a line calculated after can pass to next line, so now w
i=32 (i.e. the columns of array).If interconnect mode, so w between the row of computing array employing adjacent column
ifor the line number of array, i.e. w
i=16.In another embodiment of the present invention, the second maximum data width is designated as w
a, w
aalso can in units of the number of PE.Such as concerning conventional AES-128 cryptographic algorithm, each operation of cryptographic algorithm is all for 128 bit packet data, and so the maximum data width of each step of this cryptographic algorithm is 128 bits.The process width supposing PE is 8 bits, obtains w
a=128 bit=16, bit/8.
The fault-resistant injection attacks device that register input and output of the present invention are exchanged may be used in cipher processor.In order to realize effective exchange of register input and output, cipher processor needs some register to divide into groups, and particularly, in one embodiment of the invention, needs the multiple registers carrying out input and output exchange can be the register of storage ALU result of calculation.It should be noted that, other register in computing array also can be needed the register of grouping by cipher processor as required as grouping module 30.Further, in one embodiment of the invention, grouping module 30 is specifically for determining according to the interconnect mode of computing array needing the multiple registers carrying out input and output exchange to be to divide into groups by row or by column split.
Particularly, in one embodiment of the invention, if computing array adopts the interconnected this one-way data interconnect mode of adjacent lines in the ranks, multiple register grouping is divided into groups by row.Otherwise if interconnect mode between the row of computing array employing adjacent column, then multiple register divides into groups by row.Further, in one embodiment of the invention, if be divide into groups by row during the grouping of multiple register, so illustrate that the every a line of computing array has w
iindividual register stores the result of calculation of ALU.The the second maximum data width needed when running cryptographic algorithm due to target integrated circuit is w
a, for ensureing independent variation between enciphered data, the register of same a line is divided into w
agroup.During grouping, the register of same a line is numbered 1-w from left to right
i, organized into groups successively by the register of same a line afterwards, the register being such as numbered 1 enrolls the 1st group, and the register being numbered 2 enrolls the 2nd group ..., be numbered w
athe register of+1 also enrolls the 1st group, until all organized into groups by all registers, then uses the same method the register grouping of storage ALU result of calculation all in computing array.
Further, in one embodiment of the invention, in improved circuit, multiple ALU that each IN_MUX is corresponding with the multiple registers often organized respectively are connected, and each OUT_MUX is also connected with the output terminal of other register often organized respectively.Particularly, the input of the corresponding IN_MUX of each register comes from the input that the same all registers (comprising self) organized are original with this register, and the data being finally input to register are selected by corresponding IN_MUX.The input of the corresponding OUT_MUX of each register comes from and the output of this register with all registers (comprising self) organized, and final OUT_MUX selects one and outputs in the original output target of register from the output of all registers with group.
Further, in one embodiment of the invention, domination number is produced by randomizer RNG.Namely multiple IN_MUX that the multiple register places circuit often organized is corresponding and multiple OUT_MUX carries out data selection and is driven by randomizer (RNG), it should be noted that, multiple IN_MUX that the multiple register places circuit often organized is corresponding and multiple OUT_MUX also can be driven by miscellaneous part, but in order to reach the effect of fault-resistant injection attacks, the domination number and the MUX control signal that are supplied to multiple IN_MUX and multiple OUT_MUX need to have certain randomness.Most cryptographic algorithm all adopt the account form of wheel iteration, and namely by the security performing and improve cryptographic algorithm that iterates to series of computation operation, performing once needs the operation iterated to be called to take turns.Therefore, suppose in the present invention, whenever cryptographic algorithm executes an operation taken turns, the MUX control signal of RNG exports and also changes once, in fact, as long as the generation speed of the MUX control signal of RNG meets the demand of data processing, namely during cipher processor process different pieces of information, MUX control signal changes.
Claim in the present invention register be not connected with IN_MUX before input source for input source, the output object component before not being connected with OUT_MUX is named and exports target.In order to ensure that encryption process is correctly carried out, in one embodiment of the invention, the data selection rule of multiple OUT_MUX that the multiple register places circuit often organized is corresponding can keep synchronous change with the data selection rule of multiple IN_MUX, so just can make still can pass to output target with the input source data of multiple register in group.
Further, in one embodiment of the invention, data selection rule determination module 60 specifically for the data selection rule of multiple IN_MUX corresponding to multiple register places circuit of determining often to organize according to domination number, and determines the data selection rule of corresponding multiple OUT_MUX according to the data selection rule of multiple IN_MUX.Suppose that the quantity of multiple register in a certain group is n, then the quantity of multiple IN_MUX is n.The input of IN_MUX come from to should register with the original input of all registers (comprising self) organized, namely the quantity of input source is also n.When not adding restriction, each IN_MUX can select the data of any one in this n input source to export, so just likely there is the situation (namely there is some input sources does not have IN_MUX to select the data of this input source as output) of input source loss of data, so during design IN_MUX data selection rule, need to ensure that the data of each input source at any time have an IN_MUX select and export, simultaneously in order to reduce the complexity of control, the data output setting this n IN_MUX possible is chosen as n kind, at this moment the situation that this n kind of artificial appointment is possible is needed, the data selection rule of multiple IN_MUX that the multiple register places circuit then often organized is corresponding.
The invention has the beneficial effects as follows: by adding the control that MUX is carried out the actual input source of register and exported target at the input end of register and output terminal, thus make the register of storage encryption algorithm data no longer fixing, reduce fault and be successfully injected into probability in circuit, improve the security of circuit.
In the description of this instructions, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present invention or example.In this manual, to the schematic representation of above-mentioned term not must for be identical embodiment or example.And the specific features of description, structure, material or feature can combine in one or more embodiment in office or example in an appropriate manner.In addition, when not conflicting, the feature of the different embodiment described in this instructions or example and different embodiment or example can carry out combining and combining by those skilled in the art.
In addition, term " first ", " second " only for describing object, and can not be interpreted as instruction or hint relative importance or imply the quantity indicating indicated technical characteristic.Thus, be limited with " first ", the feature of " second " can express or impliedly comprise at least one this feature.In describing the invention, the implication of " multiple " is at least two, such as two, three etc., unless otherwise expressly limited specifically.
Describe and can be understood in process flow diagram or in this any process otherwise described or method, represent and comprise one or more for realizing the module of the code of the executable instruction of the step of specific logical function or process, fragment or part, and the scope of the preferred embodiment of the present invention comprises other realization, wherein can not according to order that is shown or that discuss, comprise according to involved function by the mode while of basic or by contrary order, carry out n-back test, this should understand by embodiments of the invention person of ordinary skill in the field.
In flow charts represent or in this logic otherwise described and/or step, such as, the sequencing list of the executable instruction for realizing logic function can be considered to, may be embodied in any computer-readable medium, for instruction execution system, device or equipment (as computer based system, comprise the system of processor or other can from instruction execution system, device or equipment instruction fetch and perform the system of instruction) use, or to use in conjunction with these instruction execution systems, device or equipment.With regard to this instructions, " computer-readable medium " can be anyly can to comprise, store, communicate, propagate or transmission procedure for instruction execution system, device or equipment or the device that uses in conjunction with these instruction execution systems, device or equipment.The example more specifically (non-exhaustive list) of computer-readable medium comprises following: the electrical connection section (electronic installation) with one or more wiring, portable computer diskette box (magnetic device), random access memory (RAM), ROM (read-only memory) (ROM), erasablely edit ROM (read-only memory) (EPROM or flash memory), fiber device, and portable optic disk ROM (read-only memory) (CDROM).In addition, computer-readable medium can be even paper or other suitable media that can print described program thereon, because can such as by carrying out optical scanning to paper or other media, then carry out editing, decipher or carry out process with other suitable methods if desired and electronically obtain described program, be then stored in computer memory.
Should be appreciated that each several part of the present invention can realize with hardware, software, firmware or their combination.In the above-described embodiment, multiple step or method can with to store in memory and the software performed by suitable instruction execution system or firmware realize.Such as, if realized with hardware, the same in another embodiment, can realize by any one in following technology well known in the art or their combination: the discrete logic with the logic gates for realizing logic function to data-signal, there is the special IC of suitable combinational logic gate circuit, programmable gate array (PGA), field programmable gate array (FPGA) etc.
Those skilled in the art are appreciated that realizing all or part of step that above-described embodiment method carries is that the hardware that can carry out instruction relevant by program completes, described program can be stored in a kind of computer-readable recording medium, this program perform time, step comprising embodiment of the method one or a combination set of.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing module, also can be that the independent physics of unit exists, also can be integrated in a module by two or more unit.Above-mentioned integrated module both can adopt the form of hardware to realize, and the form of software function module also can be adopted to realize.If described integrated module using the form of software function module realize and as independently production marketing or use time, also can be stored in a computer read/write memory medium.
The above-mentioned storage medium mentioned can be ROM (read-only memory), disk or CD etc.Although illustrate and describe embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, and those of ordinary skill in the art can change above-described embodiment within the scope of the invention, revises, replace and modification.
Claims (14)
1. a fault-resistant injection attacks method for register input and output exchange, is characterized in that, comprise the following steps:
S1, according to the computing array scale of target integrated circuit and the interconnect mode of described computing array, obtain the first maximum data width that described target integrated circuit can run, wherein, described computing array comprises multiple basic computational ele-ment PE, and described PE comprises the multiple MUX MUX be connected with arithmetic logic unit alu and the register be connected with described ALU;
S2, according to described first maximum data width, obtains the second maximum data width needed when described target integrated circuit runs cryptographic algorithm;
S3, divides into groups to needing the multiple registers carrying out input and output exchange according to described second maximum data width;
S4, transforms the multiple register places circuit often organized, and wherein, in improved circuit, the input end of each described register is connected with output multi-channel selector switch OUT_MUX with input MUX IN_MUX respectively with output terminal;
S5, determines that the multiple described IN_MUX that multiple register places circuit of often organizing is corresponding and multiple described OUT_MUX carries out the domination number of data selection; And
S6, determines the data selection rule of the multiple described IN_MUX that multiple register places circuit of often organizing is corresponding and multiple described OUT_MUX according to described domination number.
2. the fault-resistant injection attacks method of register input and output exchange as claimed in claim 1, it is characterized in that, in improved circuit, multiple ALU that each described IN_MUX is corresponding with the multiple registers often organized respectively are connected, and each described OUT_MUX is also connected with the output terminal of other register often organized respectively.
3. the fault-resistant injection attacks method of register input and output exchange as claimed in claim 1, it is characterized in that, described domination number is produced by randomizer RNG.
4. the fault-resistant injection attacks method of register input and output exchange as claimed in claim 1, it is characterized in that, describedly determine that the data selection rule of the multiple described IN_MUX that multiple register places circuit of often organizing is corresponding and multiple described OUT_MUX is specially according to described domination number:
The data selection rule of the multiple described IN_MUX that multiple register places circuit of often organizing is corresponding is determined according to described domination number; And
The data selection rule of corresponding multiple described OUT_MUX is determined according to the data selection rule of multiple described IN_MUX.
5. the fault-resistant injection attacks method of register input and output exchange as claimed in claim 4, it is characterized in that, the data selection rule of the multiple described OUT_MUX that the multiple register places circuit often organized is corresponding keeps synchronous with the data selection rule of multiple described IN_MUX and changes.
6. the register input and output as claimed in claim 1 fault-resistant injection attacks method of exchanging, determines needing the described multiple register carrying out input and output exchange to be to divide into groups by row or by column split according to the interconnect mode of described computing array.
7. the fault-resistant injection attacks method of register input and output exchange as claimed in claim 6, it is characterized in that, the described multiple registers carrying out input and output exchange that need are the register storing described ALU result of calculation.
8. a fault-resistant injection attacks device for register input and output exchange, is characterized in that, comprising:
First maximum data width acquisition module, for according to the computing array scale of target integrated circuit and the interconnect mode of described computing array, obtain the first maximum data width that described target integrated circuit can run, wherein, described computing array comprises multiple basic computational ele-ment PE, and described PE comprises the multiple MUX MUX be connected with arithmetic logic unit alu and the register be connected with described ALU;
Second maximum data width acquisition module, for according to described first maximum data width, obtains the second maximum data width needed when described target integrated circuit runs cryptographic algorithm;
Grouping module, for dividing into groups to needing the multiple registers carrying out input and output exchange according to described second maximum data width;
Circuit modification module, for transforming the multiple register places circuit often organized, wherein, in improved circuit, the input end of each described register is connected with output multi-channel selector switch OUT_MUX with input MUX IN_MUX respectively with output terminal;
Domination number determination module, for determining that the multiple described IN_MUX that multiple register places circuit of often organizing is corresponding and multiple described OUT_MUX carries out the domination number of data selection; And
Data selection rule determination module, the data selection rule of the multiple described IN_MUX that the multiple register places circuit for determining often to organize according to described domination number is corresponding and multiple described OUT_MUX.
9. the fault-resistant injection attacks device of register input and output exchange as claimed in claim 8, it is characterized in that, in improved circuit, multiple ALU that each described IN_MUX is corresponding with the multiple registers often organized respectively are connected, and each described OUT_MUX is also connected with the output terminal of other register often organized respectively.
10. the fault-resistant injection attacks device of register input and output exchange as claimed in claim 8, it is characterized in that, described domination number is produced by randomizer RNG.
The fault-resistant injection attacks device that 11. register input and output as claimed in claim 8 are exchanged, is characterized in that, described data selection rule determination module specifically for:
The data selection rule of the multiple described IN_MUX that multiple register places circuit of often organizing is corresponding is determined according to described domination number; And
The data selection rule of corresponding multiple described OUT_MUX is determined according to the data selection rule of multiple described IN_MUX.
The fault-resistant injection attacks device that 12. register input and output as claimed in claim 11 are exchanged, it is characterized in that, the data selection rule of the multiple described OUT_MUX that the multiple register places circuit often organized is corresponding keeps synchronous with the data selection rule of multiple described IN_MUX and changes.
The fault-resistant injection attacks device that 13. register input and output as claimed in claim 8 are exchanged, is characterized in that, described grouping module specifically for:
Determine needing the described multiple register carrying out input and output exchange to be to divide into groups by row or by column split according to the interconnect mode of described computing array.
The fault-resistant injection attacks device that 14. register input and output as claimed in claim 13 are exchanged, it is characterized in that, the described multiple registers carrying out input and output exchange that need are the register storing described ALU result of calculation.
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