CN104681489A - Forming method of CMOS (complementary metal-oxide-semiconductor) transistor - Google Patents
Forming method of CMOS (complementary metal-oxide-semiconductor) transistor Download PDFInfo
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- CN104681489A CN104681489A CN201310612561.2A CN201310612561A CN104681489A CN 104681489 A CN104681489 A CN 104681489A CN 201310612561 A CN201310612561 A CN 201310612561A CN 104681489 A CN104681489 A CN 104681489A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 162
- 239000000463 material Substances 0.000 claims abstract description 120
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- 238000005530 etching Methods 0.000 claims description 25
- 239000007789 gas Substances 0.000 claims description 22
- 238000005137 deposition process Methods 0.000 claims description 16
- 238000004544 sputter deposition Methods 0.000 claims description 14
- 238000001039 wet etching Methods 0.000 claims description 13
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- 239000000243 solution Substances 0.000 claims description 12
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 229910052786 argon Inorganic materials 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000011259 mixed solution Substances 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 229910010038 TiAl Inorganic materials 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention provides a forming method of a CMOS (complementary metal-oxide-semiconductor) transistor. The forming method comprises the following steps that a semiconductor substrate is provided, and the semiconductor substrate comprises an NMOS (N-channel metal oxide semiconductor) region, a PMOS (P-channel metal oxide semiconductor) region, a first groove positioned in the surface of the NMOS region and a second groove positioned in the surface of the PMOS region; a grid dielectric material layer, a first metal layer, a second metal layer and a third metal layer are sequentially formed on the surfaces of the inner walls of the first groove and the second groove and the surface of a dielectric layer; covering material layers filling into the first groove and the second groove are formed, the materials of the covering material layers are insulation dielectric materials; the covering material layer on the NMOS region is removed; the covering material layer at partial thickness in the second groove is removed for forming a covering layer; a third metal layer and a second metal layer in the first groove, above the dielectric layer as well as above the covering layer and in the second groove are removed; the covering layer is removed; a first grid electrode and a second grid electrode are formed in the first groove and the second groove. The forming method of the CMOS transistor has the advantage that the performance of the CMOS transistor can be improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of CMOS transistor.
Background technology
Along with improving constantly of semiconductor device integrated level, the reduction of technology node, traditional gate dielectric layer is constantly thinning, and transistor leakage amount increases thereupon, causes the problems such as semiconductor device power wastage.For solving the problem, prior art provides a kind of solution metal gates being substituted polysilicon gate.Wherein, " rear grid (gate last) " technique is the main technique forming high-K metal gate gated transistors.
Existing employing post tensioned unbonded prestressed concrete technique forms the method for high-K metal gate gated transistors, comprise: Semiconductor substrate is provided, described Semiconductor substrate be formed with pseudo-grid structure and be positioned in described Semiconductor substrate and cover the interlayer dielectric layer of described pseudo-grid structure, described pseudo-grid structure comprises the dummy grid on pseudo-gate dielectric layer and the described pseudo-gate dielectric layer surface being positioned at described semiconductor substrate surface, and the surface of described interlayer dielectric layer flushes with pseudo-grid body structure surface; Groove is formed after removing described pseudo-grid structure; In described groove, form high-K gate dielectric layer and metal level successively, described metal level fills full groove, as the metal gates of transistor.
In order to meet the needs of high performance device, metal gate also should have gate work-function regulating power.The work-function layer of individual layer or multilayer can be formed between metal gate electrode and gate dielectric layer, be used for regulating the threshold voltage of nmos pass transistor or PMOS transistor.The gate work-function of PMOS transistor and nmos pass transistor is different, so in CMOS transistor, often needs to form different work-function layer respectively for nmos pass transistor and PMOS transistor.Usually, prior art simultaneously forms identical work-function layer at nmos pass transistor and PMOS transistor, and described work-function layer comprises general work-function layer between nmos pass transistor and PMOS transistor, and for the work-function layer of PMOS transistor; And then mask layer is formed in the work-function layer in PMOS transistor region, with described mask layer for mask, remove the PMOS work-function layer in NMOS area, thus make nmos pass transistor and PMOS transistor have different work-function layer.Usually adopt the organic material such as photoresist or bottom anti-reflection layer as the material of mask layer in prior art, to improve filling effect.But organic material is difficult to remove totally, so when the described mask layer of follow-up removal, have mask material and remain, affect the quality of the grid formed in subsequent technique, affect the performance of CMOS transistor.
So the performance of the CMOS transistor that prior art is formed needs further to be improved.
Summary of the invention
The problem that the present invention solves is to provide the formation method of CMOS transistor, improves the performance of CMOS transistor.
For solving the problem, the invention provides a kind of formation method of CMOS transistor, comprise: Semiconductor substrate is provided, described Semiconductor substrate comprises NMOS area and PMOS area, described semiconductor substrate surface has dielectric layer, in the dielectric layer on described NMOS area surface, there is the first groove, in the dielectric layer on described PMOS area surface, there is the second groove; At the 3rd metal level that inner wall surface and the dielectric layer surface of described first groove and the second groove form gate dielectric material layer successively, are positioned at the first metal layer on gate dielectric material layer surface, are positioned at second metal level on described the first metal layer surface, are positioned at described second layer on surface of metal; Form the layer of cover material of filling described first groove and the second groove, the material of described layer of cover material is insulating dielectric materials; Remove the layer of cover material in NMOS area; Remove the layer of cover material that the second inside grooves divides thickness, form cover layer, make the tectal surface in described second groove lower than the surface of dielectric layer; With described cover layer for mask, remove the 3rd metal level, the second metal level in the second groove in the first groove, above dielectric layer and above described cover layer; Remove described cover layer, then in described first groove, form first grid, in the second groove, form second grid.
Optionally, sputtering technology is adopted to form described layer of cover material.
Optionally, described sputtering technology adopts monocrystalline silicon as target, and oxygen is as reacting gas, and argon gas is sputter gas, and depositing temperature is 10 DEG C ~ 50 DEG C, and the flow velocity of oxygen is 1sccm ~ 2000sccm, and the flow velocity of argon gas is 1sccm ~ 2000sccm.
Optionally, physical gas-phase deposition, chemical vapor deposition method or atom layer deposition process is adopted to form described layer of cover material.
Optionally, atom layer deposition process or chemical vapor deposition method is adopted to form described gate dielectric material layer, the first metal layer, the second metal level and the 3rd metal level.
Optionally, the material of described the first metal layer is TiN.
Optionally, the material of described second metal level is TaN.
Optionally, the material of described 3rd metal level is TiN.
Optionally, the material of described second metal level is not identical with the material of the first metal layer.
Optionally, the material of described 3rd metal level is identical with the material of the first metal layer.
Optionally, described layer of cover material also covers the 3rd layer on surface of metal on described dielectric layer.
Optionally, the material of described layer of cover material is SiO
2, SiN, SiON or SiCN.
Optionally, the material of described mask layer is the anti-emissive material of photoresist or bottom.
Optionally, the distance of described tectal surface distance semiconductor substrate surface is 1/2 ~ 3/4 of the second depth of groove.
Optionally, wet-etching technology described 3rd metal level of etching and the second metal level is adopted.
Optionally, the etching solution etching described 3rd metal level employing is NH
4oH, H
2o
2with H
2the mixed solution of O.
Optionally, the etching solution etching described second metal level employing is HCl, H
2o
2with H
2the mixed solution of O
Optionally, described first grid and second grid are single-layer metal structure or multiple layer metal stacked structure.
Optionally, the first grid of described multiple layer metal stacked structure and second grid comprise respectively: TiAl layer, be positioned at the TiN layer on described TiAl layer surface and be positioned at Al layer or the W layer on described TiN layer surface.
Optionally, the material of described gate dielectric material layer is HfO
2, HfSiO, HfSiON, HfTaO, HfZrO, Al
2o
3or ZrO
2in one or more.
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention, form gate dielectric material layer, the first metal layer, the second metal level and the 3rd metal level successively in first groove and the second groove of described semiconductor substrate surface after, in described first groove and the second groove, form layer of cover material, then remove the layer of cover material in described NMOS area.Material due to described layer of cover material is insulating dielectric materials, easy removal, can not stay residual in described first groove, thus can avoid, in the 3rd metal level in follow-up removal first groove and the process of the second metal level, owing to covering the barrier effect of the residue of defective material layer, completely described 3rd metal level and the second metal level can not be got rid of, thus cause the work function of the nmos pass transistor formed undesirable.
Further, the method forming described layer of cover material can be sputtering technology.Because the integrated level of existing integrated circuit is higher, the grid size of CMOS transistor is also more and more less.So the size of described first groove and the second groove is also less, and depth-to-width ratio is larger.Technical scheme of the present invention, form gate dielectric layer, the first metal layer, the second metal level and the 3rd metal level in described first groove and the second groove after, the bulk be not filled in described first groove and the second groove declines further, depth-to-width ratio improves further, and the difficulty of filling layer of cover material in described second groove and the second groove is larger.Sputtering technology has higher directivity and the filling capacity of high-aspect-ratio; technical scheme of the present invention adopts sputtering technology can form the layer of cover material of better quality in described first groove and the second groove; and then improve the tectal quality of the layer of cover material formation in subsequent etching second groove, thus improve the protective effect of described cover layer for each material layer in the second groove.
Accompanying drawing explanation
Fig. 1 to Figure 10 is the structural representation of the forming process of the CMOS transistor of embodiments of the invention.
Embodiment
As described in the background art, the performance of the CMOS transistor of prior art formation needs further to be improved.
Prior art is in the process forming nmos pass transistor and PMOS transistor, form identical work-function layer in NMOS area and PMOS area simultaneously, then after PMOS area forms mask layer, remove the PMOS work-function layer in NMOS area, thus make the CMOS transistor of follow-up formation and PMOS transistor have different work functions.The material of described mask layer is the organic material such as photoresist layer or bottom anti-reflective material, although can improve mask layer for the formation of the filling effect in the groove of grid, described organic material easily stays residual in removal process.Prior art forms mask layer usually on NMOS and PMOS area simultaneously, remove the mask layer in NMOS area again, in removal process, easy bottom portion of groove on an nmos area leaves the residue of mask layer, thus cause the follow-up PMOS work-function layer can not removed completely in NMOS area, and cause the work function of the nmos pass transistor formed inaccurate, and affect the performance of CMOS transistor.
Further, follow-up removal mask layer, then formed in the process of grid, described mask layer has residual, also can affect the quality of the grid of formation, and the interface quality between grid and work-function layer, affects the performance of CMOS transistor.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Please refer to Fig. 1, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 comprises NMOS area and PMOS area, described NMOS area is also formed with the first pseudo-grid structure 201, PMOS area is formed with the second pseudo-grid structure 202, described Semiconductor substrate 100 surface has dielectric layer 300, and the surface of described dielectric layer 300 flushes with the surface of the first pseudo-grid structure 201 and the second pseudo-grid structure 202.
The material of described Semiconductor substrate 100 comprises the semi-conducting materials such as silicon, germanium, SiGe, GaAs, can be body material also can be that composite construction is as silicon-on-insulator.Those skilled in the art can select the type of described Semiconductor substrate 100 according to the semiconductor device that Semiconductor substrate 100 is formed, therefore the type of described Semiconductor substrate should not limit the scope of the invention.
Described Semiconductor substrate 100 comprises: NMOS area and PMOS area, described NMOS area is used for forming nmos pass transistor within it, described PMOS area is used for forming PMOS transistor within it, and described nmos pass transistor and PMOS transistor also can be able to be fin formula field effect transistor (Fin FET) for planar MOS transistors.
Between described NMOS area and PMOS area, also there is isolation structure 101, in the present embodiment, described isolation structure 101 is fleet plough groove isolation structure (STI), and to isolate the active region in described Semiconductor substrate 100, the material of described fleet plough groove isolation structure is silica.
Described PMOS area and NMOS area surface have the first pseudo-grid structure 201 and the second pseudo-grid structure 202 respectively, the Semiconductor substrate 100 being positioned at described first pseudo-grid structure 201 and the second pseudo-grid structure 202 both sides has source region and drain region (not shown), Semiconductor substrate 100 surface also has dielectric layer 300, and the surface of described dielectric layer 300 flushes with the surface of described first pseudo-grid structure 201 and the second pseudo-grid structure 202.Isolated by isolation structure 101 between described NMOS area and PMOS area.
In the present embodiment, described first pseudo-grid structure 201 and the second pseudo-grid structure 202 comprise the pseudo-gate dielectric layer being positioned at Semiconductor substrate 100 surface and the pseudo-grid of the polysilicon being positioned at described pseudo-gate dielectric layer surface.
In other embodiments of the invention, described first pseudo-grid structure 201 and the second pseudo-grid structure 202 only can comprise the pseudo-grid of polysilicon.
In other embodiments of the invention, the sidewall surfaces of described first pseudo-grid structure 201 and the second pseudo-grid structure 202 is also formed with side wall.
Please refer to Fig. 2, remove described first pseudo-grid structure 201(and please refer to Fig. 1) and the second pseudo-grid structure 202(please refer to Fig. 1), form the first groove 301 and the second groove 302.
After removing described first pseudo-grid structure 201 and the second pseudo-grid structure 202, expose the part surface of Semiconductor substrate 100, square one-tenth first groove 301 on an nmos area, above PMOS area, form the second groove 302, the method removing described first pseudo-grid structure 201 and the second pseudo-grid structure 202 is wet-etching technology.
Follow-uply in described first groove 301 and the second groove 302, form first grid and second grid respectively.
Please refer to Fig. 3, form gate dielectric material layer 400 in the inner wall surface of described first groove 301 and the second groove 302 and dielectric layer 300 surface, be positioned at the first metal layer 401 on gate dielectric material layer surface, be positioned at second metal level 402 on the first metal layer surface, be positioned at the 3rd metal level 403 on described second metal level 402 surface.
The material of described gate dielectric material layer 400 is high K dielectric material, comprising: HfO
2, HfSiO, HfSiON, HfTaO, HfZrO, Al
2o
3, ZrO
2in one or more, the technique forming described gate dielectric material layer 400 is atom layer deposition process or chemical vapor deposition method.In the present embodiment, the method forming described gate dielectric material layer 400 is atom layer deposition process, adopts atom layer deposition process, can improve the quality of gate dielectric material layer 400, more easily controls the thickness of the gate dielectric material layer 400 formed.
The formation method of described the first metal layer 401 can be chemical vapor deposition method or atom layer deposition process.In the present embodiment, the material of described the first metal layer 401 is TiN, adopts atom layer deposition process to form described the first metal layer 401.Concrete, the reaction temperature that described atom layer deposition process adopts is 200 DEG C ~ 400 DEG C, adopts reacting gas to comprise: containing first precursor gas of Ti, and described the first precursor gas containing Ti comprises Ti [N (C
2h
5cH
3)]
4, Ti [N (CH
3)
2]
4or Ti [N (C
2h
5)
2]
4in one or more; Second precursor gas, described second precursor gas comprises NH
3, CO or H
2one or more in O.
Described the first metal layer 401 can prevent the metal in the metal level of follow-up formation to be diffused in gate dielectric material layer 400 and dielectric layer 300, to cause being short-circuited between interconnection layer and between device, defect in gate dielectric material layer 400 is avoided to increase, the performance of the CMOS transistor that impact is formed.
The formation method of described second metal level 402 can be chemical vapor deposition method or atom layer deposition process.The material of described second metal level can be not identical with the material of the first metal layer.In the present embodiment, the material of described second metal level is TaN, adopts atom layer deposition process to form described second metal level 402 better to control the thickness of the second metal level 402, improves the quality of described second metal level 402.Concrete, the reaction temperature that described atom layer deposition process adopts is 200 DEG C ~ 400 DEG C, adopts reacting gas to comprise: containing first precursor gas of Ta, and described the first precursor gas containing Ta comprises Ta [N (C
2h
5cH
3)]
4, Ta [N (CH
3)
2]
4or Ta [N (C
2h
5)
2]
4in one or more; Second precursor gas, described second precursor gas comprises NH
3, CO or H
2one or more in O.
Described second metal level 402, as the etching barrier layer on the first metal layer 401 surface, protects described the first metal layer 401 in subsequent technique.Further, described second metal level 402 can also as work-function layer, for adjusting the work function of nmos pass transistor and PMOS transistor.
The formation method of described 3rd metal level 403 can be chemical vapor deposition method or atom layer deposition process.In the present embodiment, the material of described 3rd metal level 403 is TiN, atom layer deposition process can be adopted to form described 3rd metal level 403 better to control the thickness of the 3rd metal level 403, improve the quality of described 3rd metal level 403, the formation method of the first metal layer 401 can be adopted, form described 3rd metal level 403, therefore not to repeat here.
Described 3rd metal level 403 is as the work-function layer of PMOS transistor, and follow-up needs removes the 3rd metal level 403 in NMOS area, to meet the requirement of nmos pass transistor to gate work-function.
Please refer to Fig. 4, described Semiconductor substrate 100 formed and fills described first groove 301(and please refer to Fig. 3) and the layer of cover material 500 of the second groove (please refer to Fig. 3), the material of described layer of cover material 500 is insulating dielectric materials.
Concrete, the material of described layer of cover material 500 can be SiO
2, the insulating dielectric materials such as SiN, SiON or SiCN, described insulating dielectric materials is easily removed by etching technics, and does not have residual.Chemical vapour deposition (CVD), physical gas-phase deposition or atom layer deposition process can be adopted to form described layer of cover material 500.
In the present embodiment, the material of described layer of cover material 500 is SiO
2, and adopt sputtering technology to form described layer of cover material 500.Concrete, described sputtering adopts monocrystalline silicon as target, and oxygen is as reacting gas, and argon gas is sputter gas, and depositing temperature is 10 DEG C ~ 50 DEG C, and the flow velocity of oxygen is 1sccm ~ 2000sccm, and the flow velocity of argon gas is 1sccm ~ 2000sccm.
Because the integrated level of existing integrated circuit is higher, the grid size of described CMOS transistor is also more and more less.So described first groove 301(please refer to Fig. 2) and the second groove 302(please refer to Fig. 2) size also less, depth-to-width ratio is larger.In the present embodiment, form gate dielectric layer 400, the first metal layer 401, second metal level 402 and the 3rd metal level 403 in described first groove 301 and the second groove 302 after, the bulk be not filled in described first groove 301 and the second groove 302 declines further, depth-to-width ratio improves further, and the difficulty of filling described second groove 301 and the second groove 302 is larger.In the present embodiment, adopt sputtering technology can form the layer of cover material 500 of better quality in described first groove 301 and the second groove 302.
Described sputtering technology has higher directivity, and the bottom that be not filled part of described layer of cover material 500 in the first groove 301 and the second groove 302 starts upwards to grow gradually, and can not directly form described layer of cover material in sidewall surfaces.Simultaneously, the 3rd metal level 403 surface on described dielectric layer 300 also can form described layer of cover material 500, thickness along with described layer of cover material 500 becomes large, the layer of cover material being positioned at the 3rd metal level 403 surface above described dielectric layer 300 closes respectively at the top of the first groove 301 and the second groove 302, forms the layer of cover material 500 that surface is comparatively smooth.
In the present embodiment, the surface of the layer of cover material 500 in described first groove 302 and the second groove 302 lower than the surface of the 3rd metal level 403 above described dielectric layer 300, thus can form a cavity between layer of cover material 500 in described first groove 301 and the second groove 302 and the layer of cover material 500 on dielectric layer 300.In other embodiments of the invention, the surface of the layer of cover material 500 in described first groove 301 and the second groove 302 also higher than described 3rd metal level 403 surface, can make to there is not cavity between the layer of cover material on the 3rd metal level 403 surface.
Sputtering technology is adopted to form described layer of cover material 500; the filling quality of described layer of cover material 500 in described first groove 301 and the second groove 302 can be improved; thus improve layer of cover material 500 in subsequent technique, to the protective effect of the 3rd metal level 403, second metal level 402 covered by described layer of cover material 500 in the second groove 302.
Please refer to Fig. 5, described PMOS area is formed mask layer 600, with described mask layer 600 for mask, remove the layer of cover material 500 in NMOS area.
The material of described mask layer 600 is photoresist layer, and described mask layer 600 is positioned in PMOS area, for the protection of the layer of cover material 500 in PMOS area.The formation method of described mask layer 600 can be, after described layer of cover material 500 surface forms the photoresist layer covering described PMOS and NMOS area surface, to described photoresist layer exposure imaging, forms the mask layer 600 covering described PMOS area.
After forming described mask layer 600, with described mask layer 600 for mask, remove the layer of cover material 500 in NMOS area.Employing isotropic etching technique removes the layer of cover material 500 in described NMOS area, and in the present embodiment, employing wet-etching technology removes the layer of cover material 500 in described NMOS area, and the etching solution that described wet-etching technology adopts is HF solution.
Material due to described layer of cover material 500 is insulating dielectric materials, employing wet-etching technology can remove the layer of cover material 500 in described NMOS area more thoroughly, avoid in described first groove 301, there be the residual of layer of cover material 500, and affect the follow-up removal to the 3rd metal level in the first groove 301, the second metal level, and affect the quality of the follow-up first grid formed in the first groove 301.
Please refer to Fig. 6, remove described mask layer 600(and please refer to Fig. 5) after, etch the layer of cover material 500 in described PMOS area, remove the layer of cover material 500 of the segment thickness of layer of cover material 500 and described second groove 302 be positioned at above dielectric layer 300, in described second groove, form cover layer 501, and the surface of described cover layer 501 is lower than the surface of dielectric layer 300.
In an embodiment of the present invention, the distance on surface distance Semiconductor substrate 100 surface of described cover layer 501 can be 1/2 ~ 3/4 of second groove 302 degree of depth.The area of follow-up remaining 3rd metal level 403 and the second metal level 402 in described second groove 302 can be adjusted by the thickness adjusting described cover layer 501, thus the work function of the final PMOS transistor formed of adjustment.In the present embodiment, the degree of depth of described second groove 302 is 100nm, and described in described cover layer 501 surface distance, the distance on Semiconductor substrate 100 surface is 60nm.
Described cover layer 501 for as mask, protects the metal level on the bottom of the second groove 302 lower part and sidewall.
Please refer to Fig. 7, with described cover layer 501 for mask, remove the 3rd metal level 403 in the second groove 302 in the first groove 301, above dielectric layer 300 and above described cover layer 501.
Concrete, the method removing described part the 3rd metal level 403 is isotropic etching technique.In the present embodiment, adopt the 3rd metal level 403 in the second groove 302 in described first groove 301 of wet-etching technology removal, above dielectric layer 300 and above described cover layer 501.Concrete, the etching solution that described wet-etching technology adopts is NH
4oH, H
2o
2with H
2the mixed solution of O, concrete, described NH
4oH, H
2o
2with H
2the concentration ratio of O is 1:1:5 ~ 1:2:7.
Described second metal level 402 is different with the etch rate of the 3rd metal level 403, so described wet-etching technology is using described second metal level 402 as etching stop layer.Described second metal level 402 protects the first metal layer 401 injury-free in etching process.
In other embodiments of the invention, chemical gaseous phase etching technics also can be adopted to etch described 3rd metal level 403.
Please refer to Fig. 8, with described cover layer 501 for mask, remove the second metal level 402 in the second groove 302 in the first groove 301, above dielectric layer 300 and above described cover layer 501.
Still adopt described second metal level 402 of wet-etching technology etching, described etching solution can be HCl, H
2o
2with H
2the mixed solution of O.
In other embodiments of the invention, other etching solutions can also be adopted to etch described second metal level 402, chemical gaseous phase etching technics also can be adopted to etch described second metal level 402.Described
Due to the protective effect of described covering 501; make after above-mentioned processing step; the bottom of described second groove 302 lower part and sidewall also retains part the 3rd metal level 403 and part second metal level 402; described part the 3rd metal level 403 and part second metal level 402 for regulating the work function of PMOS transistor, thus meet nmos pass transistor and PMOS transistor to the different requirements of work function.
Please refer to Fig. 9, remove described cover layer 501(as shown in Figure 8).
Wet-etching technology is adopted to remove described cover layer.In the present embodiment, the material of described cover layer 501 is silica, and the solution of described wet-etching technology is HF solution.
Cover layer 501(can be please refer to Fig. 8 by described wet-etching technology) remove completely, do not have residual in described second groove, thus compared with prior art, the quality of the grid of follow-up formation can be improved, thus improve the performance of CMOS transistor.
Please refer to Fig. 9, please refer to Fig. 8 at described first groove 301 and the second groove 302() in form first grid 601 and second grid 602 respectively.
The method forming described first grid 601 and second grid 602 comprises: formed and fill full described first groove 301, second groove 302 and the gate material layers covering the first metal layer 301 surface on described dielectric layer 300; With described dielectric layer 300 for stop-layer, planarization is carried out to the gate dielectric material layer 400 on described dielectric layer 300 surface, the first metal layer 401 and gate material layers, remove the gate dielectric material layer 400, the first metal layer 401 and the gate material layers that are positioned at above described dielectric layer 300, form the first grid 601 be positioned in NMOS area, be positioned at the second grid 602 in PMOS area.
Described first grid 601 and second grid 602 can be single-layer metal structures, also can be multiple layer metal stacked structures.In the present embodiment, described first grid 601 and second grid 602 all comprise respectively: the 4th metal level, be positioned at the 5th metal level of the 4th layer on surface of metal and be positioned at the 6th metal level (not shown) of the 5th layer on surface of metal.
Concrete, in the present embodiment, described 4th metal level is TiAl layer, and described 4th metal level can regulate the work function of nmos pass transistor and PMOS transistor; Described 5th metal level is TiN layer, and described 5th metal level, as barrier layer, can stop that metallic atom in the 6th metal level is to outdiffusion, affects the work function of transistor; The material of described 6th metal level is W or Al.
In sum, in embodiments of the invention, form gate dielectric material layer, the first metal layer, the second metal level and the 3rd metal level successively in first groove and the second groove of described semiconductor substrate surface after, layer of cover material is formed in described first groove and the second groove, then remove the layer of cover material in described NMOS area, form the cover layer being positioned at the second groove.The material of the layer of cover material that embodiments of the invention adopt is insulating dielectric materials, easy removal, can not stay residual in removal process in described first groove, thus can avoid in the process of the 3rd metal level in removal first groove and the second metal level, owing to covering the barrier effect of the residue of defective material layer, completely described 3rd metal level and the second metal level can not be got rid of, thus cause the work function of the nmos pass transistor formed undesirable.
Further, sputtering technology can also be adopted in embodiments of the invention to form described layer of cover material.Form gate dielectric layer, the first metal layer, the second metal level and the 3rd metal level in described first groove and the second groove after, the bulk be not filled in described first groove and the second groove declines further, depth-to-width ratio improves further, and the difficulty of filling layer of cover material in described second groove and the second groove is larger.Sputtering technology has higher directivity and the filling capacity of high-aspect-ratio, forms the cover layer that deposition quality is higher in the second groove, thus improves the protective effect for each material layer in the second groove in etching process of described cover layer.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for CMOS transistor, is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate comprises NMOS area and PMOS area, described semiconductor substrate surface has dielectric layer, has the first groove in the dielectric layer on described NMOS area surface, has the second groove in the dielectric layer on described PMOS area surface;
At the 3rd metal level that inner wall surface and the dielectric layer surface of described first groove and the second groove form gate dielectric material layer successively, are positioned at the first metal layer on gate dielectric material layer surface, are positioned at second metal level on described the first metal layer surface, are positioned at described second layer on surface of metal;
Form the layer of cover material of filling described first groove and the second groove, the material of described layer of cover material is insulating dielectric materials;
Remove the layer of cover material in NMOS area;
Remove the layer of cover material that the second inside grooves divides thickness, form cover layer, make the tectal surface in described second groove lower than the surface of dielectric layer;
With described cover layer for mask, remove the 3rd metal level, the second metal level in the second groove in the first groove, above dielectric layer and above described cover layer;
Remove described cover layer, then in described first groove, form first grid, in the second groove, form second grid.
2. the formation method of CMOS transistor according to claim 1, is characterized in that, adopts sputtering technology to form described layer of cover material.
3. the formation method of CMOS transistor according to claim 2, it is characterized in that, described sputtering technology adopts monocrystalline silicon as target, oxygen is as reacting gas, argon gas is sputter gas, depositing temperature is 10 DEG C ~ 50 DEG C, and the flow velocity of oxygen is 1sccm ~ 2000sccm, and the flow velocity of argon gas is 1sccm ~ 2000sccm.
4. the formation method of CMOS transistor according to claim 1, is characterized in that, adopts physical gas-phase deposition, chemical vapor deposition method or atom layer deposition process to form described layer of cover material.
5. the formation method of CMOS transistor according to claim 1, is characterized in that, adopts atom layer deposition process or chemical vapor deposition method to form described gate dielectric material layer, the first metal layer, the second metal level and the 3rd metal level.
6. the formation method of CMOS transistor according to claim 1, is characterized in that, the material of described the first metal layer is TiN.
7. the formation method of CMOS transistor according to claim 6, is characterized in that, the material of described second metal level is TaN.
8. the formation method of CMOS transistor according to claim 7, is characterized in that, the material of described 3rd metal level is TiN.
9. the formation method of CMOS transistor according to claim 1, is characterized in that, the material of described second metal level is not identical with the material of the first metal layer.
10. the formation method of CMOS transistor according to claim 1, is characterized in that, the material of described 3rd metal level is identical with the material of the first metal layer.
The formation method of 11. CMOS transistor according to claim 1, is characterized in that, described layer of cover material also covers the 3rd layer on surface of metal on described dielectric layer.
The formation method of 12. CMOS transistor according to claim 1, is characterized in that, the material of described layer of cover material is SiO
2, SiN, SiON or SiCN.
The formation method of 13. CMOS transistor according to claim 1, is characterized in that, the material of described mask layer is the anti-emissive material of photoresist or bottom.
The formation method of 14. CMOS transistor according to claim 1, is characterized in that, the distance of described tectal surface distance semiconductor substrate surface is 1/2 ~ 3/4 of the second depth of groove.
The formation method of 15. CMOS transistor according to claim 1, is characterized in that, adopts wet-etching technology described 3rd metal level of etching and the second metal level.
The formation method of 16. CMOS transistor according to claim 8, is characterized in that, the etching solution etching described 3rd metal level employing is NH
4oH, H
2o
2with H
2the mixed solution of O.
The formation method of 17. CMOS transistor according to claim 8, is characterized in that, the etching solution etching described second metal level employing is HCl, H
2o
2with H
2the mixed solution of O.
The formation method of 18. CMOS transistor according to claim 7, is characterized in that, described first grid and second grid are single-layer metal structure or multiple layer metal stacked structure.
The formation method of 19. CMOS transistor according to claim 18, it is characterized in that, first grid and the second grid of described multiple layer metal stacked structure comprise respectively: TiAl layer, be positioned at the TiN layer on described TiAl layer surface and be positioned at Al layer or the W layer on described TiN layer surface.
The formation method of 20. CMOS transistor according to claim 1, is characterized in that, the material of described gate dielectric material layer is HfO
2, HfSiO, HfSiON, HfTaO, HfZrO, Al
2o
3or ZrO
2in one or more.
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