CN104679216A - Data routing device and control method thereof - Google Patents

Abstract

The invention discloses a data routing device and a control method thereof. The device comprises at least one replication logic and at least one signal generation module; the first input end of the signal generation module is connected with the output end of the replication logic, and while an original enable signal of a functional part is connected to the second input end of the signal generation module; the replication logic is used for calculating ODC (observability don't cares) value of an output signal of the functional part; if the ODC value is at the first level, the signal generating module generates a new enable signal of the functional part according to the ODC value and the original enable signal of the functional part; the new enable signal of the functional part is used for inhibiting the update of the output signal of the functional part. Compared with the traditional data routing structure, the data routing device has the advantages that the control of an input signal register is added, so that unnecessary inversion is reduced, and as a result, the power consumption can be reduced.

Description

A kind of data path means and control method thereof

Technical field

The present invention relates to integrated circuit (IC) design field, particularly a kind of data path means and control method thereof.

Background technology

Along with improving constantly of integrated circuit (IC) design complicacy, whole system can realize on one chip, but the raising of this performance sharply increases to cost with power consumption, particularly for the handheld device of widespread use.Because being significantly lifted at of battery capacity not easily realizes in a short time, this just requires not only will consider performance in integrated circuit design process, and will consider power consumption.

Data routing (Data Path) is the key components of processor cores transmission of signal, and in program operation process, signal upset is very frequent, and this makes one of data routing main source becoming power consumption of processing unit.

Fig. 1 is the general structure of data routing.As shown in Figure 1, data routing is primarily of circuit compositions such as register (Register), MUX (Multiplexer), totalizers (Adder).Input signal (as Bus_A and Bus_B) participates in the calculating of calculating unit (as ADDER) by MUX (as MUX1 and MUX2), and result of calculation is assigned to final output signal (as Bus_Out).

As can be seen from Figure 1, as enable signal (Sel2_En=1) of MUX (MUX2), MUX (MUX2) selecting paths 1, and the signal upset of signal (as Bus_A, Bus_B and Bus_C) and the result of calculation of functional part (as MUX1 and ADDER) can not pass to final output signal (as Bus_Out), this just causes a large amount of power consumption penalty.

Considerable independence (Observability Don ' t Care is called for short ODC) is analyzed the inconsiderable condition of the signal of data routing.As shown in Figure 2, its Boolean function expression formula is (z=x & y), symbol " & " presentation logic and computing for two input logics and door.When input variable y is low level, then no matter why input variable x is worth, and output variable z is low level, and namely input variable x is inconsiderable at output variable z place.On the other hand, when output variable z is not from considerable in final output signal place (as Primary Output), then input variable x is inconsiderable at final output signal place yet.

For two input logics and door, the ODC of input variable x calculates as shown in Equation 1:

$\mathrm{ODC}\left(x\right)=\stackrel{\‾}{y}+\mathrm{ODC}\left(z\right)---\left(1\right)$

Symbol "+" presentation logic or computing, symbol "-" presentation logic inverse.

For different functional parts, more generally ODC calculates as shown in Equation 2:

ODC(x)＝ODC _M(x)+ODC(z) (2)

The considerable independence ODC of functional part _mwhen () is for high level x, represent that input variable x is inconsiderable at the output variable place of functional part.The ODC of usual definition final output signal (as Primary Output) is low level, and namely final output signal is considerable all the time.

Propose in the people such as Yun-long Zhang delivers in periodical IEEE SOC Design Conference ISOCC2012 " Automatic Register Transfer Level CAD Tool Design for Advanced Clock Gating and Low Power Schemes " and use gated clock to reduce signal upset unnecessary in data routing.Its structure as shown in Figure 3, only have when clock (as clk) is for low level, activation function (as Fa and Fb) just can be delivered to the input end with door, when clock is from when low level becomes high level and activation function is high level, clock signal is enable, otherwise clock signal is forbidden.This method can reduce the unnecessary signal upset of a part, and then reduces power consumption.

Propose in " Low-power implementations of DSP through operand isolation and clock gating " article that the people such as Jun Chao delivers in periodical IEEE ASICON2007 and use operand isolation to reduce signal upset unnecessary in data routing.The principal feature of this structure is between input signal and calculating unit, insert isolation logic (blocking logic).Its principle of work is: if the operation result of calculating unit can be delivered to final output signal, then isolation logic is opened, otherwise isolation logic stops input signal to enter calculating unit.As shown in Figure 4, this method can reach the effect reducing power consumption preferably to its structure for specific data routing.

The above-mentioned power consumption in order to reduce data routing in processor, there is following shortcoming in the gated clock adopted and operand isolation method:

(1) gated clock effectively can not reduce unnecessary signal upset.As shown in Fig. 3 (a), output signal Bus_C selects Bus_A or Bus_B to export according to the value of gating signal Sel1_En.But owing to sharing a gated clock, therefore no matter select which signal to export, the clock signal of Parasites Fauna REG1 and REG2 all can not be forbidden, unnecessary signal upset cannot be reduced.

(2) different gated clocks is adopted to solve the problem, namely according to the value of gating signal Sel1_En, the clock signal of disable register group REG1 or REG2 respectively, as shown in Figure 3 (b).Even if but input signal Bus_A and Bus_B remains unchanged, due to the change of gating signal Sel1_En, the unnecessary upset of signal Bus_C cannot be reduced.Meanwhile, adopt different gated clocks that the time of clock signal clk arrival Parasites Fauna REG1 with REG2 may be made different, cause clock jitter (Clock Skew), increase the complexity of design.

(3) operand isolation needs to increase isolation logic, when the signal bit wide in data routing is larger (as Fig. 4, bit wide is 32 bits), needs to insert an isolation logic to each bit.Because isolation logic increases power consumption and area, make the power consumption of operand isolation and area cost very large.

Summary of the invention

The object of the invention is to, propose a kind of low power consumption data path structure, this structure adds the control to input signal register relative to traditional datapath architecture.When data routing works, adopt the unnecessary upset of ODC condition detection signal, forbid the enable signal of its input register.So just can reduce unnecessary signal upset, thus reduce power consumption.

For achieving the above object, on the one hand, the invention provides a kind of data path means, this device comprises: at least one replicated logic and at least one signal generation module, the first input end of described signal generation module is connected with the output terminal of described replicated logic, the former enable signal of its second input end access function parts; Described replicated logic calculates the considerable independence ODC value of described functional part output signal, when described ODC value is the first level, described signal generation module generates the new enable signal of described functional part according to the former enable signal of described ODC value and described functional part, and the new enable signal of described functional part is for forbidding the renewal that described functional part outputs signal.

On the other hand, the invention provides a kind of data routing control method, the method comprises: the considerable independence ODC value of computing function component output signals, when described ODC value is the first level, former enable signal according to described ODC value and described functional part generates the new enable signal of described functional part, and the new enable signal of described functional part is for forbidding the renewal that described functional part outputs signal.

The present invention adds the control to input signal register relative to traditional datapath architecture.When data routing works, adopt the unnecessary upset of considerable independence condition detection signal, forbid the enable signal of its input register, reduce unnecessary signal upset, thus reduce power consumption.

Accompanying drawing explanation

Fig. 1 is the datapath architecture schematic diagram of prior art;

Fig. 2 is the ODC computation structure schematic diagram of logical variable;

Fig. 3 is gated clock structural representation;

Fig. 4 is operand isolation structural representation;

A kind of data path means structural representation that Fig. 5 (a) provides for the embodiment of the present invention;

The another kind of data path means structural representation that Fig. 5 (b) provides for the embodiment of the present invention;

Fig. 6 is for driving base part structural representation;

Fig. 7 is ODC sample calculation figure;

Fig. 8 reduces the electrical block diagram that driver part outputs signal unnecessary upset.

Embodiment

Below by drawings and Examples, technical scheme of the present invention is described in further detail.

A kind of data path means structural representation that Fig. 5 (a) provides for the embodiment of the present invention.As shown in Fig. 5 (a), this device comprises replicated logic 10, replicated logic 20, replicated logic 30, signal generation module 60, signal generation module 61, signal generation module 70, signal generation module 80, first Parasites Fauna (REG1), the second Parasites Fauna (REG2), the 3rd register (REG3), the 4th register (REG4), the first MUX (MUX1), the second MUX (MUX2), totalizer (ADDER), steering logic 40 and steering logic 50.

The first input end of signal generation module 60 is connected with the output terminal of replicated logic 10, and the former enable signal MuxSell_Enb of its second input end access the 3rd register, its output terminal exports the new enable signal MuxSell_Enb_Gated of the 3rd register.The output terminal of the 3rd register is connected with an input end of steering logic 40.

The first input end of signal generation module 61 is connected with the output terminal of replicated logic 10, and the former enable signal MuxSell_Ena of its second input end access the 4th register, its output terminal exports the new enable signal MuxSell_Ena_Gated of the 4th register.The output terminal of the 4th register is connected with another input end of steering logic 40.

The first input end of signal generation module 70 is connected with the output terminal of replicated logic 20, and its second input end accesses the former enable signal Reg1_En of the first Parasites Fauna, and its output terminal exports the new enable signal Reg1_En_Gated of the first Parasites Fauna.The output terminal of the first Parasites Fauna is connected with an input end of the first MUX, and exports Bus_A signal to the first MUX.

The first input end of signal generation module 80 is connected with the output terminal of replicated logic 30, and its second input end accesses the former enable signal Reg2_En of the second Parasites Fauna, and its output terminal exports the new enable signal Reg2_En_Gated of the second Parasites Fauna.The output terminal of the second Parasites Fauna is connected with another input end of the first MUX, and exports Bus_B signal to the first MUX.

The first input end of the first MUX accesses the output signal Bus_A of the first Parasites Fauna, and its second input end accesses the output signal Bus_B of the second Parasites Fauna, and its output terminal is connected with an input end of totalizer, and exports Bus_C signal to totalizer.Another input end of totalizer access Bus_D signal, its output terminal is connected with an input end of the second MUX, and exports Bus_E signal to the second MUX.

Steering logic 40 according to the output signal of the output signal of the 3rd register and the 4th register to the first MUX output enable signal Sel1_En.Steering logic 50 according to the output signal of the output signal of the 5th register (not shown) and the 6th register (not shown) to the second MUX output enable signal Sel2_En.

One input end of the second MUX is connected with the output terminal of totalizer, its another input end access path 1 signal Bus_F, and its output terminal exports final output signal Bus_Out.

Replicated logic 10 is for calculating the ODC value (as ODC (Bus_C)@(T+1)) of the output signal Bus_C of the first MUX, when the ODC value of the output signal Bus_C of the first MUX is high level, then show that the output signal of the first MUX is inconsiderable at final output signal Bus_Out place, namely the renewal of the output signal of the first MUX is exactly unnecessary upset.Therefore, new enable signal MuxSel1_Enb_Gated and MuxSel1_Ena_Gated of input signal b and a of the first MUX enable signal Sel1_En that signal generation module 60 and signal generation module 61 generate, the renewal of the 3rd register and the 4th register output signal will be forbidden, the enable signal Sel1_En of the first MUX is made to keep original logical value by steering logic 40, to reduce the unnecessary upset of the first MUX output signal; When the ODC value of the output signal Bus_C of the first MUX is low level, show that its output signal is considerable at final output signal place, namely this signal can be delivered to final output signal.Therefore, the 3rd register is controlled by former enable signal MuxSel1_Enb, the 4th register is controlled by former enable signal MuxSel1_Ena, normally works.

Replicated logic 20 is for calculating the ODC value (as ODC (Bus_A)@(T+1)) of the output signal Bus_A of the first Parasites Fauna, when the ODC value of the output signal Bus_A of the first Parasites Fauna is high level, show that the output signal Bus_A of the first Parasites Fauna is inconsiderable at final output signal Bus_Out place, namely the first Parasites Fauna output signal can not be delivered to final signal, and so the renewal (as Bus_A becomes Bus_Ain) of the first Parasites Fauna output signal is exactly unnecessary upset.Therefore, the new enable signal Reg1_En_Gated of the first Parasites Fauna is generated by signal generation module 70, new enable signal Reg1_En_Gated will forbid the renewal of the first Parasites Fauna output signal, the output signal of the first Parasites Fauna is made to keep original logical value, reduce unnecessary upset, and then reduce power consumption; When the ODC value of the output signal Bus_A of the first Parasites Fauna is low level, show that its output signal is considerable at final output signal place, namely this signal can be delivered to final output signal.Therefore, the first Parasites Fauna is controlled by former enable signal Reg1_En, normally works.

Replicated logic 30 is for calculating the ODC value (as ODC (Bus_B)@(T+1)) of the output signal Bus_B of the second Parasites Fauna, when the ODC value of the output signal Bus_B of the second Parasites Fauna is high level, show that the output signal Bus_B of the second Parasites Fauna is inconsiderable at final output signal Bus_Out place, namely the second Parasites Fauna output signal can not be delivered to final signal, and so the renewal (as Bus_B becomes Bus_Bin) of the second Parasites Fauna output signal is exactly unnecessary upset.Therefore, the new enable signal Reg2_En_Gated of the second Parasites Fauna is generated by signal generation module 80, new enable signal Reg2_En_Gated, by forbidding the renewal of the second Parasites Fauna output signal, makes the output signal of the second Parasites Fauna keep original logical value, reduces unnecessary upset; When the ODC value of the output signal Bus_B of the second Parasites Fauna is low level, show that its output signal is considerable at final output signal place, namely this signal also can be delivered to final output signal.Therefore, the second Parasites Fauna is controlled by former enable signal Reg2_En, normally works.

In above-mentioned calculating data routing during the ODC value of signal, subscript@T is expressed as the variate-value of present clock period, the variate-value that@(T+1) is following clock cycle, the variate-value that@(T-1) is preceding clock cycle, the variate-value that the embodiment of the present invention represents without subscript, is all expressed as the variate-value of present clock period.In order to reduce the unnecessary upset of current period signal, needing to put forward the ODC value that the previous clock period calculates signal, therefore needing replicated logic.

The another kind of data path means structural representation that Fig. 5 (b) provides for the embodiment of the present invention.As shown in Fig. 5 (b), replicated logic 10-30 is made up of logical circuit usually, and the Parasites Fauna of input bus signal (as Bus_A) can share same replicated logic (as replicated logic 20), and therefore cost is very little.

In one embodiment, replicated logic 10 is formed by with door 11, accesses signal c@(T+1) and signal d@(T+1) respectively.Replicated logic 20 by with door 21 and with door 22, and or door 23 form, wherein, signal a@(T+1) and signal b@(T+1) is accessed respectively with door 21, access signal c@(T+1) and signal d@(T+1) respectively with door 22, with door 21 and with the output terminal of door 22 with or the input end of door 23 be connected.Replicated logic 30 by with door 31, with door 32, not gate 34 and or door 33 form, wherein, signal a@(T+1) and signal b@(T+1) is accessed respectively with door 31, signal c@(T+1) and signal d@(T+1) is accessed respectively with door 32, be connected with the input end of the output terminal Sheffer stroke gate 34 of door 31, the output terminal of not gate 34 and being connected respectively and with the input end of door 33 with the output terminal of door 32.

Steering logic 40 forms by with door 40, and access signal a and signal b respectively with the input end of door 40, its output terminal is connected with the first MUX, and to its output enable signal Sel1_En, (Sel1_En=a & b).

Steering logic 50 forms by with door 50, and access signal c and signal d respectively with the input end of door 50, its output terminal is connected with the second MUX, and to its output enable signal Sel2_En, (Sel2_En=c & d).

Signal generation module 60 forms by not gate 63 with door 60, its not gate 63 input end and being connected with the output terminal of door 11 in replicated logic 10, not gate 63 output terminal and being connected with door 60 1 input end, access the former enable signal MuxSel1_Enb of the 3rd register with another input end of door 60, its output terminal exports new enable signal MuxSe1_Enb_Gated to the 3rd register.

Signal generation module 61 forms by not gate 62 with door 61, its not gate 62 input end and being connected with the output terminal of door 11 in replicated logic 10, not gate 62 output terminal and being connected with door 61 1 input end; The former enable signal MuxSe1_Ena of the 4th register is accessed with another input end of door 61.Its output terminal exports new enable signal MuxSel1_Ena_Gated to the 4th register.

Signal generation module 70 forms by not gate 71 with door 70, wherein not gate 71 input end with in replicated logic 20 or the output terminal of door 23 be connected, not gate 71 output terminal and being connected with door 70 1 input end; Access the former enable signal Reg1_En of the first Parasites Fauna with another input end of door 70, its output terminal exports new enable signal Reg1_En_Gated to the first register.

Signal generation module 80 forms by not gate 81 with door 80, wherein not gate 81 input end with in replicated logic 30 or the output terminal of door 33 be connected, not gate 81 output terminal and being connected with door 80 1 input end; Access the former enable signal Reg2_En of the second Parasites Fauna with another input end of door 80, its output terminal exports new enable signal Reg2_En_Gated to the second register.

The embodiment of the present invention is according to ODC _mfunctional part is divided into two classes by the complexity calculated: compute classes parts and driving base part.Compute classes parts comprise: various with or, NOT logic door, the calculating unit such as totalizer and multiplier.The ODC of compute classes parts _mcomparatively complicated, and its computing method need to add a large amount of logic gate, and cost is increased.Therefore the ODC of embodiment of the present invention definition compute classes parts _mfor low level.Driving base part comprises: triple gate, the parts such as register and MUX.Drive base part structure as shown in Figure 6, its ODC _mcalculating as shown in Equation 3:

$\begin{array}{c}\mathrm{Tri}-\mathrm{state}:{\mathrm{ODC}}_M(\mathrm{Tri}\_\mathrm{In})=\stackrel{\‾}{\mathrm{Tri}\_\mathrm{En}}\\ \mathrm{Register}:{\mathrm{ODC}}_M(\mathrm{Reg}\_\mathrm{In})=\stackrel{\‾}{\mathrm{Reg}\_E{n}_{@(T-1)}}\\ \mathrm{Multiplexer}:{\mathrm{ODC}}_M(\mathrm{Mux}\_\mathrm{In}0)=\stackrel{\‾}{\mathrm{Sel}\_\mathrm{En}0}...\\ {\mathrm{ODC}}_M(\mathrm{Mux}\_\mathrm{InN})=\stackrel{\‾}{\mathrm{Sel}\_\mathrm{EnN}}\end{array}---\left(3\right)$

From formula 3, drive the ODC of base part _monly do logic NOT operation to its enable signal, calculate comparatively simple, therefore cost is very little.

The calculating of signal ODC can in two kinds of situation: input signal non-linkage function parts but have multiple fan-out signal and input signal linkage function parts and have multiple output signal.

Input signal non-linkage function parts but have multiple fan-out signal, its ODC calculates as shown in Equation 4:

$\mathrm{ODC}\left(\mathrm{bus}\right)=\underset{i=1}{\overset{N}{\mathrm{\Π}}}\mathrm{ODC}\left({\mathrm{fanout}}_i\right)---\left(4\right)$

Input signal linkage function parts and have multiple output signal, its ODC calculates as shown in Equation 5:

$\mathrm{ODC}\left(\mathrm{bus}\right)={\mathrm{ODC}}_M\left(\mathrm{bus}\right)+\underset{i=1}{\overset{M}{\mathrm{\Π}}}\mathrm{ODC}\left({\mathrm{out}}_i\right)---\left(5\right)$

In formula, bus represents input signal, and fanout represents fan-out signal, and N represents the number of fan-out signal, and symbol " ∏ " represents multiple signal and does logic and operation, and out represents output signal, the number of M representative output signal.

Below by the computing method (shown in figure 7) of clear signal ODC a simple example.

$\begin{array}{c}\mathrm{ODC}\left({\mathrm{Fanout}}_1\right)={\mathrm{ODC}}_M\left({\mathrm{Fanout}}_1\right)+\underset{i=1}{\overset{1}{\mathrm{\Π}}}\mathrm{ODC}(\mathrm{Mux}\_\mathrm{Out})\\ =\stackrel{\‾}{\mathrm{Sel}1\_\mathrm{En}}+\mathrm{ODC}(\mathrm{Mux}\_\mathrm{Out})\\ \mathrm{ODC}\left({\mathrm{Fanout}}_2\right)={\mathrm{ODC}}_M\left({\mathrm{Fanout}}_2\right)+\underset{i=1}{\overset{2}{\mathrm{\Π}}}\mathrm{ODC}\left({\mathrm{out}}_i\right)\\ =0+\mathrm{ODC}\left(\mathrm{Sum}\right)\&\mathrm{ODC}\left(\mathrm{Carry}\right)\\ =\mathrm{ODC}\left(\mathrm{Sum}\right)\&\mathrm{ODC}\left(\mathrm{Carry}\right)\\ \mathrm{ODC}(\mathrm{Bus}\_E)=\underset{i=1}{\overset{2}{\mathrm{\Π}}}\mathrm{ODC}\left({\mathrm{Fanout}}_i\right)\\ =\mathrm{ODC}\left({\mathrm{Fanout}}_1\right)\&\mathrm{ODC}\left({\mathrm{Fanout}}_2\right)\end{array}---\left(5\right)$

The wherein ODC of Fanout2 _mfor low level is because totalizer (ADDER) is compute classes parts.

Reduce driver part and output signal the circuit structure of unnecessary upset as shown in Figure 8.

For triple gate, the ODC condition of output signal can be utilized for reducing unnecessary signal upset.For register and MUX, can utilize the ODC condition of output signal for reducing the upset of unnecessary signal, need to carry the previous clock period calculates its ODC result simultaneously, therefore needs to add replicated logic.

The embodiment of the present invention adds the control to input signal register relative to traditional datapath architecture.When data routing works, adopt the unnecessary upset of considerable independence condition detection signal, forbid the enable signal of its input register.So just can reduce unnecessary signal upset, thus reduce power consumption.In addition, the embodiment of the present invention does not need to increase a large amount of isolation logic, and can not cause clock jitter.

Obviously, under the prerequisite not departing from true spirit of the present invention and scope, the present invention described here can have many changes.Therefore, all changes that it will be apparent to those skilled in the art that, all should be included within scope that these claims contain.The present invention's scope required for protection is only limited by described claims.

Claims (10)

1. a data path means, it is characterized in that, comprise: at least one replicated logic and at least one signal generation module, the first input end of described signal generation module is connected with the output terminal of described replicated logic, the former enable signal of its second input end access function parts;

Described replicated logic calculates the considerable independence ODC value of described functional part output signal, when described ODC value is the first level, described signal generation module generates the new enable signal of described functional part according to the former enable signal of described ODC value and described functional part, and the new enable signal of described functional part is for forbidding the renewal that described functional part outputs signal.

2. device according to claim 1, is characterized in that, when described ODC value is second electrical level, described signal generation module exports the former enable signal of described functional part, and described functional part is controlled by its former enable signal.

3. device according to claim 2, is characterized in that, described first level is high level, and described second electrical level is low level.

4. device according to claim 1, is characterized in that, described replicated logic is mainly used in:

Put forward the ODC value of the functional part output signal described in the calculating of previous clock period.

5. device according to claim 1, is characterized in that, described replicated logic forms primarily of with one or more in door or door and not gate.

6. device according to claim 1, is characterized in that, described signal generation module forms primarily of not gate and/or with door.

7. device according to claim 1, it is characterized in that, described functional part comprises compute classes parts and drives base part, described compute classes parts mainly comprise and one or more in door or door, not gate, totalizer and multiplier, described driving base part mainly comprise in triple gate, register and MUX one or more.

8. a data routing control method, is characterized in that, the method comprises:

The considerable independence ODC value of computing function component output signals, when described ODC value is the first level, former enable signal according to described ODC value and described functional part generates the new enable signal of described functional part, and the new enable signal of described functional part is for forbidding the renewal that described functional part outputs signal.

9. method according to claim 8, is characterized in that, when described ODC value is second electrical level, export the former enable signal of described functional part, described functional part is controlled by its former enable signal.

10. method according to claim 9, is characterized in that, described first level is high level, and described second electrical level is low level.