CN104671187B - A kind of semiconductor device and forming method thereof - Google Patents
A kind of semiconductor device and forming method thereof Download PDFInfo
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- CN104671187B CN104671187B CN201310617894.4A CN201310617894A CN104671187B CN 104671187 B CN104671187 B CN 104671187B CN 201310617894 A CN201310617894 A CN 201310617894A CN 104671187 B CN104671187 B CN 104671187B
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Abstract
A kind of semiconductor device and forming method thereof.Wherein, in method for forming semiconductor devices, the second surface of etching covering substrate, form the cavity for accommodating the components and parts being raised in Semiconductor substrate first surface, and for forming the opening of metal plug, sheetmetal material is filled afterwards in described opening, after forming metal plug, described covering substrate is covered at Semiconductor substrate first surface, make the components and parts in Semiconductor substrate be positioned at described cavity, and the metal plug in described covering substrate is fixed with the testing cushion in Semiconductor substrate and is connected.The first surface grinding covering substrate afterwards exposes described metal plug.In the electric performance test operation of the semiconductor device formed, directly connect components and parts and the test instrunment of outside by described metal plug, complete the electric performance test operation to components and parts, thus simplify the electric performance test operation of semiconductor device, and the success rate that the electric performance test operation improving semiconductor device is carried out.
Description
Technical field
The present invention relates to quasiconductor preparation field, especially relate to a kind of semiconductor device and forming method thereof.
Background technology
Along with the continuous progress of semiconductor integrated circuit manufacturing technology, the integrated level of integrated circuit constantly promotes,
The size of device the most constantly reduces.Now at a ULSI (Ultra Large-Scale
Integration；It is called for short, ULSI) in, components and parts up to a million can be comprised.
In the most large-scale ic manufacturing process, in integrated circuit preparation process, specifically
Time period, the testing electrical property that the various test structures being required on silicon chip are carried out, such as WAT(wafer
Receive test, Wafer Acceptance Test).Analyzed by WAT data, can find in time partly to lead
Problem in body making technology, helps making technology to be adjusted.
With reference to shown in Fig. 1～Fig. 3, for MEMS(Micro-Electronic&Mechanical System,
MEMS) encapsulate and WAT test technology.Specific embodiment includes:
With reference to shown in Fig. 1, first it is used for encapsulating equipped with being formed in the substrate 10 of MEMS chip 13 at one
Junction point (bonding pad) 11 and for WAT test test point (testing pad) 12, its
Middle test point 12 and MEMS chip electrical connection；Surface is provided to offer the covering substrate (Cap of cavity 23
Wafer) 20, described cavity 23 is corresponding with MEMS chip 13 position；With reference to shown in Fig. 2, will cover
Substrate 20 covers in described substrate 10, and MEMS chip 13 is positioned at described cavity 23, junction point
11 fix (bonding step) with described covering substrate 20；Remove part described covering substrate 20(dicing
Step) expose test point 12, prepare for follow-up WAT test, and deposition electricity in described substrate 10
Sealing coat (not shown), so far completes MEMS chip 13 and installs.
With continued reference to shown in Fig. 3, afterwards, carry out MEMS chip test, open and be positioned at described test point
Electricity isolated layer above in the of 12, exposes test point 12, and is inserted into testing needle card (probe to electricity isolated layer
Finger) 30, thus carry out the testing electrical property of MEMS chip.
Additionally, in actual WAT test process, for the ease of the removal of covering substrate 20 afterwards,
To expose test point 12, on covering substrate 20 surface, also need to offer groove with test point 12 correspondence position
24.As it has been described above, the WAT test process of existing MEMS is loaded down with trivial details.And, at testing needle card 30
When inserting the opening being positioned at the electricity isolated layer above test point, if misoperation, described testing needle card 30
Deviation can occur；If it is improper to be positioned at the through hole that the electricity isolated layer above test point 12 offers, or remove
Part covering substrate 20 position occur deviation time, testing needle card 30 also can occur with covering substrate 20
Touching, above-mentioned situation all can cause testing needle card 30 to damage, and causes WAT test crash.
To this end, how to improve in integrated circuit fabrication process, test technology success rate and testing efficiency are these
The problem that skilled person needs solution badly.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor device and forming method thereof, thus improves and partly lead
Efficiency during body device detection and the success rate of test step.
The forming method of a kind of semiconductor device provided by the present invention, including:
Thering is provided Semiconductor substrate, the first surface of described Semiconductor substrate has components and parts, described quasiconductor
There is in substrate surface and be exposed to the testing cushion of Semiconductor substrate first surface, described components and parts and testing cushion
Between noncontact, and by the interconnection line in described Semiconductor substrate, described components and parts and testing cushion are electrically connected
Connect；
Covering substrate is provided, etches the second surface of described covering substrate, formed in described covering substrate
Opening；
In described opening, fill full metal material, form metal plug；
Etch the second surface of described covering substrate, in described covering substrate, form cavity,；
By the second surface laminating of the first surface of described Semiconductor substrate with described covering substrate, make described
Components and parts in Semiconductor substrate are positioned at described cavity, and make testing cushion in described Semiconductor substrate with
Described metal plug is fixing to be connected；
Grind the first surface of described covering substrate, until exposing described metal plug, described covering substrate
First surface relative with the second surface position of covering substrate.
Alternatively, the degree of depth of described opening is 200 ± 50 μm, and aperture is 20 ± 10 μm.
Alternatively, the material of described testing cushion is copper, and described metal material is copper.
Alternatively, it is binding technique that described testing cushion fixes the method being connected with described metal plug, described
Binding technique includes:
At a temperature of 350 ± 50 DEG C, under the pressure of 40 ± 20KN, metal plug and testing cushion is kept to connect
Touch 10～40min.
Alternatively, the forming process of described metal plug includes: in sidewall and the bottom shape of described opening
Become electricity isolated layer, backward described opening in fill full metal material, to form described metal plug.
Alternatively, the thickness of described electricity isolated layer is 1000～3000。
Present invention also offers a kind of semiconductor device, described semiconductor device includes:
Semiconductor substrate, the first surface of described Semiconductor substrate has components and parts, described Semiconductor substrate
Inside there is surface and be exposed to the testing cushion of Semiconductor substrate first surface, between described components and parts and testing cushion
Noncontact, and described components and parts are electrically connected by the interconnection line in described Semiconductor substrate with testing cushion；
It is covered in the covering substrate on the first surface of described Semiconductor substrate, the second of described covering substrate
Surface and the first surface laminating of described Semiconductor substrate, wherein, offer free in described covering substrate
Chamber, the components and parts in described Semiconductor substrate are positioned at described cavity；
The second surface of described covering substrate and the of covering substrate it is formed through in described covering substrate
The metal plug on one surface, described metal plug is fixing with described testing cushion to be connected, described covering substrate
First surface is relative with the second surface position of covering substrate.
Alternatively, the degree of depth of described metal plug is 200 ± 50 μm, and width is 20 ± 10 μm.
Alternatively, described metal plug includes that metal material and electricity isolated layer, described electricity isolated layer are positioned at
Between described metal material and covering substrate.
Alternatively, the thickness of described electricity isolated layer is 1000～3000。
Alternatively, the metal material in described metal plug is copper, and the material of described testing cushion is copper.
Compared with prior art, technical scheme has the advantage that
First surface in Semiconductor substrate has components and parts, has surface sudden and violent in described Semiconductor substrate
Expose the testing cushion of Semiconductor substrate first surface；Etch the second surface of described covering substrate, formed and use
Cavity in the components and parts accommodated in Semiconductor substrate；Etch described covering substrate second surface, described
Form opening in covering substrate, backward described opening in filler metal material, formed in covering substrate
Metal plug；The second surface of described covering substrate is made to fit with the first surface of Semiconductor substrate afterwards,
The components and parts in described Semiconductor substrate are made to be positioned in the cavity of substrate, and in described covering substrate
Metal plug is fixing with the testing cushion in Semiconductor substrate to be connected；Etch the first surface of described covering substrate,
Until exposing described metal plug so that described metal plug runs through covering substrate first surface and the second table
Face, forms semiconductor device.In the electric performance test operation of above-mentioned semiconductor device, can directly pass through
Described metal plug realizes the test instrunment of components and parts and outside and connects, and completes the electrical property to components and parts
Test step, thus simplify the electric performance test operation of semiconductor device, and improve the electricity of semiconductor device
The success rate that performance test operation is carried out.
Accompanying drawing explanation
Fig. 1～3 is the process schematic of the WAT test of existing MEMS chip；
Fig. 4～10 is the structural representation of the forming method of the semiconductor device that one embodiment of the invention provides
Figure.
Detailed description of the invention
As described in background, in semiconductor fabrication, need partly to lead manufactured
Body device is tested, and as WAT tests, thus finds the problem in manufacture of semiconductor in time, and makees corresponding
Adjust.
But, in existing test process, need to be opened by the semiconductor device of shaping, at semiconductor device
Form opening in the testing cushion of part, and testing needle card is inserted in described opening, with continuity test pad, from
And carry out the test of correspondence.This cumbersome, operation precision requirement is high, not so can cause testing needle card
Damage equivalent risk, thus cause test crash.
To this end, the invention provides the forming method of a kind of semiconductor device and this semiconductor device.?
Directly form the metal plug electrically connected with testing cushion on semiconductor device, thus change traditional employing and survey
Test point card completes the technique of semiconducter device testing, simplifies the test technology process of semiconductor device, and carries
The success rate of high test technology.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
The flowage structure schematic diagram of the forming method of the semiconductor device that Fig. 4～Figure 10 provides for the present embodiment.
Its detailed process includes:
With reference to shown in Fig. 4, it is provided that semi-conductive substrate 100.The upper surface of described Semiconductor substrate 100 is (i.e.,
The first surface of Semiconductor substrate) on there are components and parts 110, described components and parts 110 are raised in described partly leads
The upper surface of body substrate 100.Also there is in described Semiconductor substrate 100 testing cushion 120, described test
The surface of pad 120 is exposed and the upper surface of described Semiconductor substrate 100.Described testing cushion 120 and unit's device
Keep at a certain distance away between part 110, in non-contact structure.Described components and parts 110 and testing cushion 120 are passed through
The interconnection line electrical connection being located in described Semiconductor substrate 100.
Described Semiconductor substrate 100 can be silicon substrate, it is also possible to be germanium, germanium silicon, gallium arsenide substrate or
Silicon-on-insulator substrate, common Semiconductor substrate all can be as the Semiconductor substrate in the present embodiment.
In the present embodiment, described Semiconductor substrate 100 is silicon substrate.
Described components and parts 110 can be the electric elements of arbitrary integrated circuit, or IC chip.
The present embodiment, is as a example by described components and parts by MEMS chip.
In the present embodiment, described testing cushion (test pad) 120 is metal gasket, is chosen as copper lining.
Described Semiconductor substrate 100 is formed described MEMS chip 110 and testing cushion 120, and
Described MEMS chip 110 and the maturation process that electrical connection technique is this area of testing cushion 120, at this
Repeat no more.
With reference to shown in Fig. 5, it is provided that a covering substrate 200, described covering substrate 200 includes that upper surface is (i.e.,
The first surface of covering substrate) 201 and lower surface (that is, the second surface of covering substrate) 202.Described
Covering substrate 200 is for covering the MEMS chip 110 in described Semiconductor substrate 100.
Etch the lower surface 202 of described covering substrate 200, in described covering substrate 200, form opening
210。
In the present embodiment, the degree of depth of described opening 210 is chosen as 200 ± 50 μm, and aperture is 20 ± 10
μm。
Described opening 210 formation process specifically includes: first at the lower surface 202 of described covering substrate 200
Upper formation photoresist layer, the most through exposure and development after technique, forms pattern in described photoresist layer,
And covering substrate 200 described in the photoresist layer after patterning as mask etching, form described opening 210.
Above-mentioned technique is the maturation process of this area, does not repeats them here.
Afterwards, in the opening 210 of described covering substrate 200, metal plug is formed.Described metal plug
Formation process specifically include:
With reference to shown in Fig. 6, in described opening 210, first form one layer of electricity isolated layer 211.Described electric isolution
The thickness of layer 211 is 1000～3000。
In the present embodiment, described electricity isolated layer 211 is chosen as TEOS(tetraethyl orthosilicate) layer, silicon oxide
Layer etc., its formation process is CVD(chemical gaseous phase deposition) technique；Or thermal oxidation technology can be used,
One layer of silicon oxide layer is formed in sidewall and the bottom of described opening 210.211 layers of shape of described electricity isolated layer
One-tenth technique is prior art, does not repeats them here.
With reference to shown in Fig. 7, afterwards, the fuller metal material of filling in described opening 210, to form gold
Belong to connector 220.
In the present embodiment, the metal material used is copper, and it is identical with the material of testing cushion 120, from
And it is easy to follow-up described testing cushion 120 and metal plug binding.
In the present embodiment, in opening 210, the technique of filler metal material includes: can first use such as PVD
(physical vapour deposition (PVD)) technique first one layer of copper seed layer of formation above described electricity isolated layer 211, afterwards,
Electroplating technology is used to form the copper material bed of material on the basis of described copper seed layer, to fill up described opening 210, and
Using CMP(chemical mechanical polishing method later) technique makes the surface of the described copper material bed of material cover with described
The lower surface 202 of lid substrate 200 flushes, thus forms metal plug 220.
With reference to shown in Fig. 8, after forming described metal plug 220, continue to etch described covering substrate 200
Lower surface 202, in described covering substrate 200 formed cavity 230.
The formation process of described cavity 230 includes, first on the lower surface 202 of described covering substrate 200
Cover photoresist layer, the technique such as the most through exposure and development, pattern described photoresist layer；And with pattern
Photoresist layer after change is the lower surface 202 of covering substrate 200 described in mask etching, thus in described covering
Described cavity 230 is formed in substrate 200.Detailed process is the maturation process of this area, does not repeats them here.
Afterwards, with reference to shown in Fig. 9, after forming described cavity 230, described covering substrate 200 is covered
Cover in described Semiconductor substrate 100.Lower surface 202 and the described quasiconductor of described covering substrate 200
The upper surface laminating of substrate 100, described MEMS chip 110 is positioned in described cavity 230, and makes
Described metal plug 220 is fixing with described testing cushion 120 to be connected.
In the present embodiment, described metal plug 220 is key with the described fixing technique being connected of testing cushion 120
Connection technique, detailed process includes:
After described covering substrate 200 is covered in described Semiconductor substrate 100 so that described covering base
Metal plug 220 surface in sheet 200 is affixed with the surface of the testing cushion 120 in Semiconductor substrate 100
Closing, the temperature in regulation reaction chamber is 350 ± 50 DEG C, and pressure is 40 ± 20KN, keeps described metal to insert
Plug 220 contact with testing cushion 120 10～40min(minute).In this process, testing cushion 120 and metal
Copper generation atomic migration in connector 220, thus realize testing cushion 120 and metal plug 220 binding.
Referring next to shown in Figure 10, grind the upper surface 201 of described covering substrate 200, until exposing institute
State metal plug 220.
In the present embodiment, the method for described grinding is chosen as CMP, and concrete can use 0.2～4
The stepping rate of μm/s, 1000～3000 turns/min pad rotating speed grinds described covering substrate 200.
Afterwards, above described Semiconductor substrate 100 and covering substrate 200, use the techniques such as CVD
Metallization medium layer (not shown), to wrap up described covering substrate 200, uses the techniques such as CMP to grind
Dielectric layer so that the surface of described dielectric layer and the upper surface flush of described covering substrate 200.
This enforcement also provides for the semiconductor device used obtained by the forming method of above-mentioned quasiconductor.It is concrete
Shown in structural reference Figure 10, including:
Semiconductor substrate 100, upper surface (that is, the first of Semiconductor substrate of described Semiconductor substrate 100
Surface) there are components and parts 110, in described Semiconductor substrate 100, there is surface and be exposed to Semiconductor substrate
The testing cushion 120 of 100 upper surfaces.Noncontact between described components and parts 110 and testing cushion 120, and pass through
Interconnection line electrical connection in described Semiconductor substrate 100.
It is covered in the covering substrate 200 above described Semiconductor substrate 100, described covering substrate 200 times
The upper surface of surface (that is, the second surface of covering substrate) and described Semiconductor substrate 100 is (i.e..Half
The first surface of conductor substrate) laminating；Wherein, in described covering substrate 200, it is formed with cavity 230,
Described components and parts 110 are positioned at described cavity 230；
Described covering substrate upper surface (that is, covering substrate it is formed through in described covering substrate 200
First surface) and the metal plug 220 of lower surface (that is, the second surface of covering substrate), described gold
Genus connector 220 is fixing with described testing cushion 120 to be connected.
In the present embodiment, the degree of depth of described metal plug 220 is 200 ± 50 μm, and width is 20 ± 10
μm。
Described metal plug 200 includes that metal material and electricity isolated layer 211(are with reference to shown in Fig. 6).Described
Electricity isolated layer 211 wraps described metal material, and be positioned at described metal material and covering substrate 200 it
Between.
In the present embodiment, the thickness of described electricity isolated layer 211 is 1000～3000, material is chosen as TEOS
Or silicon oxide layer dielectric material.
In the present embodiment, being all chosen as of metal material in described metal plug 220 and testing cushion 120
Copper.
Described semiconductor device also includes being covered in the dielectric layer above described Semiconductor substrate 100 (in figure
Do not show), described dielectric layer wraps described covering substrate 200 periphery, and dielectric layer upper surface and described
The upper surface flush of covering substrate 200.
In the test process of described semiconductor device, run through the described upper and lower surface of covering substrate 200
Metal plug 220 is directly connected to the test instrunment of outside, to realize the testing electrical property of semiconductor device.Phase
Ratio is in the test step of existing employing testing needle card, and it not only avoid and reopens semiconductor device, dew
Go out the cumbersome process such as testing cushion, and avoid the defects such as testing needle card damage.It greatly improves and partly lead
The convenient degree of body device electric test and the success rate of test step, to improve semiconducter device testing
Efficiency.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (5)
1. the forming method of a semiconductor device, it is characterised in that including:
Thering is provided Semiconductor substrate, the first surface of described Semiconductor substrate has components and parts, and described quasiconductor serves as a contrast
There is surface at the end and be exposed to the testing cushion of Semiconductor substrate first surface, described components and parts and testing cushion
Between noncontact, and by the interconnection line in described Semiconductor substrate by described components and parts and testing cushion electricity
Connect；
Covering substrate is provided, etches the second surface of described covering substrate, formed in described covering substrate and open
Mouthful；
In described opening, fill full metal material, form metal plug, wherein, the shape of described metal plug
One-tenth process includes: form electricity isolated layer at the sidewall of described opening and bottom, backward described opening
The full metal material of interior filling, to form described metal plug；
Etch the second surface of described covering substrate, in described covering substrate, form cavity；
By the second surface laminating of the first surface of described Semiconductor substrate with described covering substrate, make described half
Components and parts on conductor substrate are positioned at described cavity, and make testing cushion in described Semiconductor substrate with
Described metal plug is fixing to be connected；
Grind the first surface of described covering substrate, until exposing described metal plug, described covering substrate
First surface is relative with the second surface position of covering substrate；
In the test process of the electrical property to described semiconductor device, realize unit's device by described metal plug
Part and the connection of outside test instrunment, to realize the electric performance test to described semiconductor device.
2. the forming method of semiconductor device as claimed in claim 1, it is characterised in that described opening deep
Degree is 200 ± 50 μm, and aperture is 20 ± 10 μm.
3. the forming method of semiconductor device as claimed in claim 1, it is characterised in that described testing cushion
Material is copper, and described metal material is copper.
4. the forming method of semiconductor device as claimed in claim 1, it is characterised in that described testing cushion with
It is binding technique that described metal plug fixes the method for connection, and described binding technique includes:
At a temperature of 350 ± 50 DEG C, under the pressure of 40 ± 20KN, metal plug is kept to contact with testing cushion
10～40min.
5. the forming method of semiconductor device as claimed in claim 1, it is characterised in that described electricity isolated layer
Thickness be
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| EP2009710A2 (en) * | 2007-06-27 | 2008-12-31 | Nihon Dempa Kogyo Co., Ltd. | Piezoelectric component and manufacturing method thereof |
| CN101350342A (en) * | 2007-07-19 | 2009-01-21 | 联华电子股份有限公司 | Integrated circuit structure for test |
| CN102363520A (en) * | 2011-11-04 | 2012-02-29 | 中国科学院半导体研究所 | Wafer level three-dimensional encapsulation method for micro-electro-mechanical system (MEMS) device |
| CN202988703U (en) * | 2012-11-20 | 2013-06-12 | 苏州敏芯微电子技术有限公司 | Micro-electromechanical system device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7393758B2 (en) * | 2005-11-03 | 2008-07-01 | Maxim Integrated Products, Inc. | Wafer level packaging process |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1508968A (en) * | 2002-12-19 | 2004-06-30 | ������������ʽ���� | Electronic element and its manufacturing method |
| EP2009710A2 (en) * | 2007-06-27 | 2008-12-31 | Nihon Dempa Kogyo Co., Ltd. | Piezoelectric component and manufacturing method thereof |
| CN101350342A (en) * | 2007-07-19 | 2009-01-21 | 联华电子股份有限公司 | Integrated circuit structure for test |
| CN102363520A (en) * | 2011-11-04 | 2012-02-29 | 中国科学院半导体研究所 | Wafer level three-dimensional encapsulation method for micro-electro-mechanical system (MEMS) device |
| CN202988703U (en) * | 2012-11-20 | 2013-06-12 | 苏州敏芯微电子技术有限公司 | Micro-electromechanical system device |
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