CN104660370B - The processing method and equipment of sequence - Google Patents
The processing method and equipment of sequence Download PDFInfo
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- CN104660370B CN104660370B CN201310604004.6A CN201310604004A CN104660370B CN 104660370 B CN104660370 B CN 104660370B CN 201310604004 A CN201310604004 A CN 201310604004A CN 104660370 B CN104660370 B CN 104660370B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
- H04L1/0011—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding applied to payload information
Abstract
An embodiment of the present invention provides a kind of processing method of sequence and equipment, this method includes：The first bit sequence of transmitting terminal pair carries out channel coding processing, to obtain the second bit sequence；Transmitting terminal is interleaved processing to second bit sequence, and to obtain third bit sequence, third bit sequence includes bit 0 or bit 1；Transmitting terminal obtains segmentation ratio according to modulation system；Transmitting terminal is according to the segmentation ratio, third bit sequence is handled, to obtain the 4th bit sequence, the 4th bit sequence includes bit 0 or bit 1, and the ratio shared by bit 0 and bit 1 in the 4th bit sequence is different from the bit 0 in third bit sequence and the ratio shared by bit 1；Transmitting terminal is modulated processing to the 4th bit sequence；Transmitting terminal sends the bit sequence obtained after modulation treatment to receiving terminal.The technical solution provided according to embodiments of the present invention, to realize the channel capacity for improving wireless communication system.
Description
【Technical field】
The present invention relates to signal processing technology more particularly to the processing methods and equipment of a kind of sequence.
【Background technology】
In the prior art, the Transmission system of bit sequence, in such as bidirectional relay system based on physical-layer network coding,
One sending device and the second sending device can send bit sequence to receiving device (such as relay node) simultaneously.It is sent with first
For equipment, the first sending device first carries out low density parity check code (Low Density to the bit sequence of input
Parity Check Code, LDPC) channel coding processing, processing then is interleaved to bit sequence again, finally to bit sequence
Row are modulated processing, and are sent to receiving device by noisy communication channel, wherein, will when being modulated processing to bit sequence
Bit sequence is mapped on the corresponding planisphere of modulation system of modulator, forms corresponding constellation point, and a constellation point is exactly
One symbolic information, each symbolic information are that equiprobability is sent to receiving device, and sending probability is uniformly distributed.First sends
Equipment and the second sending device be respectively received receiving device transmission symbolic information after, to symbolic information carry out demodulation process,
Deinterleave processing and channel decoding processing；By taking the first sending device as an example, the first sending device knows the symbol transmitted by itself
Information, therefore the first sending device can utilize bit exclusive or algorithm, and the second sending device is obtained from the symbolic information of reception
The symbolic information of transmission.Similarly, for the second sending device, the first sending device it is also known that itself send symbolic information, because
This second sending device can also utilize bit exclusive or algorithm, and the transmission of the first sending device is obtained from the symbolic information of reception
Symbolic information, in this way, realizing the exchange of bit sequence between the first sending device and the second sending device.
However, bit sequence transmission method cannot reach maximum letter of the wireless communication system under current transmission mode at present
Road capacity.
【Invention content】
In view of this, an embodiment of the present invention provides a kind of processing method of sequence and equipment, to realize raising channel radio
The channel capacity of letter system.
In a first aspect, an embodiment of the present invention provides a kind of processing methods of sequence, including：
The first bit sequence of transmitting terminal pair carries out channel coding processing, to obtain the second bit sequence；
The transmitting terminal is interleaved processing to second bit sequence, to obtain third bit sequence, the third
Bit sequence includes bit 0 or bit 1；
The transmitting terminal obtains segmentation ratio according to modulation system；
The transmitting terminal is handled the third bit sequence according to the segmentation ratio, to obtain the 4th bit
Sequence, the 4th bit sequence include bit 0 or bit 1, shared by the bit 0 and bit 1 in the 4th bit sequence
Ratio is different from the bit 0 in the third bit sequence and the ratio shared by bit 1；
The transmitting terminal is modulated processing to the 4th bit sequence；
The transmitting terminal sends the bit sequence obtained after the modulation treatment to receiving terminal.
In the first possible realization method of first aspect, the 4th bit sequence include the 5th bit sequence and
6th bit sequence, the transmitting terminal are handled the third bit sequence according to the segmentation ratio, to obtain the 4th
Bit sequence specifically includes：
According to the segmentation ratio, processing is split to the third bit sequence, with obtain the 6th bit sequence and
7th bit sequence；
7th bit sequence is handled, to obtain the 8th bit sequence；
Processing is interleaved to the 8th bit sequence, to obtain the 5th bit sequence.
The possible realization method of with reference to first aspect the first, in second of possible realization method of first aspect
In, the length of the 7th bit sequence and the ratio of the length of the 6th bit sequence are equal to the segmentation ratio.
The possible realization method of with reference to first aspect the first or second of possible realization method, in first aspect
It is described that 7th bit sequence is handled in the third possible realization method, to obtain the 8th bit sequence, specifically
Including：
Predeterminated position is inserted at least one bit 0 in the 7th bit sequence, to obtain the 8th bit sequence；
Alternatively,
Predeterminated position is inserted at least one bit 1 in the 7th bit sequence, to obtain the 8th bit sequence.
The third possible realization method with reference to first aspect, in the 4th kind of possible realization method of first aspect
In, the method further includes：
If predeterminated position is inserted at least one bit 0 in the 7th bit sequence, in the 7th bit sequence
Predeterminated position is inserted at least two bits 1；Alternatively,
If predeterminated position is inserted at least one bit 1 in the 7th bit sequence, in the 7th bit sequence
Predeterminated position is inserted at least two bits 0.
Second aspect, an embodiment of the present invention provides a kind of processing methods of sequence, including：
Receiving terminal receives the sequence that at least two transmitting terminals are sent；
The receiving terminal carries out demodulation process to the sequence, described to obtain the sequence of the first log-likelihood ratio LLR value
It includes bit 0 or bit 1 that the sequence of first LLR value has mapping relations, first bit sequence with the first bit sequence；
The receiving terminal handles the sequence of first LLR value, to obtain the sequence of the second LLR value, described the
The sequence of two LLR values and the second bit sequence have a mapping relations, and second bit sequence includes bit 0 or bit 1, and described the
The ratio shared by bit 0 and bit 1 in one bit sequence is different from 1 institute of bit 0 and bit in second bit sequence
The ratio accounted for, second bit sequence are the bit sequence handled according to modulation system first bit sequence；
The receiving terminal carries out channel decoding processing to the sequence of second LLR value, to obtain at least two sequence
The court verdict of the bit exclusive or of row.
In the first possible realization method of second aspect, the sequence of first LLR value includes third LLR value
The sequence of sequence and the 4th LLR value, the receiving terminal handle the sequence of first LLR value, to obtain the second LLR value
Sequence, specifically include：
Processing is deinterleaved to the sequence of the third LLR value, to obtain the sequence of the 5th LLR value；
The sequence of 5th LLR value is handled, to obtain the sequence of the 6th LLR value；
The sequence for merging the sequence and the 4th LLR value of the 6th LLR value, to obtain the sequence of the second LLR value.
In conjunction with the first possible realization method of second aspect, in second of possible realization method of second aspect
In, the ratio of the corresponding bit sequence of the sequence bit sequence corresponding with the sequence of the 4th LLR value of the 6th LLR value
Equal to segmentation ratio, the segmentation ratio is obtained according to the modulation system.
In conjunction with second of possible realization method of second aspect, in the third possible realization method of second aspect
In, the sequence to the 5th LLR value is handled, to obtain the sequence of the 6th LLR value, including：
At least one 1 is deleted in the predeterminated position of the corresponding bit sequence of sequence of the 5th LLR value, described in acquisition
The sequence of 6th LLR value；Alternatively,
At least one 0 is deleted in the predeterminated position of the corresponding bit sequence of sequence of the 5th LLR value, described in acquisition
The sequence of 6th LLR value.
In conjunction with the third possible realization method of second aspect, in the 4th kind of possible realization method of second aspect
In, the method further includes：
If at least one bit 1 is deleted in the predeterminated position of the corresponding bit sequence of sequence of the 5th LLR value, in institute
The predeterminated position for stating the corresponding bit sequence of sequence of the 5th LLR value deletes at least two bits 0；Alternatively,
If at least one bit 0 is deleted in the predeterminated position of the corresponding bit sequence of sequence of the 5th LLR value, in institute
The predeterminated position for stating the corresponding bit sequence of sequence of the 5th LLR value deletes at least two bits 1.
The third aspect, an embodiment of the present invention provides a kind of processing equipments of sequence, including：
Channel encoding unit, for carrying out channel coding processing to the first bit sequence, to obtain the second bit sequence；
Interleave unit, for being interleaved processing to second bit sequence, to obtain third bit sequence, described
Bit sequence includes bit 0 or bit 1；
Processing unit is used for：
According to modulation system, segmentation ratio is obtained；
According to the segmentation ratio, the third bit sequence is handled, to obtain the 4th bit sequence, described
Four bit sequences include bit 0 or bit 1, and the bit 0 in the 4th bit sequence and the ratio shared by bit 1 are different from institute
State the bit 0 in third bit sequence and the ratio shared by bit 1；
Modulation unit, for being modulated processing to the 4th bit sequence；
Transmission unit, for sending the bit sequence obtained after the modulation treatment to receiving terminal.
In the first possible realization method of the third aspect, the 4th bit sequence include the 5th bit sequence and
6th bit sequence, the processing unit, is specifically used for：
According to modulation system, segmentation ratio is obtained；
According to the segmentation ratio, processing is split to the third bit sequence, with obtain the 6th bit sequence and
7th bit sequence；
7th bit sequence is handled, to obtain the 8th bit sequence；
Processing is interleaved to the 8th bit sequence, to obtain the 5th bit sequence.
In conjunction with the first possible realization method of the third aspect, in second of possible realization method of the third aspect
In, the length of the 7th bit sequence and the ratio of the length of the 6th bit sequence are equal to the segmentation ratio.
In conjunction with the first possible realization method or second of possible realization method of the third aspect, in the third aspect
In the third possible realization method, the processing unit is specifically used for：
According to modulation system, segmentation ratio is obtained；
According to the segmentation ratio, processing is split to the third bit sequence, with obtain the 6th bit sequence and
7th bit sequence；
Predeterminated position is inserted at least one bit 0 in the 7th bit sequence, to obtain the 8th bit sequence；
Alternatively, predeterminated position is inserted at least one bit 1 in the 7th bit sequence, to obtain the 8th bit sequence；
Processing is interleaved to the 8th bit sequence, to obtain the 5th bit sequence.
In conjunction with the third possible realization method of the third aspect, in the 4th kind of possible realization method of the third aspect
In, the processing unit is specifically used for：
According to modulation system, segmentation ratio is obtained；
According to the segmentation ratio, processing is split to the third bit sequence, with obtain the 6th bit sequence and
7th bit sequence；
If predeterminated position is inserted at least one bit 0 in the 7th bit sequence, in the 7th bit sequence
Predeterminated position is inserted at least two bits 1, to obtain the 8th bit sequence, if alternatively, in the 7th bit sequence
Predeterminated position is inserted at least one bit 1, and predeterminated position is inserted at least two bits 0 in the 7th bit sequence, to obtain
Obtain the 8th bit sequence；
Processing is interleaved to the 8th bit sequence, to obtain the 5th bit sequence.
Fourth aspect, an embodiment of the present invention provides a kind of processing equipments of sequence, including：
Receiving unit, the sequence for receiving the transmission of at least two transmitting terminals；
Demodulating unit, for carrying out demodulation process to the sequence, to obtain the sequence of the first log-likelihood ratio LLR value,
It includes bit 0 or bit 1 that the sequence of first LLR value has mapping relations, first bit sequence with the first bit sequence；
Processing unit is handled for the sequence to first LLR value, described to obtain the sequence of the second LLR value
The sequence of second LLR value and the second bit sequence have a mapping relations, and second bit sequence includes bit 0 or bit 1, described
The ratio shared by bit 0 and bit 1 in first bit sequence is different from the bit 0 in second bit sequence and bit 1
Shared ratio, second bit sequence are the bit sequence handled according to modulation system first bit sequence
Row；
Channel decoding unit, for carrying out channel decoding processing to the sequence of second LLR value, with described in obtaining at least
The court verdict of the bit exclusive or of two sequences.
In the first possible realization method of fourth aspect, the sequence of first LLR value includes third LLR value
The sequence of sequence and the 4th LLR value, the processing unit are specifically used for：
Processing is deinterleaved to the sequence of the third LLR value, to obtain the sequence of the 5th LLR value；
The sequence of 5th LLR value is handled, to obtain the sequence of the 6th LLR value；
The sequence for merging the sequence and the 4th LLR value of the 6th LLR value, to obtain the sequence of the second LLR value.
In the first possible realization method in conjunction with fourth aspect, in second of possible realization method of fourth aspect
In, the ratio of the corresponding bit sequence of the sequence bit sequence corresponding with the sequence of the 4th LLR value of the 6th LLR value
Equal to segmentation ratio, the segmentation ratio is obtained according to the modulation system.
In conjunction with second of possible realization method of fourth aspect, in the third possible realization method of fourth aspect
In, the processing unit is specifically used for：
Processing is deinterleaved to the sequence of the third LLR value, to obtain the sequence of the 5th LLR value；
At least one bit 1 is deleted in the predeterminated position of the corresponding bit sequence of sequence of the 5th LLR value, to obtain
The sequence of 6th LLR value, alternatively, the corresponding bit sequence of sequence of the 5th LLR value predeterminated position delete to
A few bit 0, to obtain the sequence of the 6th LLR value；
The sequence for merging the sequence and the 4th LLR value of the 6th LLR value, to obtain the sequence of the second LLR value.
In conjunction with the third possible realization method of fourth aspect, in the 4th kind of possible realization method of fourth aspect
In, the processing unit is specifically used for：
Processing is deinterleaved to the sequence of the third LLR value, to obtain the sequence of the 5th LLR value；
If at least one bit 1 is deleted in the predeterminated position of the corresponding bit sequence of sequence of the 5th LLR value, in institute
The predeterminated position for stating the corresponding bit sequence of sequence of the 5th LLR value deletes at least two bits 0 to obtain the 6th LLR value
Sequence, if alternatively, the predeterminated position in the corresponding bit sequence of sequence of the 5th LLR value deletes at least one bit 0,
At least two bits 1 are deleted to obtain the described 6th in the predeterminated position of the corresponding bit sequence of sequence of the 5th LLR value
The sequence of LLR value；
The sequence for merging the sequence and the 4th LLR value of the 6th LLR value, to obtain the sequence of the second LLR value.
As can be seen from the above technical solutions, the embodiment of the present invention has the advantages that：
According to the knowwhy of information theory, only when the sending probability Gaussian distributed of symbolic information, i.e., by energy
Lower symbolic information is sent with higher sending probability, and the higher symbolic information of energy is sent with lower sending probability
When going out, the channel capacity of wireless communication system can just reach maximum value, therefore, in the embodiment of the present invention, to bit sequence into
Row processing so that the number of bit has differences in the bit sequence obtained after processing, to such bit sequence into
The sending probability and symbol energy Gaussian distributed of the symbolic information obtained after row modulation, therefore wireless communication system can be improved
The channel capacity of system.
【Description of the drawings】
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this field
For those of ordinary skill, without having to pay creative labor, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the flow diagram of the processing method one for the sequence that the embodiment of the present invention is provided；
Fig. 2 is the schematic diagram for the transmitting terminal that the embodiment of the present invention is provided；
Fig. 3 is the flow diagram of the processing method two for the sequence that the embodiment of the present invention is provided；
Fig. 4 is the schematic diagram for the receiving terminal that the embodiment of the present invention is provided；
Fig. 5 is the flow diagram of the embodiment of the processing method for the sequence that the embodiment of the present invention is provided；
Fig. 6 is the schematic diagram of the application scenarios of the embodiment of the processing method for the sequence that inventive embodiments are provided；
Fig. 7 (a)~Fig. 7 (c) is the planisphere of the embodiment of the present invention；
Fig. 8 (a)~Fig. 8 (b) is the sending probability and symbol energy Gaussian distributed of symbolic information of the embodiment of the present invention
Schematic diagram；
Fig. 9 is the symbolic information sending probability and symbol energy after the symbolic information superposition of two transmitting terminals of the embodiment of the present invention
Measure the schematic diagram of Gaussian distributed；
Figure 10 is the contrast schematic diagram of error performance of the embodiment of the present invention；
Figure 11 is the functional block diagram of the processing equipment one for the sequence that the embodiment of the present invention is provided；
Figure 12 is the structural schematic diagram of the processing equipment one for the sequence that the embodiment of the present invention is provided；
Figure 13 is the functional block diagram of the processing equipment two for the sequence that the embodiment of the present invention is provided；
Figure 14 is the structural schematic diagram of the processing equipment two for the sequence that the embodiment of the present invention is provided.
【Specific implementation mode】
For a better understanding of the technical solution of the present invention, being retouched in detail to the embodiment of the present invention below in conjunction with the accompanying drawings
It states.
It will be appreciated that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Base
Embodiment in the present invention, those of ordinary skill in the art obtained without creative efforts it is all its
Its embodiment, shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of processing method of sequence, referring to FIG. 1, what it was provided by the embodiment of the present invention
The flow diagram of the processing method one of sequence is processing flow schematic diagram of the transmitting terminal to bit sequence, as shown, the party
Method includes the following steps：
Step 101, the first bit sequence of transmitting terminal pair carries out channel coding processing, to obtain the second bit sequence.
Specifically, referring to FIG. 2, transmitting terminal in the Transmission system of information, can include at least two sending devices (figure
Two sending devices, i.e. sending device A and sending device B are only provided in 2)；For each sending device A, in sending device A
Channel encoding unit receives the first bit sequence of input, channel coding processing is carried out to the first bit sequence, to obtain channel
The code word obtained after coded treatment, the code word are the second bit sequence, and channel encoding unit is sent out to the interleave unit of sending device
Give second bit sequence.
Wherein, the channel encoding unit can be LDPC channel encoding units, be said by taking LDPC channel encoding units as an example
It is bright to bit sequence carry out channel coding processing method be：According to input LDPC channel encoding units, LDPC code is signal number
Linear block codes is multiplied with generator matrix each bit sequence of the signal number in obtain corresponding check code, utilize
The check code arrived forms LDPC code word with bit sequence, which is exactly the second bit sequence obtained after channel coding is handled
Row.
Wherein, the sending device can be base station or terminal etc.；It is K that first bit sequence of input, which can be length,C
Bit sequence XA, bit sequence XAIt is all made of bit 0 and bit 1, and bit 0 is identical with the number of bit 1；The letter
The code check of road coding unitIt is N that channel encoding unit, which exports length,CCode word, which is exactly the second bit sequence
uA。
Wherein, if the system that sending device and receiving device form be based on bit XOR operation and energy it is equally distributed
The wireless communication system of physical-layer network coding transmission technology, then bit 0 is equal with the quantity of bit 1 in the first bit sequence,
Bit 0 is equal with the quantity of bit 1 in second bit sequence.
Step 102, the transmitting terminal is interleaved processing to second bit sequence, to obtain third bit sequence,
The third bit sequence includes bit 0 or bit 1.
Specifically, referring to FIG. 2, the interleave unit of sending device obtains the second bit sequence u from channel encoding unitA,
To the second bit sequence uAIt is interleaved processing, to obtain third bit sequence vA, the third bit sequence vAAll by bit
0 and bit 1 form, and bit 0 is identical with the number of bit 1.
Wherein, the second bit sequence of interleave unit pair uAThe method for being interleaved processing can be：
As unit of the number of bits that the symbol in the modulation system of modulator is included, i.e., with the corresponding symbol of modulation system
Number size is unit, and the bit sequence received is stored in a random access memory (Random Access Memory, RAM)
In, until all bit sequences all store in RAM.
Then interleave unit is needed from bit sequence is extracted in RAM as unit of symbol, and since the 1st RAM, extraction is every
The 1st row symbol of a RAM after the 1st row symbol for having extracted all RAM, then since the 1st RAM, extracts the 2nd of each RAM
Row symbol, and so on；The symbol extracted is sent to map unit by last interleave unit according to sequence of extraction.
For example, interleave unit is to be interleaved processing to the bit sequence obtained after coding as unit of symbol, with modulation
For unit is 1024-QAM, interleave depth is 108 LDPC code words.Interleave depth is the LDPC code frame number of storage, storage
Total bit number is that LDPC frame lengths are multiplied by interleave depth according to amount.The each code element of 1024-QAM includes 10 bits, and interleave unit will be with
10 bits are that the bit data received is stored in RAM by unit, and the receive the 1st 10 bits are stored in first by interleave unit
2nd 10 bits are stored in the 2nd row of first RAM by the first row of RAM, and so on, until (n-1)th 10 bit is stored in
The (n-1)th row of first RAM, first RAM are filled with；Then n-th 10 bits are stored in the first row of second RAM, (n+1)th
A 10 bit is stored in the second row of second RAM, and so on, until second RAM is filled with, and so on, until
The bit sequence obtained after the coding received is all stored in RAM by interleave unit.
Here, the bit sequence that interleave unit is sent to map unit is to the second bit sequence uAAfter reconfiguring
Bit sequence vA, that is to say, that the second bit sequence u that interleave unit will be obtained as unit of symbol after channel codingAIt breaks up,
The third bit sequence v after reconfiguring is exported againA；The second bit sequence of interleave unit pair uAInterleaving treatment do not change
Two bit sequence uAEssence, but change the second bit sequence uAStructural order, error burst is broken up, noisy communication channel is made
Error burst in transmission process is decentralized to greatest extent, thus in third bit sequence 0 and 1 quantity it is still equal.
Step 103, the transmitting terminal obtains segmentation ratio according to modulation system.
Specifically, as shown in Fig. 2, map unit further comprises serial to parallel conversion module, mapping block and interleaving block.
Serial to parallel conversion module receives third bit sequence v from interleave unitA, need to divide the third bit sequence
Processing is cut, by third bit sequence vAIt is divided into two-way bit sequence, here, serial to parallel conversion module is needed according to certain segmentation
Ratio divides third bit sequence, and therefore, serial to parallel conversion module can obtain segmentation ratio according to modulation system；For example, modulation
The modulation system of unit is the pulse amplitude modulation (Pulse Amplitude Modulation, 4PAM) of 4 level, then the ration of division
Example is 1：2.
Step 104, the transmitting terminal is handled the third bit sequence according to the segmentation ratio, to obtain
4th bit sequence, the 4th bit sequence include bit 0 or bit 1, bit 0 and bit in the 4th bit sequence
Ratio shared by 1 is different from the bit 0 in the third bit sequence and the ratio shared by bit 1.
Specifically, as shown in Fig. 2, map unit further comprises serial to parallel conversion module, mapping block and interleaving block.
First, serial to parallel conversion module is split processing according to segmentation ratio to the third bit sequence, by third ratio
Special sequence vAIt is divided into two-way bit sequence, i.e. first via bit sequence and the second road bit sequence, wherein first via bit sequence
Row include the 7th bit sequence dA, the second road bit sequence includes the 6th bit sequence sA2；Serial to parallel conversion module is by the 7th bit
Sequence dAIt is sent to mapping block, by the 6th bit sequence sA2It is transmitted directly to modulation unit；The obtained for dividing processing
Six bit sequences and the 7th bit sequence, the ratio of the length of the 7th bit sequence and the length of the 6th bit sequence
Equal to the segmentation ratio.
Secondly, mapping block receives the 7th bit sequence d that serial to parallel conversion module is sentA, to the 7th bit sequence dA
Mapping processing is carried out, corresponding 8th bit sequence c is obtainedA；Mapping block is by the 8th bit sequence c of acquisitionAIt is sent to intertexture
Module.
Finally, interleaving block receives the 8th bit sequence c that mapping block is sentA, and to the 8th bit sequence cAInto
Row interleaving treatment obtains corresponding 5th bit sequence sA1；Interleaving block is by the 5th bit sequence sA1It is sent to modulation unit；
Here, to each 8th bit sequence cAThe method for being interleaved processing can refer to interleave unit pair second in step 102 and compare
The method that special sequence is interleaved processing.
For example, the 7th bit sequence d of mapping block pairAMapping processing is carried out to refer in the 7th bit sequence dAIn preset
At least one bit 0 is inserted into position, is either inserted at least one bit 1 or is inserted at least two bits 0 and at least one ratio
Spy 1, or be inserted at least one 0 and at least two bit 1 of bit so that including the 5th bit sequence and the 6th bit sequence
In 4th bit sequence, including bit 0 number and the number of bit 1 have a certain difference, such modulation unit pair
After 4th bit sequence is modulated, sending probability and the symbol energy of the symbolic information of acquisition meet Gaussian Profile.
Due in the 7th bit sequence dAMiddle predeterminated position is inserted at least one bit 0, alternatively, in the 7th bit sequence dA
Middle predeterminated position is inserted at least one bit 1, optionally, in the 7th bit sequence dAMiddle predeterminated position is inserted at least one bit
When 0, it can be inserted at least two bits 1 simultaneously, alternatively, in the 7th bit sequence dAMiddle predeterminated position is inserted at least one bit
When 1, it can be inserted at least two bits 0 simultaneously, then the 8th bit sequence c obtainedAThe number of middle bit 0 and bit 1 differs,
That is the 8th bit sequence cAThe number of middle bit 1 is more than the number or the 8th bit sequence c of bit 0AThe number of middle bit 0 is more than
The number of bit 1；Preferably, in order to enable the preferable Gaussian distributed of the sending probability of symbolic information, it is required that the 8th ratio
The number of bit 0 is much larger than the number of bit 0 much larger than the number of bit 1 or the number of bit 1 in special sequence, therefore, right
Each 7th bit sequence dAThe method of the mapping processing of progress is identical, i.e. the 7th bit sequence dAIn all be inserted into it is at least one
Bit 0 or the 7th bit sequence dAIn be all to be inserted at least one bit 1, in this way, the 8th bit sequence c obtainedAMiddle ratio
The number of spy 0 is more than at least one 7th bit sequence dAThe number of middle bit 0, alternatively, the 8th bit sequence cAIn
1 number is more than at least one 7th bit sequence dAIn 1 number.
Wherein, mapping block is to the 7th bit sequence d that receivesALinear Mapping is carried out, corresponding 8th bit sequence is obtained
Arrange cA, for example, Linear Mapping needs to meet：dA1∈ I, dA2∈ I,cA11∈ O, cA12∈ O,Wherein, dA1、dA2、dA3It is at least one 8th bit sequence that mapping block obtains to belong to set I, O
Arrange cASet, cA11、cA12、cA13Belong to set O, cA11、cA12、cA13Respectively dA1、dA2、dA3Mapping processing result.
Here, when carrying out mapping processing to bit sequence, have the characteristics that Linear Mapping, mapping are simple, it can be effectively real
The sending probability of existing bit sequence meets Gaussian Profile with symbol energy.
Step 105, the transmitting terminal is modulated processing to the 4th bit sequence.
Specifically, modulation unit receives the 4th bit sequence that map unit is sent, the 4th bit sequence includes from reflecting
Penetrate the 5th bit sequence s that the interleaving block of unit receivesA1, and received from the serial to parallel conversion module of map unit the 6th ratio
Special sequence sA2；The 4th bit sequence of modulation unit pair is modulated processing, to obtain symbolic information bA。
Wherein, the method that the 4th bit sequence of modulation unit pair is modulated processing is：Modulation unit is according to the 5th bit
Sequence sA1Planisphere is divided into different sub- planispheres, then according to the 6th bit sequence sA2Constellation is selected in sub- planisphere
Point, to realize modulation, at least one constellation point selected is exactly symbolic information.
With in the 7th bit sequence dAFor middle insertion bit 0, due to the 7th bit sequence dAMiddle insertion bit 0, then the 4th
The number of bit 0 is more than the number of bit 1 in bit sequence, therefore the 4th bit sequence is mapped to planisphere, obtained star
In seat point, the selected probability of the sub- planisphere that is started with bit 0 be more than be selected with the sub- planisphere that bit 1 start it is general
Rate, therefore in obtained constellation point, the probability of bit 0 is more than the probability of bit 1 so that include bit 0 in the constellation point sent out
Probability be more than and include the probability of bit 1, i.e., the sending probability of constellation point is higher than with bit in the sub- planisphere started with bit 0
1 beginning sub- planisphere in constellation point sending probability, and in the sub- planisphere due to being started with bit 0 constellation point apart from constellation
The origin of figure is closer, and closer apart from constellation primitive point, the symbol energy of symbolic information is lower, therefore, realizes the lower star of energy
Seat point can be sent out with higher sending probability.According to the knowwhy of information theory, only when the sending probability of symbolic information with
When symbol energy Gaussian distributed, i.e., the lower symbolic information of symbol energy is sent with higher sending probability, is accorded with
When number higher symbolic information of energy is sent with lower sending probability, the channel capacity of wireless communication system can just reach
Maximum value, therefore after the bit sequence of mapping processing is using modulation treatment, symbolic information is sent to noisy communication channel, energy
Enough so that the channel capacity of wireless communication system can just reach maximum value.
Step 106, the transmitting terminal sends the bit sequence obtained after the modulation treatment to receiving terminal.
Specifically, modulation unit is by the symbolic information b of acquisitionAIt is sent in the noisy communication channel, receiving device will be by making an uproar
Acoustic channel receives symbolic information bA。
Similarly, for other transmitting terminals, sending device B as shown in Figure 2 carries out 101~step 106 of above-mentioned steps
Flow, for example, sending device B is by symbolic information bBIt is sent in the noisy communication channel, receiving device will be connect by noisy communication channel
Receive symbolic information bB。
The embodiment of the present invention provides a kind of processing method of bit sequence, referring to FIG. 3, it is carried by the embodiment of the present invention
The flow diagram of the processing method two of the sequence of confession is processing flow schematic diagram of the receiving terminal to sequence, as shown, the party
Method includes the following steps：
Step 301, receiving terminal receives the sequence that at least two transmitting terminals are sent.
Specifically, receiving terminal includes a receiving device, such as trunking；The receiving unit of receiving device receives transmitting terminal
At least two sending devices in the sequence that sends of each sending device, i.e. receiving device receives at least two sequences, then connects
Receive the demodulating unit that the sequence received is sent to receiving device by unit；For example, as shown in figure 4, sending device A is sent to and makes an uproar
The symbolic information b of Acoustic channelAIt indicates, symbolic information bABecome sequences y after the transmission of noisy communication channelA, similarly, transmission is set
Standby B is sent to the symbolic information b of noisy communication channelBIt indicates, symbolic information bBBecome sequences y after the transmission of noisy communication channelB；
The sequence that demodulating unit is received from noisy communication channel is expressed as r, wherein r=yA+yB+ n, n are the noise in noisy communication channel.
Step 302, the receiving terminal carries out demodulation process to the sequence, to obtain the first log-likelihood ratio LLR value
Sequence, the sequence of first LLR value and the first bit sequence have a mapping relations, first bit sequence include bit 0 or
Bit 1.
Specifically, demodulating unit receives the sequence that above-mentioned receiving unit is sent, bit exclusive or algorithm is then utilized, to receiving
At least two sequences arrived carry out physical layer network demodulation process, obtain first after the bit XOR operation of at least two sequences
The sequence of log-likelihood ratio (Log Likelihood Ratio, LLR) value, the sequence of first LLR value includes third LLR valueSequence and the 4th LLR valueSequence.
By taking sending device A and sending device B as an example, the sequence of third LLR value is the 5th bit sequence s of sending device AA1
With the 5th bit sequence s of sending device BB1Bit exclusive or resultLLR value after noisy communication channelSequence, the sequence of the 4th LLR value is the 6th bit sequence s of sending device AA2With the 6th of sending device B the
Bit sequence sB2Bit exclusive or resultLLR value after noisy communication channelSequence.
The sequence of first LLR value is sent to processing unit by demodulating unit.
In the present embodiment, receiving device can be two-way relay nodes；Demodulating unit can be that physical layer network demodulation is single
Member.
Step 303, the receiving terminal handles the sequence of first LLR value, to obtain the sequence of the second LLR value
Row, it includes bit 0 or ratio that sequence and the second bit sequence of second LLR value, which have mapping relations, second bit sequence,
Spy 1, the bit 0 in first bit sequence and the ratio shared by bit 1 are different from the bit 0 in second bit sequence
With the ratio shared by bit 1, second bit sequence handles first bit sequence according to modulation system
Bit sequence.
Specifically, referring to FIG. 4, processing unit includes de-interleaving block, De-mapping module and parallel serial conversion module.
First, de-interleaving block receives the third LLR value that modulation unit is sentSequence, to the 3rd LLR
ValueSequence be deinterleaved processing, that is, the inverse process of above-mentioned interleaving block is executed, to obtain the 5th LLR valueSequence, de-interleaving block is by the 5th LLR valueSequence be sent to De-mapping module.
Then, De-mapping module receives the 5th LLR value that de-interleaving block is sentSequence, to the 5th
LLR valueSequence carry out demapping processing, with obtain the 6th LLR value sequence, that is, execute mapping processing it is inverse
Processing；For example, in the 5th LLR valueThe corresponding bit sequence of sequence in predeterminated position delete it is at least one
0, to obtain the sequence of the 6th LLR value；Alternatively, in the 5th LLR valueThe corresponding bit sequence of sequence it is default
Position deletes at least one 1, to obtain the sequence of the 6th LLR value；Alternatively, in the 5th LLR valueSequence pair answer
Bit sequence predeterminated position at least two 0 and at least one 1, with obtain the 6th LLR value sequence；Alternatively, the 5th
LLR valueThe corresponding bit sequence of sequence predeterminated position at least one 0 and at least two 1, to obtain
Six LLR valuesSequence；6th LLR value is exactly the symbol of first part after serial to parallel conversion processing in sending device A
Information dAWith the symbolic information d of first part after serial to parallel conversion processing in sending device BBBit exclusive or resultBy
LLR value after noisy communication channelSequence；For example, increasing by 2 ratios before every 2 bits in the 7th bit sequence
Spy, then demapping processing is exactly to delete the first two LLR value in the sequence of the 5th LLR value in the sequence of every 4 LLR values
Sequence；Demapping processing module is by the 5th LLR valueSequence be sent to parallel serial conversion module.
Finally, referring to FIG. 4, parallel serial conversion module receives the 6th LLR value that demapping processing module is sentSequence, and receive demodulating unit send the 4th LLR valueSequence, to the 6th LLR valueSequence and the 4th LLR valueSequence merge, to obtain the second LLR valueSequence.
Wherein, the ratio of the corresponding bit sequence of the sequence bit sequence corresponding with the sequence of the 4th LLR value of the 6th LLR value
Value is equal to above-mentioned segmentation ratio, and the segmentation ratio is obtained according to the modulation system.
Wherein, the sequence of second LLR value and the second bit sequence have the mapping relations, second bit sequence to include
Bit 0 or bit 1, the bit 0 in first bit sequence and the ratio shared by bit 1 are different from second bit sequence
In bit 0 and the ratio shared by bit 1, second bit sequence be to first bit sequence according to modulation system into
The bit sequence of row processing.
Step 304, the receiving terminal carries out channel decoding processing to the sequence of second LLR value, with described in obtaining extremely
The court verdict of the bit exclusive or of few two sequences.
Specifically, channel decoding unit receives the second LLR value that parallel serial conversion unit is sentSequence, it is right
Second LLR valueSequence carry out channel decoding processing, the bit exclusive or to obtain at least two sequences is sentenced
Certainly result
Embodiment
Referring to FIG. 5, the flow diagram of the embodiment of the transmission method of its sequence provided by the embodiment of the present invention,
Referring to FIG. 6, in the present embodiment, with based on bit XOR operation and the equally distributed bit sequence transmission technology of sending probability
It is illustrated for wireless communication system, which includes transmitting terminal and receiving terminal, wherein transmitting terminal includes two
Sending device, i.e. terminal A and terminal B, receiving terminal can be relay node；As shown in figure 5, this approach includes the following steps：
Step 501, terminal A and terminal B carries out channel coding processing to 6912 the first bit sequences of input, to obtain
Obtain 9216 the second bit sequences.
Specifically, by taking terminal A as an example, the channel encoding unit in terminal A receives the first bit sequence of input, to first
Bit sequence carries out channel coding processing, to obtain the second bit sequence, and to the interleave unit of sending device send this second
Bit sequence；Wherein, the LDPC code that the code check of channel encoding unit is 3/4, the bit in the first bit sequence of input are
6912, channel encoding unit obtain the second bit sequence in bit be 9216；The processing procedure phase of terminal B and terminal A
Together.
Step 502, processing is interleaved to 9216 the second bit sequences, to obtain 9216 third bit sequences
Row.
Specifically, by taking terminal A as an example, the interleave unit of terminal A obtains the second bit sequence from channel encoding unit, to
Two bit sequences are interleaved processing, and to obtain third bit sequence, third bit sequence is sent to mapping list by interleave unit
Member；Bit is 9216 in third bit sequence.
Step 503, mapping processing is carried out to 9216 third bit sequences, to obtain 12288 the 4th bit sequences
Row, the 4th bit sequence includes 6144 the 5th bit sequences and 6144 the 6th bit sequences.
Specifically, map unit further comprises serial to parallel conversion module, mapping block and interleaving block.First, it goes here and there and becomes
It changes the mold block and receives third bit sequence from interleave unit, processing is split to the third bit sequence, by third bit sequence
Arrange vAIt is divided into the 7th bit sequence and the 6th bit sequence, wherein the 7th bit sequence is first 3072 of third bit sequence
Bit sequence, the 6th bit sequence be third bit sequence rear 6144 bit sequences；Serial to parallel conversion module is by the 7th
Bit sequence is sent to mapping block, and the 6th bit sequence is transmitted directly to modulation unit.
Secondly, mapping block receive serial to parallel conversion module send the 7th bit sequence, to the 7th bit sequence into
Row mapping is handled, and obtains the 8th bit sequence；In the present embodiment, mapping block utilizes (2,4) mapping policy as shown in Table 1,
Mapping processing is carried out to 3072 the 7th bit sequences received, obtains 6144 the 8th bit sequences；
Table 1
| 7th bit sequence (set I) of input | 8th bit sequence (set O) of output |
| 00 | 0000 |
| 01 | 0001 |
| 10 | 0010 |
| 11 | 0011 |
As shown in table 1, map unit is inserted into two bits 0 in the foremost of the 7th bit sequence of input, obtains the 8th
Bit sequence so that in the 8th bit sequence, the probability of bit 0 is 12/16, and the probability of bit 1 is 4/16；With reference to step 103
In Linear Mapping rule, here meet the 7th bit sequence to the 8th bit sequence Linear Mapping.
Finally, interleaving block receives the 8th bit sequence that mapping block is sent, and is carried out to the 8th bit sequence
Interleaving treatment, obtains the 5th bit sequence, and the 5th bit sequence is sent to modulation unit by interleaving block.
Step 504, processing is modulated to 6144 the 5th bit sequences and 6144 the 6th bit sequences, will adjusted
The bit sequence obtained after system processing is sent to relay node by noisy communication channel.
Specifically, modulation unit receives 6144 the 5th bit sequences and 6144 the 6th bit sequences, and use
6144 the 5th bit sequences of modulation system pair of 4PAM and 6144 the 6th bit sequences are modulated；Wherein, the 5th
Bit sequence is used to represent first of constellation point in planisphere, and the 6th bit sequence is used to represent the of constellation point in planisphere
Two；As shown in Fig. 7 (a), the 5th bit sequence of terminal A and the 6th bit sequence are adjusted using the planisphere of 4PAM
It makes, in planisphere shown in Fig. 7 (a) shown in sending probability such as Fig. 8 (a) of constellation point；As shown in Fig. 7 (b), the star of 4PAM is utilized
Seat figure is modulated the 5th bit sequence of terminal B and the 6th bit sequence, constellation point in planisphere shown in Fig. 7 (b)
Shown in sending probability such as Fig. 8 (b)；The symbol for square being equal to the corresponding symbolic information of the numerical value of the numerical value of abscissa in Fig. 8 (a)
Number energy, therefore, closer to coordinate origin, numerical value is smaller, and symbol energy is lower；The ratio that modulation unit will obtain after modulation treatment
Special sequence is sent to relaying section by additive white Gaussian noise (Additive White Gaussian Noise, AWGN) channel
Point.
Here, due in transmitting terminal there are two sending device, if carried out using identical 4PAM planispheres
The modulation of the 5th bit sequence and the 6th bit sequence of terminal A and terminal B, the two-way symbol that terminal A and terminal B can be caused to send
In the planisphere that number information bit XOR operation obtains, some constellation points can represent at least two different symbolic information so that
Relay node can not carry out demodulation process and channel decoding processing；For example, in the planisphere obtained after superposition, constellation point may be same
Shi represents 00 and 01 two bit sequence；Therefore, in the present embodiment, the star of the planisphere of the 4PAM of terminal A and the 4PAM of terminal B
Seat figure is mutually orthogonal, such as the planisphere for the 4PAM that Fig. 7 (a) is terminal A, wherein constellation point -1 represents bit sequence 00, constellation point
1 represents bit sequence 01, and constellation point -3 represents bit sequence 10, and constellation point 3 represents bit sequence 11；If Fig. 7 (b) is terminal B
4PAM planisphere, wherein constellation point-i represents bit sequence 00, and constellation point i represents bit sequence 01, constellation point -3i generations
Table bit sequence 10, constellation point 3i represent bit sequence 11, in this way, the symbolic information (such as -1,1, -3 and 3) and terminal B of terminal A
Symbolic information (as-i, i, -3i and 3i) carry out bit XOR operation after, obtain constellation point shown in Fig. 7 (c), these constellations
The corresponding sending probability of point as shown in figure 9, as shown in figure 9, the sending probability close to the symbolic information of planisphere origin is bigger,
Realize that the lower constellation point of symbol energy can be sent out with higher sending probability.
Step 505, relay node receives the sequence that terminal A and terminal B is sent respectively, is demodulated to described two sequences
Processing, to obtain the sequence of the first LLR value.
Specifically, the receiving unit of relay node receives the sequence that terminal A and terminal B is sent respectively, terminal A, which is sent to, to make an uproar
The symbolic information b of Acoustic channelAIt indicates, symbolic information bABecome sequences y after the transmission of noisy communication channelA, similarly, terminal B hairs
It is sent to the symbolic information b of noisy communication channelBIt indicates, symbolic information bBBecome sequences y after the transmission of noisy communication channelB；Demodulation is single
The signal that member is received from noisy communication channel is expressed as r, wherein r=yA+yB+ n, n are the noise in noisy communication channel.
Demodulating unit utilizes bit exclusive or algorithm, carries out demodulation process at least one sequence received, obtains at least one
The sequence of the first log-likelihood ratio (Log Likelihood Ratio, LLR) value after the bit XOR operation of a sequence, this
The sequence of one LLR value includes the sequence of the sequence and the 4th LLR value of third LLR value；The sequence of third LLR value is the of terminal A
Five bit sequence sA1With the 5th bit sequence s of sending device BB1Bit exclusive or resultAfter noisy communication channel
LLR valueSequence, the sequence of the 4th LLR value is the 6th bit sequence s of sending device AA2With sending device B
The 6th bit sequence sB2Bit exclusive or resultLLR value after noisy communication channelSequence；
The sequence of the sequence of third LLR value and the 4th LLR value is sent to processing unit by demodulating unit.
Step 506, demapping processing is carried out to the sequence of first LLR value, to obtain the sequence of the second LLR value.
Specifically, de-interleaving block receives third LLR valueSequence, the sequence of third LLR value is carried out
Deinterleaving is handled, to obtain the 5th LLR valueSequence.
De-mapping module receives the 5th LLR value that de-interleaving block is sentSequence, to the 5th LLR valueSequence carry out demapping processing, that is, execute mapping processing inversely processing, delete the 5th LLR valueSequence in every four LLR values sequence the first two bit 0, to obtain the 6th LLR value's
Sequence；Demapping processing module is by the 6th LLR valueSequence be sent to parallel serial conversion module.
Referring to FIG. 4, parallel serial conversion module receives the 6th LLR value that demapping processing module is sentSequence
Row, and receive the 4th LLR value that demodulating unit is sentSequence, to the 6th LLR valueSequence
Row and the 4th LLR valueSequence merge, to obtain the second LLR valueSequence.
Step 507, channel decoding processing is carried out to the sequence of second LLR value, to obtain at least two sequence
Bit exclusive or court verdict.
Specifically, channel decoding unit receives the second LLR value that parallel serial conversion unit is sentSequence, it is right
Second LLR valueSequence carry out channel decoding processing, outputAs terminal A and terminal B are respectively sent
6912 the first original bit sequences bit exclusive or court verdict；The court verdict with terminal A and terminal B respectively
The bit exclusive or result of 6912 bit sequences sent is compared, and can obtain the error performance of wireless communication system.
In technical scheme of the present invention, transmitting terminal carries out mapping processing to bit sequence so that is accorded in planisphere when modulation
Number lower constellation point of energy can be sent to noisy communication channel with higher sending probability, realize symbolic information in information theory
Sending probability Gaussian distributed, the lower symbolic information of energy are sent out with higher sending probability, the higher symbol letter of energy
Breath is sent out with lower sending probability, and the channel capacity of system can reach maximum, improve the availability of frequency spectrum of system so that
Error performance under same bits signal-to-noise ratio, which has, significantly to be promoted.As shown in Figure 10, solid line indicate based on bit XOR operation and
Bit error rate when the equally distributed bit sequence transmission technology of sending probability, in the schematic diagram of the sending probability of constellation point, horizontal seat
It is designated as bit signal-to-noise ratioIf abscissa is converted to symbol signal-to-noise ratioIt then needs accordingly to be adjusted schematic diagram
It is whole, i.e., the line segment in schematic diagram is translated, translation needs to meetBeing converted to decibel is：Wherein, R is the equivalent code check in wireless communication system.In the present embodiment, equivalent code checkAnd in the prior art, it is based on bit XOR operation and transmission
In the equally distributed bit sequence transmission technology of probability, equivalent code check isAccidentally
Code check is 10-4When,Dotted line is based on the bit sequence based on mapping processing provided in the embodiment of the present invention
Bit error rate when transmission technology, the bit error rate 10-4When,Compared with prior art, bit signal-to-noise ratio improves
0.71dB, therefore the error performance that the technical solution of the embodiment of the present invention can be optimal.
The embodiment of the present invention, which further provides, realizes the device embodiment of each step and method in above method embodiment.
1 is please referred to Fig.1, the functional block diagram of the processing equipment one of the sequence provided by the embodiment of the present invention, the sequence
The processing equipment of row is transmitting terminal, such as terminal or base station；As shown, the equipment includes：
Channel encoding unit 110, for carrying out channel coding processing to the first bit sequence, to obtain the second bit sequence
Row；
Interleave unit 111, for being interleaved processing to second bit sequence, to obtain third bit sequence, institute
It includes bit 0 or bit 1 to state third bit sequence；
Processing unit 112, is used for：
According to modulation system, segmentation ratio is obtained；
According to the segmentation ratio, the third bit sequence is handled, to obtain the 4th bit sequence, described
Four bit sequences include bit 0 or bit 1, and the bit 0 in the 4th bit sequence and the ratio shared by bit 1 are different from institute
State the bit 0 in third bit sequence and the ratio shared by bit 1；
Modulation unit 113, for being modulated processing to the 4th bit sequence；
Transmission unit 114, for sending the bit sequence obtained after the modulation treatment to receiving terminal.
Optionally, the 4th bit sequence includes the 5th bit sequence and the 6th bit sequence, the processing unit
112, it is specifically used for：According to modulation system, segmentation ratio is obtained；According to the segmentation ratio, to the third bit sequence into
Row dividing processing, to obtain the 6th bit sequence and the 7th bit sequence；7th bit sequence is handled, to obtain
8th bit sequence；Processing is interleaved to the 8th bit sequence, to obtain the 5th bit sequence.
Optionally, the ratio of the length of the length and the 6th bit sequence of the 7th bit sequence is equal to described point
Cut ratio.
Optionally, the processing unit 112, is specifically used for：
According to modulation system, segmentation ratio is obtained；
According to the segmentation ratio, processing is split to the third bit sequence, with obtain the 6th bit sequence and
7th bit sequence；
Predeterminated position is inserted at least one bit 0 in the 7th bit sequence, to obtain the 8th bit sequence；
Alternatively, predeterminated position is inserted at least one bit 1 in the 7th bit sequence, to obtain the 8th bit sequence；
Processing is interleaved to the 8th bit sequence, to obtain the 5th bit sequence.
Optionally, the processing unit 112, is specifically used for：
According to modulation system, segmentation ratio is obtained；
According to the segmentation ratio, processing is split to the third bit sequence, with obtain the 6th bit sequence and
7th bit sequence；
If predeterminated position is inserted at least one bit 0 in the 7th bit sequence, in the 7th bit sequence
Predeterminated position is inserted at least two bits 1, to obtain the 8th bit sequence, if alternatively, in the 7th bit sequence
Predeterminated position is inserted at least one bit 1, and predeterminated position is inserted at least two bits 0 in the 7th bit sequence, to obtain
Obtain the 8th bit sequence；
Processing is interleaved to the 8th bit sequence, to obtain the 5th bit sequence.
In the embodiment of the present invention, bit sequence is handled so that bit in the bit sequence obtained after processing
Number has differences, thus the sending probability and symbol energy of the symbolic information obtained after being modulated to such bit sequence
Gaussian distributed, therefore the channel capacity of wireless communication system can be improved.
2 are please referred to Fig.1, the structural schematic diagram of the processing equipment one of the sequence provided by the embodiment of the present invention is corresponding
In Figure 11, as shown, the equipment includes：
Memory 121, for store include program routine information；
Processor 122 couples, the execution for controlling described program routine with memory 121, transmitter 123, specific to wrap
It includes：Channel coding processing is carried out to the first bit sequence, to obtain the second bit sequence；Second bit sequence is handed over
Processing is knitted, to obtain third bit sequence, the third bit sequence includes bit 0 or bit 1；According to modulation system, obtain
Divide ratio；According to the segmentation ratio, the third bit sequence is handled, it is described to obtain the 4th bit sequence
4th bit sequence includes bit 0 or bit 1, and the bit 0 in the 4th bit sequence and the ratio shared by bit 1 are different from
The ratio shared by bit 0 and bit 1 in the third bit sequence；Processing is modulated to the 4th bit sequence；
Transmitter 123, for sending the bit sequence obtained after the modulation treatment to receiving terminal.
The processor 122 correspond to Figure 11 in channel encoding unit 110, interleave unit 111, first processing units 112,
Modulation unit 113, transmitter 123 correspond to transmission unit 114 in Figure 11.
Optionally, the 4th bit sequence include the 5th bit sequence and the 6th bit sequence, the processor 122,
It is specifically used for：
According to modulation system, segmentation ratio is obtained；
According to the segmentation ratio, processing is split to the third bit sequence, with obtain the 6th bit sequence and
7th bit sequence；
7th bit sequence is handled, to obtain the 8th bit sequence；
Processing is interleaved to the 8th bit sequence, to obtain the 5th bit sequence.
Optionally, the ratio of the length of the length and the 6th bit sequence of the 7th bit sequence is equal to described point
Cut ratio.
Optionally, the processor 122, is specifically used for：
According to modulation system, segmentation ratio is obtained；
According to the segmentation ratio, processing is split to the third bit sequence, with obtain the 6th bit sequence and
7th bit sequence；
Predeterminated position is inserted at least one bit 0 in the 7th bit sequence, to obtain the 8th bit sequence；
Alternatively, predeterminated position is inserted at least one bit 1 in the 7th bit sequence, to obtain the 8th bit sequence；
Processing is interleaved to the 8th bit sequence, to obtain the 5th bit sequence.
Optionally, the processor 122, is specifically used for：
According to modulation system, segmentation ratio is obtained；
According to the segmentation ratio, processing is split to the third bit sequence, with obtain the 6th bit sequence and
7th bit sequence；
If predeterminated position is inserted at least one bit 0 in the 7th bit sequence, in the 7th bit sequence
Predeterminated position is inserted at least two bits 1, to obtain the 8th bit sequence, if alternatively, in the 7th bit sequence
Predeterminated position is inserted at least one bit 1, and predeterminated position is inserted at least two bits 0 in the 7th bit sequence, to obtain
Obtain the 8th bit sequence；
Processing is interleaved to the 8th bit sequence, to obtain the 5th bit sequence.
In the embodiment of the present invention, bit sequence is handled so that bit in the bit sequence obtained after processing
Number has differences, thus the sending probability and symbol energy of the symbolic information obtained after being modulated to such bit sequence
Gaussian distributed, therefore the channel capacity of wireless communication system can be improved.
3 are please referred to Fig.1, the functional block diagram of the processing equipment two of the sequence provided by the embodiment of the present invention, the sequence
The processing equipment of row is receiving terminal, such as relay node；As shown, the equipment includes：
Receiving unit 130, the sequence for receiving the transmission of at least two transmitting terminals；
Demodulating unit 131, for carrying out demodulation process to the sequence, to obtain the sequence of the first log-likelihood ratio LLR value
Row, it includes bit 0 or ratio that sequence and the first bit sequence of first LLR value, which have mapping relations, first bit sequence,
Spy 1；
Processing unit 132 is handled for the sequence to first LLR value, to obtain the sequence of the second LLR value,
The sequence of second LLR value and the second bit sequence have a mapping relations, and second bit sequence includes bit 0 or bit 1,
The ratio shared by bit 0 and bit 1 in first bit sequence is different from the bit 0 in second bit sequence and ratio
Ratio shared by spy 1, second bit sequence are the bit handled according to modulation system first bit sequence
Sequence；
Channel decoding unit 133 carries out channel decoding processing, described in acquisition for the sequence to second LLR value
The court verdict of the bit exclusive or of at least two sequences.
Optionally, the sequence of first LLR value includes the sequence of the sequence and the 4th LLR value of third LLR value, the place
Reason unit 132 is specifically used for：Processing is deinterleaved to the sequence of the third LLR value, to obtain the sequence of the 5th LLR value；
The sequence of 5th LLR value is handled, to obtain the sequence of the 6th LLR value；Merge the 6th LLR value sequence and
The sequence of 4th LLR value, to obtain the sequence of the second LLR value.
Optionally, the corresponding bit sequence of sequence of the 6th LLR value ratio corresponding with the sequence of the 4th LLR value
The ratio of special sequence is equal to segmentation ratio, and the segmentation ratio is obtained according to the modulation system.
Optionally, the processing unit 132, is specifically used for：
Processing is deinterleaved to the sequence of the third LLR value, to obtain the sequence of the 5th LLR value；
At least one bit 1 is deleted in the predeterminated position of the corresponding bit sequence of sequence of the 5th LLR value, to obtain
The sequence of 6th LLR value, alternatively, the corresponding bit sequence of sequence of the 5th LLR value predeterminated position delete to
A few bit 0, to obtain the sequence of the 6th LLR value；
The sequence for merging the sequence and the 4th LLR value of the 6th LLR value, to obtain the sequence of the second LLR value.
Optionally, the processing unit 132, is specifically used for：
Processing is deinterleaved to the sequence of the third LLR value, to obtain the sequence of the 5th LLR value；
If at least one bit 1 is deleted in the predeterminated position of the corresponding bit sequence of sequence of the 5th LLR value, in institute
The predeterminated position for stating the corresponding bit sequence of sequence of the 5th LLR value deletes at least two bits 0 to obtain the 6th LLR value
Sequence, if alternatively, the predeterminated position in the corresponding bit sequence of sequence of the 5th LLR value deletes at least one bit 0,
At least two bits 1 are deleted to obtain the described 6th in the predeterminated position of the corresponding bit sequence of sequence of the 5th LLR value
The sequence of LLR value；
The sequence for merging the sequence and the 4th LLR value of the 6th LLR value, to obtain the sequence of the second LLR value.
In the embodiment of the present invention, bit sequence is handled in transmitting terminal so that in the bit sequence obtained after processing
The number of bit has differences, the sending probability of the symbolic information to obtain after being modulated to such bit sequence with
Symbol energy Gaussian distributed, therefore the channel capacity of wireless communication system can be improved；Above-mentioned receiving terminal executes transmitting terminal
The inversely processing of processing eliminates the difference of bit in sequence, to restore bit sequence, transmitting terminal can be coordinated to realize and improved
The channel capacity of wireless communication system.
4 are please referred to Fig.1, the structural schematic diagram of the processing equipment two of the sequence provided by the embodiment of the present invention is corresponding
In Figure 13, as shown, the equipment includes：
Receiver 141, the sequence for receiving the transmission of at least two transmitting terminals；
Memory 142, for store include program routine information；
Processor 143 is coupled with memory 142, receiver 141, for carrying out demodulation process to the sequence, to obtain
The sequence of first log-likelihood ratio LLR value, the sequence of first LLR value and the first bit sequence have a mapping relations, and described the
One bit sequence includes bit 0 or bit 1；The sequence of first LLR value is handled, to obtain the sequence of the second LLR value
Row, it includes bit 0 or ratio that sequence and the second bit sequence of second LLR value, which have mapping relations, second bit sequence,
Spy 1, the bit 0 in first bit sequence and the ratio shared by bit 1 are different from the bit 0 in second bit sequence
With the ratio shared by bit 1, second bit sequence handles first bit sequence according to modulation system
Bit sequence；Channel decoding processing is carried out to the sequence of second LLR value, it is special with the ratio for obtaining at least two sequence
Or court verdict.
Receiver 141 corresponds to the receiving unit 130 of Figure 13, and processor 143 corresponds to the demodulating unit 131 of Figure 13, place
Manage unit 132 and channel decoding unit 133.
Optionally, the sequence of first LLR value includes the sequence of the sequence and the 4th LLR value of third LLR value, the place
Reason device 143 is specifically used for：Processing is deinterleaved to the sequence of the third LLR value, to obtain the sequence of the 5th LLR value；It is right
The sequence of 5th LLR value is handled, to obtain the sequence of the 6th LLR value；Merge sequence and the institute of the 6th LLR value
The sequence for stating the 4th LLR value, to obtain the sequence of the second LLR value.
Optionally, the corresponding bit sequence of sequence of the 6th LLR value ratio corresponding with the sequence of the 4th LLR value
The ratio of special sequence is equal to segmentation ratio, and the segmentation ratio is obtained according to the modulation system.
Optionally, the processor 143, is specifically used for：
Processing is deinterleaved to the sequence of the third LLR value, to obtain the sequence of the 5th LLR value；
At least one bit 1 is deleted in the predeterminated position of the corresponding bit sequence of sequence of the 5th LLR value, to obtain
The sequence of 6th LLR value, alternatively, the corresponding bit sequence of sequence of the 5th LLR value predeterminated position delete to
A few bit 0, to obtain the sequence of the 6th LLR value；
The sequence for merging the sequence and the 4th LLR value of the 6th LLR value, to obtain the sequence of the second LLR value.
Optionally, the processor 143, is specifically used for：
Processing is deinterleaved to the sequence of the third LLR value, to obtain the sequence of the 5th LLR value；
If at least one bit 1 is deleted in the predeterminated position of the corresponding bit sequence of sequence of the 5th LLR value, in institute
The predeterminated position for stating the corresponding bit sequence of sequence of the 5th LLR value deletes at least two bits 0 to obtain the 6th LLR value
Sequence, if alternatively, the predeterminated position in the corresponding bit sequence of sequence of the 5th LLR value deletes at least one bit 0,
At least two bits 1 are deleted to obtain the described 6th in the predeterminated position of the corresponding bit sequence of sequence of the 5th LLR value
The sequence of LLR value；
The sequence for merging the sequence and the 4th LLR value of the 6th LLR value, to obtain the sequence of the second LLR value.
In the embodiment of the present invention, bit sequence is handled in transmitting terminal so that in the bit sequence obtained after processing
The number of bit has differences, the sending probability of the symbolic information to obtain after being modulated to such bit sequence with
Symbol energy Gaussian distributed, therefore the channel capacity of wireless communication system can be improved；Above-mentioned receiving terminal executes transmitting terminal
The inversely processing of processing eliminates the difference of bit in sequence, to restore bit sequence, transmitting terminal can be coordinated to realize and improved
The channel capacity of wireless communication system.
The above-mentioned technical proposal of the embodiment of the present invention has the advantages that：
When the sending probability Gaussian distributed of symbolic information, i.e., by the lower symbolic information of energy with higher transmission
Probability is sent, when the higher symbolic information of energy is sent with lower sending probability, the channel of wireless communication system
Capacity can reach maximum value, therefore, in the embodiment of the present invention, handle bit sequence so that the bit obtained after processing
The number of bit has differences in sequence, thus the transmission of the symbolic information obtained after being modulated to such bit sequence
Probability and symbol energy Gaussian distributed, therefore the channel capacity of wireless communication system can be improved.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
With within principle, any modification, equivalent substitution, improvement and etc. done should be included within the scope of protection of the invention god.
Claims (20)
1. a kind of processing method of sequence, which is characterized in that the method includes：
The first bit sequence of transmitting terminal pair carries out channel coding processing, to obtain the second bit sequence；
The transmitting terminal is interleaved processing to second bit sequence, to obtain third bit sequence, the third bit
Sequence includes bit 0 or bit 1, and in the third bit sequence bit 0 quantity it is identical with the quantity of bit 1；
The transmitting terminal obtains segmentation ratio according to modulation system；
The transmitting terminal is handled the third bit sequence according to the segmentation ratio, to obtain the 4th bit sequence,
4th bit sequence includes bit 0 or bit 1, and in the 4th bit sequence quantity and bit 1 of bit 0 quantity
It is different；
The transmitting terminal is modulated processing to the 4th bit sequence；
The transmitting terminal sends the bit sequence obtained after the modulation treatment to receiving terminal.
2. according to the method described in claim 1, it is characterized in that, the 4th bit sequence includes the 5th bit sequence and the
Six bit sequences, the transmitting terminal are handled the third bit sequence according to the segmentation ratio, to obtain the 4th ratio
Special sequence, specifically includes：
According to the segmentation ratio, processing is split to the third bit sequence, to obtain the 6th bit sequence and the 7th
Bit sequence；
7th bit sequence is handled, to obtain the 8th bit sequence；
Processing is interleaved to the 8th bit sequence, to obtain the 5th bit sequence.
3. according to the method described in claim 2, it is characterized in that：
The length of 7th bit sequence and the ratio of the length of the 6th bit sequence are equal to the segmentation ratio.
4. according to the method in claim 2 or 3, which is characterized in that it is described that 7th bit sequence is handled, with
The 8th bit sequence is obtained, is specifically included：
Predeterminated position is inserted at least one bit 0 in the 7th bit sequence, to obtain the 8th bit sequence；Or
Person,
Predeterminated position is inserted at least one bit 1 in the 7th bit sequence, to obtain the 8th bit sequence.
5. according to the method described in claim 4, it is characterized in that, the method further includes：
If predeterminated position is inserted at least one bit 0 in the 7th bit sequence, preset in the 7th bit sequence
At least two bits 1 are inserted into position；Alternatively,
If predeterminated position is inserted at least one bit 1 in the 7th bit sequence, preset in the 7th bit sequence
At least two bits 0 are inserted into position.
6. a kind of processing method of sequence, which is characterized in that the method includes：
Receiving terminal receives the sequence that at least two transmitting terminals are sent；
The receiving terminal carries out demodulation process to the sequence, to obtain the sequence of the first LLR value, the sequence of first LLR value
Row have a mapping relations with the first bit sequence, and first bit sequence includes bit 0 or bit 1, and the first bit sequence
The quantity of bit 0 is different with the quantity of bit 1 in row；
The receiving terminal handles the sequence of first LLR value, to obtain the sequence of the second LLR value, the 2nd LLR
The sequence of value and the second bit sequence have a mapping relations, and second bit sequence includes bit 0 or bit 1, and described second
The quantity of bit 0 is identical with the quantity of bit 1 in bit sequence, second bit sequence be to first bit sequence according to
The bit sequence handled according to modulation system；
The receiving terminal carries out channel decoding processing to the sequence of second LLR value, to obtain at least two sequence
The court verdict of bit exclusive or.
7. according to the method described in claim 6, it is characterized in that, the sequence of first LLR value includes the sequence of third LLR value
The sequence of row and the 4th LLR value, the receiving terminal handle the sequence of first LLR value, to obtain the second LLR value
Sequence specifically includes：
Processing is deinterleaved to the sequence of the third LLR value, to obtain the sequence of the 5th LLR value；
The sequence of 5th LLR value is handled, to obtain the sequence of the 6th LLR value；
The sequence for merging the sequence and the 4th LLR value of the 6th LLR value, to obtain the sequence of the second LLR value.
8. according to the method described in claim 7, it is characterized in that：
The ratio of the corresponding bit sequence of the sequence bit sequence corresponding with the sequence of the 4th LLR value of 6th LLR value
Value is equal to segmentation ratio, and the segmentation ratio is obtained according to the modulation system.
9. according to the method described in claim 8, it is characterized in that, the sequence to the 5th LLR value is handled, with
The sequence of the 6th LLR value is obtained, including：
At least one 1 is deleted in the predeterminated position of the corresponding bit sequence of sequence of the 5th LLR value, to obtain the described 6th
The sequence of LLR value；Alternatively,
At least one 0 is deleted in the predeterminated position of the corresponding bit sequence of sequence of the 5th LLR value, to obtain the described 6th
The sequence of LLR value.
10. according to the method described in claim 9, it is characterized in that, the method further includes：
If the predeterminated position in the corresponding bit sequence of sequence of the 5th LLR value deletes at least one bit 1, described the
The predeterminated position of the corresponding bit sequence of sequence of five LLR values deletes at least two bits 0；Alternatively,
If the predeterminated position in the corresponding bit sequence of sequence of the 5th LLR value deletes at least one bit 0, described the
The predeterminated position of the corresponding bit sequence of sequence of five LLR values deletes at least two bits 1.
11. a kind of processing equipment of sequence, which is characterized in that the equipment includes：
Channel encoding unit, for carrying out channel coding processing to the first bit sequence, to obtain the second bit sequence；
Interleave unit, for being interleaved processing to second bit sequence, to obtain third bit sequence, the third ratio
Special sequence includes bit 0 or bit 1, and in the third bit sequence bit 0 quantity it is identical with the quantity of bit 1；
Processing unit is used for：
According to modulation system, segmentation ratio is obtained；
According to the segmentation ratio, the third bit sequence is handled, to obtain the 4th bit sequence, the 4th ratio
Special sequence includes bit 0 or bit 1, and the bit 0 in the 4th bit sequence and the ratio shared by bit 1 are different from described the
The ratio shared by bit 0 and bit 1 in bit sequence, and the quantity of bit 0 and bit 1 in the 4th bit sequence
Quantity is different；
Modulation unit, for being modulated processing to the 4th bit sequence；
Transmission unit, for sending the bit sequence obtained after the modulation treatment to receiving terminal.
12. equipment according to claim 11, which is characterized in that the 4th bit sequence include the 5th bit sequence and
6th bit sequence, the processing unit, is specifically used for：
According to modulation system, segmentation ratio is obtained；
According to the segmentation ratio, processing is split to the third bit sequence, to obtain the 6th bit sequence and the 7th
Bit sequence；
7th bit sequence is handled, to obtain the 8th bit sequence；
Processing is interleaved to the 8th bit sequence, to obtain the 5th bit sequence.
13. equipment according to claim 12, which is characterized in that the length of the 7th bit sequence compares with the described 6th
The ratio of the length of special sequence is equal to the segmentation ratio.
14. equipment according to claim 12 or 13, which is characterized in that the processing unit is specifically used for：
According to modulation system, segmentation ratio is obtained；
According to the segmentation ratio, processing is split to the third bit sequence, to obtain the 6th bit sequence and the 7th
Bit sequence；
Predeterminated position is inserted at least one bit 0 in the 7th bit sequence, to obtain the 8th bit sequence；Or
Person, predeterminated position is inserted at least one bit 1 in the 7th bit sequence, to obtain the 8th bit sequence；
Processing is interleaved to the 8th bit sequence, to obtain the 5th bit sequence.
15. equipment according to claim 14, which is characterized in that the processing unit is specifically used for：
According to modulation system, segmentation ratio is obtained；
According to the segmentation ratio, processing is split to the third bit sequence, to obtain the 6th bit sequence and the 7th
Bit sequence；
If predeterminated position is inserted at least one bit 0 in the 7th bit sequence, preset in the 7th bit sequence
At least two bits 1 are inserted into position, to obtain the 8th bit sequence, if alternatively, being preset in the 7th bit sequence
At least one bit 1 is inserted into position, and predeterminated position is inserted at least two bits 0 in the 7th bit sequence, to obtain
State the 8th bit sequence；
Processing is interleaved to the 8th bit sequence, to obtain the 5th bit sequence.
16. a kind of processing equipment of sequence, which is characterized in that the equipment includes：
Receiving unit, the sequence for receiving the transmission of at least two transmitting terminals；
Demodulating unit, for carrying out demodulation process to the sequence, to obtain the sequence of the first LLR value, first LLR value
Sequence and the first bit sequence have a mapping relations, and first bit sequence includes bit 0 or bit 1, and first bit
The quantity of bit 0 is different with the quantity of bit 1 in sequence；
Processing unit is handled for the sequence to first LLR value, with obtain the second LLR value sequence, described second
The sequence of LLR value and the second bit sequence have a mapping relations, and second bit sequence includes bit 0 or bit 1, and described the
The quantity of bit 0 is identical with the quantity of bit 1 in two bit sequences, and second bit sequence is to first bit sequence
The bit sequence handled according to modulation system；
Channel decoding unit carries out channel decoding processing, to obtain described at least two for the sequence to second LLR value
The court verdict of the bit exclusive or of sequence.
17. equipment according to claim 16, which is characterized in that the sequence of first LLR value includes third LLR value
The sequence of sequence and the 4th LLR value, the processing unit are specifically used for：
Processing is deinterleaved to the sequence of the third LLR value, to obtain the sequence of the 5th LLR value；
The sequence of 5th LLR value is handled, to obtain the sequence of the 6th LLR value；
The sequence for merging the sequence and the 4th LLR value of the 6th LLR value, to obtain the sequence of the second LLR value.
18. equipment according to claim 17, it is characterised in that：
The ratio of the corresponding bit sequence of the sequence bit sequence corresponding with the sequence of the 4th LLR value of 6th LLR value
Value is equal to segmentation ratio, and the segmentation ratio is obtained according to the modulation system.
19. equipment according to claim 18, which is characterized in that the processing unit is specifically used for：
Processing is deinterleaved to the sequence of the third LLR value, to obtain the sequence of the 5th LLR value；
At least one bit 1 is deleted in the predeterminated position of the corresponding bit sequence of sequence of the 5th LLR value, described in acquisition
The sequence of 6th LLR value, alternatively, the predeterminated position in the corresponding bit sequence of sequence of the 5th LLR value deletes at least one
A bit 0, to obtain the sequence of the 6th LLR value；
The sequence for merging the sequence and the 4th LLR value of the 6th LLR value, to obtain the sequence of the second LLR value.
20. equipment according to claim 19, which is characterized in that the processing unit is specifically used for：
Processing is deinterleaved to the sequence of the third LLR value, to obtain the sequence of the 5th LLR value；
If the predeterminated position in the corresponding bit sequence of sequence of the 5th LLR value deletes at least one bit 1, described the
The predeterminated position of the corresponding bit sequence of sequence of five LLR values deletes at least two bits 0 to obtain the sequence of the 6th LLR value
Row, if alternatively, the predeterminated position in the corresponding bit sequence of sequence of the 5th LLR value deletes at least one bit 0, in institute
The predeterminated position for stating the corresponding bit sequence of sequence of the 5th LLR value deletes at least two bits 1 to obtain the 6th LLR value
Sequence；
The sequence for merging the sequence and the 4th LLR value of the 6th LLR value, to obtain the sequence of the second LLR value.
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| CN1575549A (en) * | 2001-08-23 | 2005-02-02 | 北方电讯网络有限公司 | System and method performing quadrature amplitude modulation by combining co-sets and strongly coded co-set identifiers |
| CN101883063A (en) * | 2009-05-08 | 2010-11-10 | 中兴通讯股份有限公司 | Iterative detecting method and device |
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| CN1575549A (en) * | 2001-08-23 | 2005-02-02 | 北方电讯网络有限公司 | System and method performing quadrature amplitude modulation by combining co-sets and strongly coded co-set identifiers |
| CN101883063A (en) * | 2009-05-08 | 2010-11-10 | 中兴通讯股份有限公司 | Iterative detecting method and device |
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