CN104657754B - RFID reader BPSK receivers - Google Patents

Abstract

The invention discloses a kind of RFID reader BPSK receivers, including：I, Q high frequency carrier demodulator, I, Q clock circuits, I, Q variable gain bandpass filters, I, the roadbed band signals of Q bis- selection control circuit, two bit A/D C BPSK demodulator circuits, decoder and agc circuit.Interference of the variable gain band pass filter circuit in addition to it can filter out signal bandwidth and the spuious harmonic for coming from chip itself, also with variable gain amplifier, using the teaching of the invention it is possible to provide certain dynamic range；Two bit A/D C demodulator circuits will carry out BPSK correlation demodulations to I, the roadbed band signals of Q bis-；AGC controls the gain of variable gain filter by handling the range signal exported after demodulation, realizes the controllable of link.Decoder is decoded to the data flow after demodulation and used to rear class digital circuit.The method can significantly improve demodulation performance, increase signal to noise ratio.Present invention can apply to the circuit realiration of circuit board components level and chip-scale.

Description

RFID reader BPSK receivers

Technical field

It is more particularly to a kind of to use two bit A/D C (Analog-digital Converters the present invention relates to RFID (radio frequency identification) field Device) demodulation 13.56MHz RFID readers BPSK (two-phase PSK) receiver.

Background technology

RFID technique is the non-contact technology that a kind of use electromagnetic field couples come automatic identification people or things.It with tradition Contact IC (integrated circuit) card compare, it is not necessary to contact contact, it is relatively reliable.RFID system is typically made up of two parts, Read write line and label.In RFID system, the energy needed for electric data carrier (RFID tag) work is non-contacting from read write line Transmit to obtain, and read write line obtains useful and reliable information from the antenna transmission signal of RFID tag.Use RFID Technology can allow the manufacturer of product and the supplier of commodity preferably to classify or track their commodity or goods.RFID The other important application of technology include financial payment, public transport, gate inhibition safety etc. field.

The general 13.56MHz RFID standards that are operated in are mainly ISO-14443 standards, ISO-14443 standards in the world Including two kinds of Type A (type A) and Type B (type B).Up-high speed data in Type B standards from label to read write line Transmission employs the mode of BPSK modulating subcarriers.This receiver for being accomplished by read write line is demodulated using corresponding BPSK subcarriers System.

One traditional BPSK read write lines receiver circuit is as shown in figure 1, adjudicated using a bit sample 13.56MHz RFID reader BPSK receiver architectures.It is by antenna and its match circuit, and high frequency carrier demodulator is (passive mixed Frequency device), IQ clock circuits, bandpass filter and a bit sample decision device, decoder is constituted.One bit sample decision device is Bpsk signal is demodulated into the Key Circuit of NRZ (nonreturn to zero code).Due to its output only with a data, so it is only Corresponding phase place change information can be obtained after the decoding, and can not obtain accurate amplitude information, and it is outer that this is highly susceptible to it Portion or the interference of noise level caused by itself, so as to cause mistaken verdict, reduce the sensitivity of receiver circuit.While because Gain for such receiver circuit is fixed, untunable, the simulation base so obtained after high frequency carrier demodulator circuit is demodulated When band signal amplitude is more than the maximum input range of amplifier, late-class circuit meeting saturation, so as to cause whole receiver signal to noise ratio Decline, reduce the performance of read write line.

The content of the invention

The technical problem to be solved in the present invention is to provide a kind of RFID reader BPSK receivers, solution tonality can be significantly improved Can, increase signal to noise ratio.

In order to solve the above technical problems, the RFID reader BPSK receivers of the present invention, including：

One I, Q clock circuit, for producing I, the road clocks of Q bis- are used as sampled clock signal, I, the road clock signal phases of Q bis- Difference is 90 °；

One I roads high frequency carrier demodulator, sampling holding is carried out to the RFID signal of input, by the high-frequency signal received with I roads clock signal is mutually mixed, and baseband signal is moved to I paths from 13.56MHz high frequencies, I roadbed band signals are exported；

One Q roads high frequency carrier demodulator circuit, the RFID signal to input carries out sampling holding, by the high-frequency signal received Mutually it is mixed with Q roads clock signal, baseband signal is moved to Q passages from 13.56MHz high frequencies, Q roadbed band signals are exported；Wherein, Also include：

One I passage variable gain bandpass filters, are connected with the I roads high frequency carrier demodulator, for filtering out I roadbeds High-frequency harmonic, out-of-band interference signal in band signal and the spuious harmonic for coming from chip itself, and put with variable Large gain；Export filtered I roadbeds band signal；

One Q passage variable gain bandpass filters, are connected with the Q roads high frequency carrier demodulator, for filtering out Q roadbeds High-frequency harmonic, out-of-band interference signal in band signal and the spuious harmonic for coming from chip itself, and put with variable Large gain, exports filtered Q roadbeds band signal；

The roadbed band signal of one I, Q bis- selection control circuit, can with the I passages variable gain bandpass filter and Q passages Variable-gain bandpass filter is connected, to the filtered I, and the roadbed band signals of Q bis- export baseband signal after being selected；

One or two bit A/D C BPSK demodulator circuits, with the I, the roadbed band signals of Q bis- selection control circuit is connected, to this The baseband signal of the roadbed band signal of I, Q bis- selection control circuit output carries out BPSK correlation demodulations；

One automatic gain control circuit, is connected with the two bit A/Ds C BPSK demodulator circuits, by defeated after demodulation The range signal gone out is handled, to control the I passages variable gain filter and Q passage variable gain bandpass filters Gain, makes I passages variable gain filter and Q passage variable gain filter output amplitudes be maintained at a steady state value；

One decoder, is connected with the two bit A/Ds C BPSK demodulator circuits, for being carried out to the data flow after demodulation Decoding.

The RFID reader BPSK receivers, including：

One clock circuit, for producing sampled clock signal；

One high frequency carrier demodulator, sampling holding is carried out to the RFID signal of input, by the high-frequency signal received and when Clock signal is mutually mixed, and baseband signal is moved to passage from 13.56MHz high frequencies, baseband signal is exported；Wherein, in addition to：

One variable gain bandpass filter, is connected with the high frequency carrier demodulator, for filtering out in baseband signal High-frequency harmonic, out-of-band interference signal and the spuious harmonic for coming from chip itself, and with variable gain amplifier；Output Filtered baseband signal；

One or two bit Analogue digital quantizer ADC BPSK demodulator circuits, are connected with the variable gain bandpass filter Connect, BPSK correlation demodulations are carried out to filtered baseband signal；

One automatic gain control circuit, is connected with the two bit A/Ds C BPSK demodulator circuits, by defeated after demodulation The range signal gone out is handled, and to control the gain of the variable gain filter, makes variable gain filter output amplitude It is maintained at a steady state value；

One decoder, is connected with the two bit A/Ds C BPSK demodulator circuits, for being carried out to the data flow after demodulation Decoding.

The present invention uses the BPSK demodulation architectures based on two bit A/D C, can significantly improve demodulation performance, increases signal to noise ratio, Improve the anti-noise ability of receiver；Automatic gain control circuit can control the gain of receiver link, can substantially reduce solution Adjust requirement of the device to dynamic range.

Present invention can apply to the circuit realiration of circuit board components level and chip-scale.

Brief description of the drawings

The present invention is further detailed explanation with embodiment below in conjunction with the accompanying drawings：

Fig. 1 is existing RFID reader BPSK receiver structure figures.

Fig. 2 is signal waveforms.

Fig. 3 is the schematic diagram of two bit A/D C BPSK demodulator circuits.

Fig. 4 is the example structure figure of RFID reader BPSK receivers one of the present invention.

Fig. 5 is I, the changeable RFID reader BPSK receiver structure figures of the paths of Q bis-.

Fig. 6 is the RFID reader BPSK receiver structure figures using passage all the way.

Fig. 7 is that the difference of two bit A/D C BPSK demodulator circuits realizes structure chart.

Fig. 8 is CMOS differential reference voltage circuit diagrams.

Fig. 9 is CMOS differential comparator circuit figures.

Embodiment

Referring to Fig. 4, shown in the figure is that a kind of 13.56MHz RFID readers BPSK based on two bit A/D C demodulation connects Frame structure is received, including：Antenna and its match circuit, I roads high frequency carrier demodulator circuit, Q roads high frequency carrier demodulator circuit, I, during Q Clock circuit, I passage variable gain bandpass filters, Q passage variable gain bandpass filters, I, the selection control of the roadbed band signals of Q bis- Circuit processed, two bit A/D C BPSK demodulator circuits, decoder and AGC (automatic growth control) circuit.

The antenna and its match circuit, for by the high-frequency signal received the lossless height for being delivered to rear class as far as possible Frequency carrier wave demodulation circuit.

A high frequency carrier demodulator circuit generally similar passive frequency mixer, the RFID signal to input carries out sampling guarantor Hold, to realize that signal is moved to base band from carrier wave.

Sampling clock is respectively by I, and the tunnels of Q bis- are constituted, and two road clock differences are 90 degree of phases.

The effect of variable gain bandpass filter is except filtering out high-frequency harmonic and other out-of-band interference signals and coming from Beyond the spuious harmonic of chip itself, also variable gain amplifier, using the teaching of the invention it is possible to provide certain dynamic range.

The roadbed band signal of I, Q bis- selection control circuit, to the I, output base band letter after the roadbed band signals of Q bis- are selected Number.

Two bit A/D C BPSK demodulator circuits will carry out BPSK demodulation to the baseband signal after amplification.

Data after last BPSK demodulation will enter decoding in decoder and obtain the useful information that rear class needs.It is same with this When, automatic gain control circuit will control variable gain bandpass filter gain, make its output amplitude be maintained at one it is constant Level.

The 13.56MHz RFID reader BPSK receiver structures and traditional base demodulated below to above-mentioned two bit A/Ds C The 13.56MHz RFID reader BPSK receiver structures adjudicated in a bit sample are made one and contrasted.

As shown in Fig. 2 when only use a bit PHI signals as BPSK digital demodulations output when, when PHI be high level When, it is judged as logical one；When PHI is low level, it is judged as logical zero, such as Fig. 2 b) [Fig. 2 b) deposited for small interference signal When analog input signal], Fig. 2 c) [Fig. 2 c) for based on Fig. 2 b) the data output that characterizes of the bit of use two] shown in.But The erroneous judgement of receiver shown in Fig. 1 is will result in than larger spuious or interference signal if there is one, 0 will be originally used for Logic level is judged as logical one, so as to cause error code, such as Fig. 2 d) [Fig. 2 d) it is that simulation in the presence of big interference signal is defeated Enter signal], Fig. 2 e) [Fig. 2 e) for based on Fig. 2 d) the data output that characterizes of the bit of use two] shown in.Fig. 2 a) it is data input.

If when input signal is VIN, exported using two signal PHI and AMP as two bits, signal PHI is used for sentencing Disconnected bpsk signal whether zero crossing (or VCOM points), signal AMP be used for judge output effective breadth.PHI=1, for difference For sub-signal, i.e., higher than VCOM voltages, (for differential signal, VCOM voltages are zero level to signal.Pair and single-ended signal, Then close to the half of supply voltage).Conversely, then PHI=0；AMP=1, for differential signal, i.e., signal amplitude is more than VREFP or VREFN (VREFP is equal to equal to VREFN in amplitude | VREF |, VREFP and VREFN opposite in phase)；Signal width Degree is if less than | VREF |, AMP=0.

So, signal output can be expressed as with the relation inputted：

| VIN |≤VREF AMP=0；|VIN|>VREF AMP=1,

VIN≤VCOM PHI=0；VIN>VCOM PHI=1.

When PHI signals from 0 to 1 or from 1 to 0 change imply that the symbol phase of bpsk signal there occurs 180 degree become Change.Whether the amplitude of AMP characterization signals reaches the requirement higher than VREF (differential signal is more than ± VREF).Deposited so working as When than larger interference signal, PHI and AMP output can be different.If PHI=AMP, output signal is PHI；Such as Fruit PHI ≠ AMP, output signal is AMP.The shadow that larger interference signal is demodulated to BPSK is thus overcome to a certain extent Ring.

On the basis of this theory, two bit A/D C BPSK demodulator circuits can be built, as shown in Figure 3.Bandpass filtering The output VIN of device is compared by comparator COMP1 with threshold value VREF level, exports AMP signals；VIN by comparator COMP2 with Threshold value VCOM level compares, and exports PHI signals, and AMP and PHI will give the processing of rear class decoder as two bits.Meanwhile, two ratios The synchronised clock output of rear class will be used as compared with the sampling clock of device.

The operation principle of agc circuit is as follows：

AGC function is that the bit AMP (representing amplitude) that can be exported according to ADC filters to adjust previous stage variable gain The gain of ripple device, makes it be operated in magnifying state and unsaturated.Because variable gain filter can use numerically controlled side Formula allocates gain, so the AGC that the present invention is used is realized by the way of digital algorithm.AGC input is AMP signals, when Clock signal, is output as long number control bit, the gain control word directly to adjust variable gain filter.AGC passes through system Count the ADC within a period of time and export AMP=1 number of times, so as to be simulated after obtaining the high frequency demodulation that variable gain filter is inputted The amplitude information of baseband signal.This amplitude information will (generally medium sized wave filter amplifies with a benchmark control word Digital control word representated by gain) compare, to control ADC input range.When the amplitude information is controlled more than benchmark Word, the gain of variable gain filter declines；Conversely, gain then increases so that its in the analog baseband signal certain When degree changes, the output amplitude of variable gain filter is held essentially constant.

Due to the distinctive low-voltage of CMOS technology itself, characteristic frequency is high, and low-power consumption, is easy to the excellent of integrated digital circuit Point, can realize a 13.56MHz RFID reader BPSK receiver collection demodulated based on two bit A/D C with CMOS technology Into circuit.

Receiver circuit shown in Fig. 4 has other two kinds of distressed structures, such as Fig. 5, shown in Fig. 6.

Although the receiver shown in Fig. 5 by high frequency carrier after demodulating, I is still generated, bis- passages of Q, only The data obtained according to rear class decoder are needed, judges and selects wherein signal optimal all the way, I roads or Q roads.So one Determine to save almost half power consumption in degree.

Receiver shown in Fig. 6 is only using the receiver structure of a channel signal.

Fig. 7 is the embodiment of two bit A/D C BPSK demodulator circuits of a difference form realized using CMOS technology. If signal is handled using difference form, can effectively improve common-mode rejection ratio, reduction circuit to coming from power supply, ground and The susceptibility of the interference signal of chip substrate.

The two bit A/D C BPSK demodulator circuits that difference form is realized are by three CMOS differential comparators COMP1~COMP3 Composition, above two CMOS differential comparators COMP1, COMP2 constitute AMP quantizers.A CMOS differential comparator below COMP3 is PHI quantizer.VINP, VINN are the difference output of variable gain bandpass filter, are separately input into three CMOS The input of differential comparator.CMOS differential comparators COMP1, COMP2 are defeated by the difference of variable gain bandpass filter respectively The positive phase and antiphase for going out signal VINP, VINN and differential reference voltage VREFP, VREFN are compared, and result of the comparison is defeated Enter to the OR gate OR of two inputs and obtain AMP signals.While the differential output signal VINP of variable gain bandpass filter, VINN is compared by CMOS differential comparators COMP3 and common mode electrical level and obtains PHI signals.The sampling of CMOS differential comparators The synchronised clock and AMP, PHI signal that clock also serves as rear class decoding circuit are exported together.Above three comparator should have one Fixed lag performance, it is to avoid back and forth bounce of the output level in zero crossing.

Fig. 8 describes a kind of CMOS reference voltage generating circuits of difference form, available for generation differential reference voltage VREFP,VREFN；By resistance R1~R4, nmos pass transistor M1~M3, PMOS transistor M4, M5 composition.Nmos pass transistor M1's Drain the input current IBIAS that is connected with the grid of grid, nmos pass transistor M2 grid and nmos pass transistor M3.NMOS crystal Pipe M1~M3 source ground GND.PMOS transistor M4 and PMOS transistor M5 source electrode connect supply voltage vdd terminal.PMOS is brilliant Body pipe M4 grid is connected with PMOS transistor M5 grid and drain electrode and nmos pass transistor M3 drain electrode.PMOS transistor M4 drain electrode is connected with resistance R3 one end, and is used as differential reference voltage VREFP output end.The resistance R3 other end with Resistance R4 one end, resistance R1 one end is connected with resistance R2 one end.Resistance R4 other end nmos pass transistor M2 leakage Pole is connected, and is used as differential reference voltage VREFN output end.Resistance R1 other end input difference voltage signal VINP, Resistance R2 other end input difference voltage signal VINN.

The differential voltage signal VINP and VINN of input has eliminated difference mode signal by two resistance R1, R2 summation actions, And generate a common-mode voltage, the amplitude of the common-mode voltage is approached | VINP+VINN | half.Nmos pass transistor M1~M3 and PMOS transistor M4, M5 constitutes two current mirrors, and (M1, M2 and M4 constitute a current mirror, and M1, M3 and M5 constitute another electricity Flow mirror), the electric current that mirror image obtains flowing through on resistance R3, R4 is carried out to input current IBIAS respectively.By adjusting input current IBIAS, thus it is possible to vary the differential reference voltage VREFP and VREFN of output.

Fig. 9 describes one embodiment of CMOS differential comparators, and ratio is done by differential input voltage and differential reference voltage Relatively obtain output level.The CMOS differential comparators by nmos pass transistor M6~M9, M12~M17, PMOS transistor M10, M11, M18~M21 compositions.

Nmos pass transistor M6~M9 and PMOS transistor M10, M11 constitute preamplifier.PMOS transistor M10 and PMOS transistor M11 source electrode is connected with supply voltage vdd terminal, PMOS transistor M10 grid and drain electrode and NMOS crystal Pipe M7 drain electrode and nmos pass transistor M9 drain electrode are connected.PMOS transistor M11 grid and drain electrode and nmos pass transistor M6 drain electrode and nmos pass transistor M8 drain electrode are connected.Nmos pass transistor M6~M9 source electrode is connected with one end of current source Connect, the other end ground connection GND of the current source.Nmos pass transistor M6 grid input difference voltage signal VINP, nmos pass transistor M9 grid inputs another differential voltage signal VINN.Nmos pass transistor M7 grid input difference reference voltage VREFP, NMOS Transistor M8 grid inputs another differential reference voltage VREFN.

Nmos pass transistor M12~M17 and PMOS transistor M18~M21 constitute rear class dynamic latch.PMOS transistor M18 source electrode and PMOS transistor M20 source electrode are connected with supply voltage vdd terminal；PMOS transistor M19 source electrode and PMOS Transistor M21 source electrode is connected with supply voltage vdd terminal.PMOS transistor M18 drain electrode and PMOS transistor M20 leakage Pole, nmos pass transistor M16 drain electrode, PMOS transistor M21 grid are connected with nmos pass transistor M17 grid, and it connects The node connect as differential output voltage VOUTN output end.PMOS transistor M19 drain electrode and PMOS transistor M21 leakage Pole, nmos pass transistor M17 drain electrode, PMOS transistor M20 grid are connected with nmos pass transistor M16 grid, and it connects The node connect as another differential output voltage VOUTP output end.PMOS transistor M18 grid and PMOS transistor M19 Grid input clock signal CLK.Nmos pass transistor M16 source electrode is connected with nmos pass transistor M14 drain electrode.NMOS crystal Pipe M14 grid is connected with PMOS transistor M10 drain electrode.Nmos pass transistor M14 source electrode and nmos pass transistor M12 leakage Pole is connected.Nmos pass transistor M12 source ground GND.Nmos pass transistor M12 grid input clock signal CLK.NMOS is brilliant Body pipe M17 source electrode is connected with nmos pass transistor M15 drain electrode.Nmos pass transistor M15 grid is with PMOS transistor M11's Drain electrode is connected.Nmos pass transistor M15 source electrode is connected with nmos pass transistor M13 drain electrode.Nmos pass transistor M13 source electrode It is grounded GND.Nmos pass transistor M13 grid input clock signal CLK.

This CMOS differential comparator circuits, due to the presence of preamplifier, had both reduced CMOS differential comparators Total input DC OFFSET (dc shift), (can recalcitrate) noise to the KICK-BACK that rear class comparator is produced again and carry out necessarily Isolation, with preferably comparing precision.

Although the present invention is illustrated using specific embodiment, the explanation to embodiment is not intended to limit the present invention's Scope.One skilled in the art is by reference to explanation of the invention, without departing substantially from the spirit and scope of the present invention In the case of, easily carry out various modifications or embodiment can be combined.

Claims (12)

1. a kind of RFID reader BPSK receivers, including：

One I, Q clock circuit, for producing I, the road clocks of Q bis- are as sampled clock signal, I, the road clock signal phase differences of Q bis- 90°；

One I roads high frequency carrier demodulator, the RFID signal to input carries out sampling holding, by the high-frequency signal received and I roads Clock signal is mutually mixed, and baseband signal is moved to I paths from 13.56MHz high frequencies, I roadbed band signals are exported；

One Q roads high frequency carrier demodulator, the RFID signal to input carries out sampling holding, by the high-frequency signal received and Q roads Clock signal is mutually mixed, and baseband signal is moved to Q passages from 13.56MHz high frequencies, Q roadbed band signals are exported；Its feature exists In, in addition to：

One I passage variable gain bandpass filters, are connected with the I roads high frequency carrier demodulator, are taken a message for filtering out I roadbeds High-frequency harmonic, out-of-band interference signal in number and the spuious harmonic for coming from chip itself, and increase with variable amplification Benefit；Export filtered I roadbeds band signal；

One Q passage variable gain bandpass filters, are connected with the Q roads high frequency carrier demodulator, are taken a message for filtering out Q roadbeds High-frequency harmonic, out-of-band interference signal in number and the spuious harmonic for coming from chip itself, and increase with variable amplification Benefit, exports filtered Q roadbeds band signal；

The roadbed band signal of one I, Q bis- selection control circuit, with the variable increasing of the I passages variable gain bandpass filter and Q passages Beneficial bandpass filter is connected, to the filtered I, and the roadbed band signals of Q bis- export baseband signal after being selected；

One or two bit Analogue digital quantizer ADC BPSK demodulator circuits, with the I, the roadbed band signals of Q bis- selection control circuit It is connected, to the I, the baseband signal of the roadbed band signals of Q bis- selection control circuit output carries out BPSK correlation demodulations；

One automatic gain control circuit, be connected with the two bit A/Ds C BPSK demodulator circuits, by being exported after demodulation Range signal is handled, to control the increasing of the I passages variable gain filter and Q passage variable gain bandpass filters Benefit, makes I passages variable gain filter and the output amplitude of Q passage variable gain bandpass filters be maintained at a steady state value；

One decoder, is connected with the two bit A/Ds C BPSK demodulator circuits, for being decoded to the data flow after demodulation.

2. receiver as claimed in claim 1, it is characterised in that：The roadbed band signal of the I, Q bis- selection control circuit is to institute State I, the roadbed band signals of Q bis- are added, the two bit A/Ds C BPSK demodulator circuits to the I, the roadbed band signals of Q bis- and carry out BPSK correlation demodulations.

3. receiver as claimed in claim 1, it is characterised in that：The roadbed band signal of the I, Q bis- selection control circuit selection I The optimal output all the way of signal in roadbed band signal and Q roadbed band signals, the two bit A/Ds C BPSK demodulator circuits are to I roadbeds Optimal carry out correlation demodulation all the way in band signal and Q roadbed band signals.

4. receiver as claimed in claim 1, it is characterised in that：The automatic gain control circuit is by counting at one section Interior ADC exports AMP=1 number of times, so that I is obtained, ABB after the high frequency demodulation of the road variable gain filter inputs of Q bis- The amplitude information of signal；The amplitude information is compared with a benchmark control word, to control ADC input range；When the width Spend information and be more than benchmark control word, then I, the gain of the road variable gain filters of Q bis- declines；Conversely, gain then increases, so that It is when the analog baseband signal is changing to a certain degree, I, and the output amplitude of the road variable gain filters of Q bis- is kept substantially It is constant.

5. receiver as claimed in claim 1, it is characterised in that：The two bit A/Ds C BPSK demodulator circuits are difference form Two bit A/D C BPSK demodulator circuits；It is made up of three CMOS differential comparators；Wherein,

First CMOS differential comparators and the 2nd CMOS differential comparators composition AMP quantizers；3rd CMOS differential comparators are PHI quantizer；The differential output signal of the tunnel variable gain bandpass filter of I, Q bis- is designated as VINP, VINN respectively, inputs respectively The input of three CMOS differential comparators；First CMOS differential comparators and the 2nd CMOS differential comparators are respectively by institute The positive phase and antiphase for stating differential output signal VINP, VINN and differential reference voltage VREFP, VREFN are compared, and are compared Result input to the OR gate of two inputs and obtain AMP signals；The differential output signal VINP simultaneously, VINN pass through the Three CMOS differential comparators are compared with common mode electrical level and obtain PHI signals；The sampling clock of CMOS differential comparators is as rear The synchronised clock and AMP, PHI signal of level decoding circuit are exported together；

Wherein, PHI signals be used for judge bpsk signal whether zero crossing, AMP signals be used for judge output effective breadth.

6. receiver as claimed in claim 5, it is characterised in that：Differential reference voltage VREFP, the VREFN, by difference shape The CMOS reference voltage generating circuits generation of formula；

The CMOS reference voltage generating circuits are by the resistance of first resistor~the 4th, the NMOS crystal of the first nmos pass transistor~the 3rd Pipe, the 4th PMOS transistor (M4), the 5th PMOS transistor (M5) composition；The drain electrode of first nmos pass transistor (M1) and grid, The grid of the grid of second nmos pass transistor (M2) and the 3rd nmos pass transistor (M3) is connected input current IBIAS；

The source ground of the nmos pass transistor (M1~M3) of first nmos pass transistor~the 3rd；

The source electrode of 4th PMOS transistor (M4) and the 5th PMOS transistor (M5) connects supply voltage vdd terminal；4th PMOS crystal The grid of (M4) is managed with the grid of the 5th PMOS transistor (M5) and drain electrode and the drain electrode of the 3rd nmos pass transistor (M3) to be connected Connect；The drain electrode of 4th PMOS transistor (M4) is connected with one end of 3rd resistor (R3), and is used as differential reference voltage VREFP Output end；One end, one end of first resistor (R1) and the second electricity of the other end of 3rd resistor (R3) and the 4th resistance (R4) One end of resistance (R2) is connected；The other end of 4th resistance (R4) is connected with the drain electrode of the second nmos pass transistor (M2), and makees For differential reference voltage VREFN output end；The other end input difference voltage signal VINP of first resistor (R1), second resistance (R2) other end input difference voltage signal VINN.

7. receiver as claimed in claim 5, it is characterised in that：The CMOS differential comparators by the 6th nmos pass transistor~ The nmos pass transistor (M12~M17) of 9th nmos pass transistor (M6~M9), the tenth bi-NMOS transistor~the 17th, the tenth PMOS The PMOS transistor of transistor (M10), the 11st PMOS transistor (M11), the 18th PMOS transistor~the 21st (M18~ M21) constitute；

The nmos pass transistor (M6~M9) of 6th nmos pass transistor~the 9th and the tenth PMOS transistor (M10), the 11st PMOS are brilliant Body pipe (M11) constitutes preamplifier；

The source electrode of tenth PMOS transistor (M10) and the 11st PMOS transistor (M11) is connected with supply voltage vdd terminal, the Drain electrode and nineth nmos pass transistor (M9) of the grid and drain electrode of ten PMOS transistors (M10) with the 7th nmos pass transistor (M7) Drain electrode be connected；The drain electrode of the grid of 11st PMOS transistor (M11) and drain electrode and the 6th nmos pass transistor (M6) and The drain electrode of 8th nmos pass transistor (M8) is connected；The nmos pass transistor (M6~M9) of 6th nmos pass transistor~the 9th and current source One end be connected, the other end of current source ground connection GND；The grid input difference voltage signal of 6th nmos pass transistor (M6) VINP, the grid of the 9th nmos pass transistor (M9) inputs another differential voltage signal VINN；The grid of 7th nmos pass transistor (M7) Pole input difference reference voltage VREFP, the grid of the 8th nmos pass transistor (M8) inputs another differential reference voltage VREFN；

The nmos pass transistor (M12~M17) of tenth bi-NMOS transistor~the 17th and the 18th PMOS transistor~21st PMOS transistor (M18~M21) constitutes rear class dynamic latch；

The source electrode of 18th PMOS transistor (M18) and the source electrode of the 20th PMOS transistor (M20) and supply voltage vdd terminal phase Connection；The source electrode of 19th PMOS transistor (M19) and the source electrode of the 21st PMOS transistor (M21) and supply voltage VDD End is connected；The drain electrode of 18th PMOS transistor (M18) and the drain electrode of the 20th PMOS transistor (M20), the 16th NMOS The grid of the drain electrode of transistor (M16), the grid of the 21st PMOS transistor (M21) and the 17th nmos pass transistor (M17) Be connected, and its connection node as differential output voltage VOUTN output end；The leakage of 19th PMOS transistor (M19) Pole and the drain electrode, the drain electrode of the 17th nmos pass transistor (M17), the 20th PMOS crystal of the 21st PMOS transistor (M21) The grid of the grid and the 16th nmos pass transistor (M16) of managing (M20) is connected, and the node of its connection is defeated as another difference Go out voltage VOUTP output end；The grid of 18th PMOS transistor (M18) and the grid of the 19th PMOS transistor (M19) Input clock signal CLK；The source electrode of 16th nmos pass transistor (M16) is connected with the drain electrode of the 14th nmos pass transistor (M14) Connect；The grid of 14th nmos pass transistor (M14) is connected with the drain electrode of the tenth PMOS transistor (M10)；14th NMOS is brilliant The source electrode of body pipe (M14) is connected with the drain electrode of the tenth bi-NMOS transistor (M12)；The source of tenth bi-NMOS transistor (M12) Pole is grounded GND；The grid input clock signal CLK of tenth bi-NMOS transistor (M12)；

The source electrode of 17th nmos pass transistor (M17) is connected with the drain electrode of the 15th nmos pass transistor (M15)；15th NMOS The grid of transistor (M15) is connected with the drain electrode of the 11st PMOS transistor (M11)；15th nmos pass transistor (M15) Source electrode is connected with the drain electrode of the 13rd nmos pass transistor (M13)；The source ground GND of 13rd nmos pass transistor (M13)；The The grid input clock signal CLK of 13 nmos pass transistors (M13).

8. a kind of RFID reader BPSK receivers, including：

One clock circuit, for producing sampled clock signal；

One high frequency carrier demodulator, the RFID signal to input carries out sampling holding, and the high-frequency signal received and clock are believed Number mutually it is mixed, baseband signal is moved to passage from 13.56MHz high frequencies, baseband signal is exported；

Characterized in that, also including：

One variable gain bandpass filter, is connected with the high frequency carrier demodulator, for filtering out the high frequency in baseband signal Harmonic wave, out-of-band interference signal and the spuious harmonic for coming from chip itself, and with variable gain amplifier；Output filtering Baseband signal afterwards；

One or two bit Analogue digital quantizer ADC BPSK demodulator circuits, are connected with the variable gain bandpass filter, right Filtered baseband signal carries out BPSK correlation demodulations；

One automatic gain control circuit, be connected with the two bit A/Ds C BPSK demodulator circuits, by being exported after demodulation Range signal is handled, to control the gain of the variable gain filter, keeps variable gain filter output amplitude In a steady state value；

One decoder, is connected with the two bit A/Ds C BPSK demodulator circuits, for being decoded to the data flow after demodulation.

9. receiver as claimed in claim 8, it is characterised in that：The automatic gain control circuit is by counting at one section Interior ADC exports AMP=1 number of times, so as to obtain analog baseband signal after the high frequency demodulation that variable gain filter is inputted Amplitude information；The amplitude information is compared with a benchmark control word, to control ADC input range；When the amplitude information More than benchmark control word, then the gain of variable gain filter declines；Conversely, gain then increases, so that it is in the simulation Baseband signal when changing to a certain degree, and the output amplitude of variable gain filter is held essentially constant.

10. receiver as claimed in claim 8, it is characterised in that：The two bit A/Ds C BPSK demodulator circuits are difference shape Two bit A/D C BPSK demodulator circuits of formula；It is made up of three CMOS differential comparators；Wherein,

First CMOS differential comparators and the 2nd CMOS differential comparators composition AMP quantizers；3rd CMOS differential comparators are PHI quantizer；The differential output signal of variable gain bandpass filter is designated as VINP, VINN respectively, and described three are inputted respectively The input of individual CMOS differential comparators；First CMOS differential comparators and the 2nd CMOS differential comparators are respectively by the difference Output signal VINP, VINN and differential reference voltage VREFP, VREFN positive phase and antiphase are compared, result of the comparison Input to the OR gate of two inputs and obtain AMP signals；While the differential output signal VINP, VINN pass through the 3rd CMOS Differential comparator is compared with common mode electrical level and obtains PHI signals；The sampling clock of CMOS differential comparators is decoded as rear class The synchronised clock and AMP, PHI signal of circuit are exported together；

Wherein, PHI signals be used for judge bpsk signal whether zero crossing, AMP signals be used for judge output effective breadth.

11. receiver as claimed in claim 10, it is characterised in that：Differential reference voltage VREFP, the VREFN, by difference The CMOS reference voltage generating circuits generation of form；

The CMOS reference voltage generating circuits are by the resistance of first resistor~the 4th, the NMOS crystal of the first nmos pass transistor~the 3rd Pipe, the 4th PMOS transistor (M4), the 5th PMOS transistor (M5) composition；The drain electrode of first nmos pass transistor (M1) and grid, The grid of the grid of second nmos pass transistor (M2) and the 3rd nmos pass transistor (M3) is connected input current IBIAS；

The source ground of the nmos pass transistor (M1~M3) of first nmos pass transistor~the 3rd；

The source electrode of 4th PMOS transistor (M4) and the 5th PMOS transistor (M5) connects supply voltage vdd terminal；4th PMOS crystal The grid of (M4) is managed with the grid of the 5th PMOS transistor (M5) and drain electrode and the drain electrode of the 3rd nmos pass transistor (M3) to be connected Connect；The drain electrode of 4th PMOS transistor (M4) is connected with one end of 3rd resistor (R3), and is used as differential reference voltage VREFP Output end；One end, one end of first resistor (R1) and the second electricity of the other end of 3rd resistor (R3) and the 4th resistance (R4) One end of resistance (R2) is connected；The other end of 4th resistance (R4) is connected with the drain electrode of the second nmos pass transistor (M2), and makees For differential reference voltage VREFN output end；The other end input difference voltage signal VINP of first resistor (R1), second resistance (R2) other end input difference voltage signal VINN.

12. receiver as claimed in claim 10, it is characterised in that：The CMOS differential comparators are by the 6th nmos pass transistor The nmos pass transistor (M12~M17) of~the nine nmos pass transistor (M6~M9), the tenth bi-NMOS transistor~the 17th, the tenth The PMOS transistor of PMOS transistor (M10), the 11st PMOS transistor (M11), the 18th PMOS transistor~the 21st (M18~M21) is constituted；

The nmos pass transistor (M6~M9) of 6th nmos pass transistor~the 9th and the tenth PMOS transistor (M10), the 11st PMOS are brilliant Body pipe (M11) constitutes preamplifier；

The source electrode of tenth PMOS transistor (M10) and the 11st PMOS transistor (M11) is connected with supply voltage vdd terminal, the Drain electrode and nineth nmos pass transistor (M9) of the grid and drain electrode of ten PMOS transistors (M10) with the 7th nmos pass transistor (M7) Drain electrode be connected；The drain electrode of the grid of 11st PMOS transistor (M11) and drain electrode and the 6th nmos pass transistor (M6) and The drain electrode of 8th nmos pass transistor (M8) is connected；The nmos pass transistor (M6~M9) of 6th nmos pass transistor~the 9th and current source One end be connected, the other end of current source ground connection GND；The grid input difference voltage signal of 6th nmos pass transistor (M6) VINP, the grid of the 9th nmos pass transistor (M9) inputs another differential voltage signal VINN；The grid of 7th nmos pass transistor (M7) Pole input difference reference voltage VREFP, the grid of the 8th nmos pass transistor (M8) inputs another differential reference voltage VREFN；

The nmos pass transistor (M12~M17) of tenth bi-NMOS transistor~the 17th and the 18th PMOS transistor~21st PMOS transistor (M18~M21) constitutes rear class dynamic latch；

The source electrode of 18th PMOS transistor (M18) and the source electrode of the 20th PMOS transistor (M20) and supply voltage vdd terminal phase Connection；The source electrode of 19th PMOS transistor (M19) and the source electrode of the 21st PMOS transistor (M21) and supply voltage VDD End is connected；The drain electrode of 18th PMOS transistor (M18) and the drain electrode of the 20th PMOS transistor (M20), the 16th NMOS The grid of the drain electrode of transistor (M16), the grid of the 21st PMOS transistor (M21) and the 17th nmos pass transistor (M17) Be connected, and its connection node as differential output voltage VOUTN output end；The leakage of 19th PMOS transistor (M19) Pole and the drain electrode, the drain electrode of the 17th nmos pass transistor (M17), the 20th PMOS crystal of the 21st PMOS transistor (M21) The grid of the grid and the 16th nmos pass transistor (M16) of managing (M20) is connected, and the node of its connection is defeated as another difference Go out voltage VOUTP output end；The grid of 18th PMOS transistor (M18) and the grid of the 19th PMOS transistor (M19) Input clock signal CLK；The source electrode of 16th nmos pass transistor (M16) is connected with the drain electrode of the 14th nmos pass transistor (M14) Connect；The grid of 14th nmos pass transistor (M14) is connected with the drain electrode of the tenth PMOS transistor (M10)；14th NMOS is brilliant The source electrode of body pipe (M14) is connected with the drain electrode of the tenth bi-NMOS transistor (M12)；The source of tenth bi-NMOS transistor (M12) Pole is grounded GND；The grid input clock signal CLK of tenth bi-NMOS transistor (M12)；

The source electrode of 17th nmos pass transistor (M17) is connected with the drain electrode of the 15th nmos pass transistor (M15)；15th NMOS The grid of transistor (M15) is connected with the drain electrode of the 11st PMOS transistor (M11)；15th nmos pass transistor (M15) Source electrode is connected with the drain electrode of the 13rd nmos pass transistor (M13)；The source ground GND of 13rd nmos pass transistor (M13)；The The grid input clock signal CLK of 13 nmos pass transistors (M13).