CN104639128A - Anti-interference timing switch circuit - Google Patents
Anti-interference timing switch circuit Download PDFInfo
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- CN104639128A CN104639128A CN201310546085.9A CN201310546085A CN104639128A CN 104639128 A CN104639128 A CN 104639128A CN 201310546085 A CN201310546085 A CN 201310546085A CN 104639128 A CN104639128 A CN 104639128A
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Abstract
The invention discloses an anti-interference timing switch circuit, which comprises a power supply, a first audion, a second audion, a third audion, a fourth audion, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a sixth diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a potentiometer, a time base chip and a relay. The anti-interference timing switch circuit has a simple structure and stable performance. The audions, voltage stabilizing diodes, resistors and capacitors form a voltage reducing stabilizing circuit and a high threshold inverter, so that various interference pulses are suppressed, the anti-interference performance is improved, and the anti-interference timing switch circuit can be applied to multiple industrial control systems.
Description
Technical field
The present invention relates to a kind of timing switch circuit, particularly relate to a kind of jamproof timing switch circuit.
Background technology
Along with the development of electronic technology, particularly occur with large scale integrated circuit, accelerate the progress of industrial development, the current equipment of industrial product always some element is subject to outside stronger electric field, the interference of magnetic field or electrostatic field, these interference can affect the normal work of electric elements by power supply or transfer wire, in a word, in Industry Control, the adhesive of particularly high-frequency spark interference, electromagnetic interference and relay and release etc., usually bring adverse effect to circuit, the not only complex structure of timing switch circuit now, and be generally easily subject to external interference.
Summary of the invention
Object of the present invention is just to provide a kind of jamproof timing switch circuit to solve the problem.
The present invention is achieved through the following technical solutions above-mentioned purpose:
The present invention includes power supply, first triode, second triode, 3rd triode, 4th triode, first electric capacity, second electric capacity, 3rd electric capacity, 4th electric capacity, 5th electric capacity, 6th electric capacity, 7th electric capacity, first diode, second diode, 3rd diode, 4th diode, 5th diode, 6th diode, first resistance, second resistance, 3rd resistance, 4th resistance, 5th resistance, 6th resistance, 7th resistance, 8th resistance, 9th resistance, tenth resistance, potentiometer, time base chip and relay, the positive pole of described power supply is connected with the first end of described first electric capacity and the negative pole of described first diode simultaneously, with the first end of described second resistance while of the negative pole of described power supply, the first end of described 4th resistance is connected with the first end of described 8th resistance, the second end of described first electric capacity simultaneously with the collector electrode of described first triode, the first end of described 3rd resistance is connected with the second end of described 4th resistance, the positive pole of described first diode is connected with the negative pole of described second diode and the second end of described second resistance simultaneously, the positive pole of described second diode is connected with the base stage of described first triode and the first end of described first resistance simultaneously, with the second end of described first resistance while of the emitter of described first triode, the emitter of described second triode, the negative pole of described 3rd electric capacity, the first end of described 4th electric capacity, the negative pole of described 5th electric capacity, the earth terminal of base chip time described, the first end of described 6th electric capacity, the positive pole of described 3rd diode, the positive pole of described 5th diode is connected with the first end of described 9th resistance and ground connection, second end of described 3rd resistance is connected with the base stage of described second triode, the collector electrode of described second triode is connected with the first end of described 5th resistance and the second end of described 6th resistance simultaneously, with the positive pole of described 3rd electric capacity while of the second end of described 5th resistance, second end of described 4th electric capacity is connected with the trigger end of base chip time described, the second end of described 6th resistance simultaneously with the first end of described second electric capacity, the first end of described 7th resistance, the reset terminal of base chip time described, the power end of base chip time described, the emitter of described 3rd triode is connected with the first end of described 7th electric capacity, second end of described second electric capacity and the equal ground connection of the second end of described 7th electric capacity, second end of described 7th resistance is connected with the first end of described potentiometer, the sliding end of described potentiometer simultaneously with the threshold value end of base chip time described, the discharge end of base chip time described, second end of described potentiometer is connected with the positive pole of described 5th electric capacity, time described, the control end of base chip is connected with the second end of described 6th electric capacity, time described, the output of base chip is connected with the positive pole of described 4th diode, the negative pole of described 4th diode is connected with the negative pole of described 3rd diode and the first end of described tenth resistance simultaneously, with the first end of described relay coil while of the second end of described 8th resistance, the collector electrode of described 3rd triode, the first end of described 11 resistance is connected with the negative pole of described 6th diode, the base stage of described 3rd triode is connected with the second end of described 11 resistance and the negative pole of described 5th diode simultaneously, second end of described relay coil is connected with the positive pole of described 6th diode and the collector electrode of described 4th triode simultaneously, the base stage of described 4th triode is connected with the second end of described tenth resistance, and the emitter of described 4th triode is connected with the second end of described 9th resistance.
Further, described second diode and described 5th diode are voltage stabilizing didoe.
Further, described 3rd electric capacity and described 5th electric capacity are polar capacitor.
Beneficial effect of the present invention is:
Circuit structure of the present invention is simple, stable performance, by composition decompression voltage regulator and high threshold inverters such as triode, voltage stabilizing didoe and Resistor-Capacitor Units, thus suppresses various disturbing pulse, improve interference free performance, can apply in the middle of multiple industrial control system.
Accompanying drawing explanation
Fig. 1 is circuit theory diagrams of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described:
As shown in Figure 1, the present invention includes power supply, first triode VT1, second triode VT2, 3rd triode VT3, 4th triode VT4, first electric capacity C1, second electric capacity C2, 3rd electric capacity C3, 4th electric capacity C4, 5th electric capacity C5, 6th electric capacity C6, 7th electric capacity C7, first diode, second diode, 3rd diode, 4th diode, 5th diode, 6th diode, first resistance R1, second resistance R2, 3rd resistance R3, 4th resistance R4, 5th resistance R5, 6th resistance R6, 7th resistance R7, 8th resistance R8, 9th resistance R9, tenth resistance R10, potentiometer RP, time base chip IC and relay J, second diode D2 and the 5th diode D5 is voltage stabilizing didoe, 3rd electric capacity C3 and the 5th electric capacity C5 is polar capacitor, the positive pole of power supply is connected with the first end of the first electric capacity C1 and the negative pole of the first diode D1 simultaneously, with the first end of the second resistance R2 while of the negative pole of power supply, the first end of the 4th resistance R4 is connected with the first end of the 8th resistance R8, second end of the first electric capacity C1 simultaneously with the collector electrode of the first triode VT1, the first end of the 3rd resistance R3 is connected with second end of the 4th resistance R4, the positive pole of the first diode D1 is connected with the negative pole of the second diode D2 and second end of the second resistance R2 simultaneously, the positive pole of the second diode D2 is connected with the base stage of the first triode VT and the first end of the first resistance R1 simultaneously, with second end of the first resistance R1 while of the emitter of the first triode VT1, the emitter of the second triode VT2, the negative pole of the 3rd electric capacity C3, the first end of the 4th electric capacity C4, the negative pole of the 5th electric capacity C5, time base chip IC earth terminal 1, the first end of the 6th electric capacity C6, the positive pole of the 3rd diode D3, the positive pole of the 5th diode D5 is connected with the first end of the 9th resistance R9 and ground connection, second end of the 3rd resistance R3 is connected with the base stage of the second triode VT2, the collector electrode of the second triode VT2 is connected with the first end of the 5th resistance R5 and second end of the 6th resistance R6 simultaneously, with the positive pole of the 3rd electric capacity C3 while of second end of the 5th resistance R5, second end of the 4th electric capacity C4 with time base chip IC trigger end 2 be connected, second end of the 6th resistance R6 simultaneously with the first end of the second electric capacity C2, the first end of the 7th resistance R7, time base chip IC reset terminal 4, time base chip IC power end 8, the emitter of the 3rd triode VT3 is connected with the first end of the 7th electric capacity C7, second end of the second electric capacity C2 and the equal ground connection of the second end of the 7th electric capacity C7, second end of the 7th resistance R7 is connected with the first end of potentiometer RP, the sliding end of potentiometer RP simultaneously with time base chip IC threshold value end 6, time base chip IC discharge end 7, second end of potentiometer RP is connected with the positive pole of the 5th electric capacity C5, time base chip IC control end 5 be connected with second end of the 6th electric capacity C6, time base chip IC output 3 be connected with the positive pole of the 4th diode D4, the negative pole of the 4th diode D4 is connected with the negative pole of the 3rd diode D3 and the first end of the tenth resistance R10 simultaneously, with the first end of relay J coil while of second end of the 8th resistance R8, the collector electrode of the 3rd triode VT3, the first end of the 11 resistance R11 is connected with the negative pole of the 6th diode D6, the base stage of the 3rd triode VT3 is connected with second end of the 11 resistance R11 and the negative pole of the 5th diode D5 simultaneously, second end of relay J coil is connected with the positive pole of the 6th diode D6 and the collector electrode of the 4th triode VT4 simultaneously, the base stage of the 4th triode VT4 is connected with second end of the tenth resistance R10, and the emitter of the 4th triode VT4 is connected with second end of the 9th resistance R9.
The present invention has stronger antijamming capability, time wherein, base chip IC selects 555 chips, selected triode is transistor, power supply is 24V DC power supply, 3rd triode VT3 and voltage stabilizing didoe second diode D2 forms decompression voltage regulator, interference filter is carried out to 24V power supply, improve trigger impulse amplitude, the element composition high threshold inverters such as the first triode VT1 and voltage stabilizing didoe second diode D2, the disturbing pulse that amplitude is less can be suppressed, second triode VT2 and some Resistor-Capacitor Units, can be used for filtering narrow pulse interference.
Claims (3)
1. a jamproof timing switch circuit, is characterized in that: comprise power supply, first triode, second triode, 3rd triode, 4th triode, first electric capacity, second electric capacity, 3rd electric capacity, 4th electric capacity, 5th electric capacity, 6th electric capacity, 7th electric capacity, first diode, second diode, 3rd diode, 4th diode, 5th diode, 6th diode, first resistance, second resistance, 3rd resistance, 4th resistance, 5th resistance, 6th resistance, 7th resistance, 8th resistance, 9th resistance, tenth resistance, potentiometer, time base chip and relay, the positive pole of described power supply is connected with the first end of described first electric capacity and the negative pole of described first diode simultaneously, with the first end of described second resistance while of the negative pole of described power supply, the first end of described 4th resistance is connected with the first end of described 8th resistance, the second end of described first electric capacity simultaneously with the collector electrode of described first triode, the first end of described 3rd resistance is connected with the second end of described 4th resistance, the positive pole of described first diode is connected with the negative pole of described second diode and the second end of described second resistance simultaneously, the positive pole of described second diode is connected with the base stage of described first triode and the first end of described first resistance simultaneously, with the second end of described first resistance while of the emitter of described first triode, the emitter of described second triode, the negative pole of described 3rd electric capacity, the first end of described 4th electric capacity, the negative pole of described 5th electric capacity, the earth terminal of base chip time described, the first end of described 6th electric capacity, the positive pole of described 3rd diode, the positive pole of described 5th diode is connected with the first end of described 9th resistance and ground connection, second end of described 3rd resistance is connected with the base stage of described second triode, the collector electrode of described second triode is connected with the first end of described 5th resistance and the second end of described 6th resistance simultaneously, with the positive pole of described 3rd electric capacity while of the second end of described 5th resistance, second end of described 4th electric capacity is connected with the trigger end of base chip time described, the second end of described 6th resistance simultaneously with the first end of described second electric capacity, the first end of described 7th resistance, the reset terminal of base chip time described, the power end of base chip time described, the emitter of described 3rd triode is connected with the first end of described 7th electric capacity, second end of described second electric capacity and the equal ground connection of the second end of described 7th electric capacity, second end of described 7th resistance is connected with the first end of described potentiometer, the sliding end of described potentiometer simultaneously with the threshold value end of base chip time described, the discharge end of base chip time described, second end of described potentiometer is connected with the positive pole of described 5th electric capacity, time described, the control end of base chip is connected with the second end of described 6th electric capacity, time described, the output of base chip is connected with the positive pole of described 4th diode, the negative pole of described 4th diode is connected with the negative pole of described 3rd diode and the first end of described tenth resistance simultaneously, with the first end of described relay coil while of the second end of described 8th resistance, the collector electrode of described 3rd triode, the first end of described 11 resistance is connected with the negative pole of described 6th diode, the base stage of described 3rd triode is connected with the second end of described 11 resistance and the negative pole of described 5th diode simultaneously, second end of described relay coil is connected with the positive pole of described 6th diode and the collector electrode of described 4th triode simultaneously, the base stage of described 4th triode is connected with the second end of described tenth resistance, and the emitter of described 4th triode is connected with the second end of described 9th resistance.
2. jamproof timing switch circuit according to claim 1, is characterized in that: described second diode and described 5th diode are voltage stabilizing didoe.
3. jamproof timing switch circuit according to claim 1, is characterized in that: described 3rd electric capacity and described 5th electric capacity are polar capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310546085.9A CN104639128A (en) | 2013-11-06 | 2013-11-06 | Anti-interference timing switch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310546085.9A CN104639128A (en) | 2013-11-06 | 2013-11-06 | Anti-interference timing switch circuit |
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| Publication Number | Publication Date |
|---|---|
| CN104639128A true CN104639128A (en) | 2015-05-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310546085.9A Pending CN104639128A (en) | 2013-11-06 | 2013-11-06 | Anti-interference timing switch circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108494367A (en) * | 2018-03-13 | 2018-09-04 | 徐磊 | A kind of wireless network signal anti-interference process device |
| CN109089071A (en) * | 2018-10-09 | 2018-12-25 | 六安腾达信息科技有限公司 | Net meeting system |
-
2013
- 2013-11-06 CN CN201310546085.9A patent/CN104639128A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108494367A (en) * | 2018-03-13 | 2018-09-04 | 徐磊 | A kind of wireless network signal anti-interference process device |
| CN109089071A (en) * | 2018-10-09 | 2018-12-25 | 六安腾达信息科技有限公司 | Net meeting system |
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Application publication date: 20150520 |
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| WD01 | Invention patent application deemed withdrawn after publication |