CN104637522B - A kind of adaptive configurable memory IP structures of pulsewidth - Google Patents
A kind of adaptive configurable memory IP structures of pulsewidth Download PDFInfo
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Abstract
A kind of adaptive configurable memory IP structures of pulsewidth, including storage array (10), sensitive amplification and read/write circuit SA＆WR (11), row decoding circuit (12), Lie Yima ＆MUX＆ precharging circuits (14), distribute rationally circuit (20), pulse configuration module (22), driving (24), 1 dummy unit row (25), n dummy unit row (26), with the sensitive amplification SA (27) of preparatory function.The adaptive configurable memory IP structures of pulsewidth of the present invention are when upper electric, pass through the internal read that circuit (20) produces once different pulse widths of distributing rationally built in memory I P-structure, and to data lookup table analysis of reading back, the final optimization afterpulse width for determining to be adapted to the memory I P-structure of device working environment, memory reads sequential to the present invention with certain chip area cost optimization, and then optimizes the reading speed and dynamic power consumption of memory I P-structure.
Description
Technical field
The present invention relates to a kind of memory I P-structure, the adaptive configurable memory IP structures of particularly a kind of pulsewidth.
Background technology
Traditional memory I P-structure, mainly including storage array, row decoding circuit, Lie Yima ＆MUX＆ precharging circuits, spirit
Quick amplification SA＆WR and fixed pulse are produced, using burst mode controller part work schedule, fixed pulse produce read in IP/
During write operation, generation fixed pulse width T control pulse is respectively transmitted to row decoding circuit, Lie Yima ＆MUX＆ precharge
Road, sensitive amplification SA＆WR, generation chopping IP read-write sequence.IP is in read operation, by the unique row of row decoding circuit evolving
Strobe signal, for the gating of memory cell rows, the row unit gated is opened and to the bit line that is connected to putting
Electricity, and bit line is produced to voltage difference；Unique row gate pulse is generated by column decoding precharging circuit to each group of MUX to believe
Number, for sending the bit line for choosing row to corresponding sensitive amplification SA＆WR to voltage difference, and by SA by bit-line voltage difference
Amplification, produces effective reading data, and export by read/write circuit WR.IP is in write operation, by Lie Yima ＆MUX＆ precharging circuits
Unique column selection strobe signal is generated to each group of MUX, for the write-in data transfer that transmits read/write circuit WR to choosing
The bit line of row, and make to choose bit line to producing the big bit line of supply voltage to voltage difference；It is unique by row decoding circuit evolving
Row strobe signal, opens memory cell rows, and there will be the bit line storage value write storage unit of supply voltage difference.
According to the read/write Time-Series analysis to traditional memory I P-structure, it is straight that fixed pulse generates pulse width
Connect that influence row gating, column selection be logical and operation pulsewidth of SA, and these pulse duration effects are to the read access time of device, and pass through position
Line has influence on the power consumption of device to the size of voltage difference.Reduce pulse width, device reading speed can be improved and power consumption is reduced,
Increase pulse width, device reading speed can be reduced and increase power consumption.Under various circumstances, memory I P-structure is by environment shadow
Ring, pulse width needed for normal read/write operation has certain difference, and fixed pulse was produced in the design phase, to ensure that device can
By sex work, larger design margin is reserved, therefore the IP work pulsewidths worked in varying environment and be not optimised, to the property of device
There can be certain influence.
The content of the invention
Present invention solves the technical problem that being：Overcome the shortcomings of under varying environment that the pulse of IP read/write fixes that there is provided one kind
The adaptive configurable memory IP structures of pulsewidth, carry out pulse optimization according to device working environment with certain area cost and match somebody with somebody
Put, so as to improve the performance of device.
The present invention technical solution be：A kind of adaptive configurable memory IP structures of pulsewidth, including storage battle array
Row, sensitive amplification and read/write circuit SA＆WR, row decoding circuit, Lie Yima ＆MUX＆ precharging circuits, distribute circuit, pulse rationally and match somebody with somebody
Module, 1 dummy unit row, n dummy unit row, sensitive amplification SA modules are put, wherein
Distribute circuit rationally, including upper electricity reads configuration generation unit, read back comparing unit and pulse choice configuration list
Member；Upper electricity reads configuration generation unit and the n preset lists that electric read strobe signal is delivered in 1 dummy unit row is produced when upper electric
Electric start pulse signal delivers to pulse choice dispensing unit in member, generation；The comparing unit that reads back receives sensitive amplification SA moulds
The n place reading evidences that block is sent, and be compared with built-in pulse configuration table of tabling look-up, it is determined that the optimal pulse needed for normal read-write
Width, and the sequence number of the corresponding pre-calibration pulse signal of optimal pulse width is delivered into pulse choice dispensing unit；It is described to table look-up
Pulse configuration table is n × n two-dimensional data table, includes the efficient combination of n kind n place reading evidences, and row represents n place readings according to right with it
The sequence number for the n roads pre-calibration pulse signal answered, row represent value of the n kind n place readings according to a certain position, and n place readings evidence is predisposed to 0/1 sequence
Row, 1 pulsewidth for representing this road pre-calibration pulse signal i-th bit is adapted to store IP in current operating environment wherein in onboard data,
IP correct read-write operation can be completed, 0 is not suitable in current operating environment for the pulsewidth of the i-th bit of this road pre-calibration pulse signal
Store IP, it is impossible to complete IP correct read-write operation, i=1,2,3,, n；
Pulse choice dispensing unit, electricity is read after the upper electric start pulse signal that configuration generation unit is sent on receiving,
The n difference that configuration signal is delivered in pulse configuration module is read by the upper electricity reading configuration signal of pulse edge triggering generation, and by upper electricity
Pulse width unit；Receive the sequence number of the corresponding pre-calibration pulse signal of optimal pulse width for comparing unit transmission of reading back
Afterwards as normal read configuration signal, and the pulse width selecting unit delivered in pulse configuration module；
Pulse configuration module, including n different pulse width units, pulse width selecting unit；N different pulse width
Generation n road pre-calibration pulse signals are delivered to sensitive after unit, the upper electricity reading configuration signal that reception pulse choice dispensing unit is sent
Amplify SA modules and pulse width selecting unit；The pulse width of the n roads pre-calibration pulse signal is respectively T, T+ ⊿ t ... T+
(n-1)×⊿t；Pulse width selecting unit, receives the n roads pre-calibration pulse signal that n different pulse width units are sent, so
The normal read configuration signal for receiving the transmission of pulse choice dispensing unit afterwards selects pulsewidth optimal from n roads pre-calibration pulse signal
Pulse signal as normal work pulse, and deliver to row decoding circuit, Lie Yima ＆MUX＆ precharging circuits and sensitive amplification and
Read/write circuit SA＆WR；
Row decoding circuit, is received after the normal work pulse that pulse width selecting unit is sent, and produces row choosing all the way
Messenger simultaneously delivers to storage array；
Storage array, including n rows, m row memory cell, receive and are selected after the gating signal of row all the way that row decoding circuit is sent
Lead to the line storage unit, when read operation, the line storage unit, to discharging, makes bit line to producing spirit to the bit line connected
Quick amplification and the recognizable voltage differences of read/write circuit SA＆WR；Receive the multichannel column selection communication that Lie Yima ＆MUX＆ precharging circuits are sent
Number, respective column bit line is passed to sensitive amplification and read/write circuit SA＆WR to voltage；
Lie Yima ＆MUX＆ precharging circuits, are received after the normal work pulse that pulse width selecting unit is sent, according to
MUX structure produces multichannel column selection messenger and delivers to control storage array；
Sensitive amplification and read/write circuit SA＆WR, are received after the normal work pulse that pulse width selecting unit is sent,
Sense amplifier SA unbalanced pulse is produced, bit line that storage array sends is received to voltage difference and is amplified and obtains exporting number
According to output data is exported；Input data is received, and the bit line for receiving storage array transmission writes data into storage to voltage
Array；
1 dummy unit row, including n preset unit, m memory cell；Upper electricity is received in n preset unit and reads configuration production
Opening unit after the upper electric read strobe signal that raw unit is sent, and by the storage value built in unit to the bit line that is connected to putting
Electricity, so as to generate n bit line to voltage difference, and delivers to n dummy unit row respectively, wherein, in n preset unit i-th it is preset
Unit is connected with i-th of dummy unit row in n dummy unit row, i=1, and 2,3,, n；The preset unit is that storage inside value is pre-
It is set to 1 memory cell；
N dummy unit row, each dummy unit row include n memory cell, and i-th of i-th of dummy unit row reception is preset
The bit line that unit is sent is to delivering to i-th of sense amplifier SA in sensitive amplification SA modules after voltage difference；
Sensitive amplification SA modules, including n sense amplifier SA, i-th of sense amplifier SA, receive n different pulse
I-th the i-th tunnels of tunnel pre-calibration pulse signal Bing pre-calibration pulse letter that i-th of different pulse width unit is sent in width unit
Gated during number, receive the bit line that i-th of dummy unit row is sent in n dummy unit row and to voltage difference and bit line is entered to voltage difference
Row amplifies, if the bit line that i-th of dummy unit row after amplification are sent is less than to voltage difference built in sensitive amplification SA modules
Normal readable data pulse width threshold, then on the contrary it is 0 that i-th bit, which reads data, then be 1, obtains delivering to after n place readings evidence and distributes rationally
The comparing unit that reads back in circuit.
The advantage of the present invention compared with prior art is：
(1) present invention is directed to the deficiency of legacy memory IP structure fixed pulse widths, and the pulse of reset-to-n road is given birth to inside IP
Into, the pulse width for being adapted to optimize under prevailing circumstances is produced by configuration operation produced during electricity on device in application environment,
Device performance is optimized, is compared with existing conventional memory IP structures, with environment self-adaption, the adjustable spy of pulse width
Point；
(2) it is of the invention compared with existing conventional memory IP structures, with faster read access time；
(3) it is of the invention compared with existing conventional memory IP structures, with lower reading power consumption.
Brief description of the drawings
Fig. 1 is traditional memory I P circuit structures；
Fig. 2 is the adaptive configurable memory IP structures of the pulsewidth of the present invention；
Fig. 3 is pulse configuration functions of modules block diagram representation of the present invention；
Fig. 4 is provided n roads pulse relation schematic diagram by pulse configuration module of the present invention；
Fig. 5 is that the present invention distributes circuit block diagram schematic diagram rationally；
Fig. 6 distributes the pulse configuration table of tabling look-up built in circuit rationally for the present invention；
Fig. 7 is a dummy unit row block diagram representation of the invention；
Fig. 8 is that n dummy unit of the present invention is arranged and with the sensitive amplification SA schematic diagrames of preparatory function.
Embodiment
As shown in figure 1, traditional memory I P circuit structures, including storage array 110, row decoding circuit 120, row are translated
Code ＆MUX＆ precharging circuits 130, sensitive amplification SA＆WR140 and fixed pulse produce 150.Fixed pulse produce 150 IP read/
During write operation, generation fixed pulse width T control pulse is respectively transmitted to row decoding circuit 120, Lie Yima ＆MUX＆ preliminary fillings
Circuit 130, sensitive amplification SA＆WR140, generation chopping IP read-write sequence.IP is in read operation, and row decoding circuit 120 is given birth to
Into unique row strobe signal, for gating the only one memory cell rows in storage array, the row unit gated
Open and to the bit line that is connected to discharging, and produce bit line to voltage difference；130 pairs of Lie Yima ＆MUX＆ precharging circuits are every
One group of MUX generates unique column selection strobe signal, corresponding sensitive for the bit line for choosing row to be sent to voltage difference
Amplify SA＆WR140, and amplified bit line to voltage difference by SA, produce effective reading data, and it is defeated by read/write circuit WR
Go out.IP is in write operation, and Lie Yima ＆MUX＆ precharging circuits 130 generate unique column selection strobe signal to each group of MUX, uses
In the write-in data for transmitting read/write circuit WR in sensitive amplification SA＆WR140, the bit line pair for choosing row is passed to, and make to choose
Bit line is to producing the big bit line of supply voltage to voltage difference；Row decoding circuit 120 generates unique row strobe signal, opens
Memory cell rows are opened, and there will be the bit line storage value write-in storage array of big voltage difference.
As shown in Fig. 2 the adjustable memory I P circuit structures of the adaptive pulse of the present invention include storage array 10, sensitive amplification
And read/write circuit SA＆WR11, row decoding circuit 12, Lie Yima ＆MUX＆ precharging circuits 14, distribute circuit 20, pulse configuration rationally
Module 22, driving 24, dummy unit row 25, n dummy unit row 26, with modules such as the sensitive amplification SA 27 of preparatory function.This hair
The bright cooperation by multimode, can be according to the pulse width of the adaptively selected optimization of change of device use environment, so as to improve
Device performance.
Fig. 3 is pulse configuration functions of modules block diagram representation, and pulse configuration module 210 includes n different pulse width list
Member (such as pulse width nt210,, pulse width t212), pulse width selecting module 213, device is when upper electric, and upper electricity is read to match somebody with somebody
Confidence number opens n roads pulse width unit, produces n road pre-calibration pulse signals.Normal read configuration signal pulse-width is selected
Module 213 is selected, and finally the selection optimization pulse unit from the pulse unit of n different pulse widths, is provided by it IP normal
Pulse signal after optimizing during read-write operation, wherein n >=2, realize that area, optimization requirement etc. are determined according to chip.
Fig. 4 show pulse configuration module and provides n roads pre-calibration pulse relation, and each road pulse width has differences, such as
The pulsewidth of figure pre-calibration pulse width 1 is T (T values are that storage array reads reference pulse width), thereafter per road pre-calibration pulse
Width it is upper all the way on the basis of Zeng Jia ⊿ t, pre-calibration pulse width n pulse width be T+ (n-1) × ⊿ t, Qi Zhong ⊿ t values
Determined according to n size and optimization precision.
Fig. 5, which is shown, distributes circuit function block diagram rationally, and electricity reading configuration generation list can be divided into by distributing circuit 20 rationally
Member 403, reading data comparing unit 401 and pulse choice dispensing unit 402, upper electricity are read to produce during electricity on configuration generation unit 403
Upper electric read strobe signal, 1 dummy unit row 25 is opened by driving 24, while upper electric trigger pulse and the comparing unit that reads back
Electricity reads configuration signal and normal read configuration signal in 401 input signal co- controlling pulse choice dispensing unit 402, generation,
Wherein upper electricity reads configuration signal and opens n roads pulse width unit (such as pulse width nt 211, pulse width t212 in Fig. 3 simultaneously
Deng), normal read configuration signal generation is that, according to analysis, the signal generated is used based on the comparing unit 401 that reads back to n place readings
The pulse that device works in working environment is best suitable for all the way in being chosen from the pulse width unit of n roads, generates normal read/write arteries and veins
Punching.
Fig. 6 is to distribute the pulse configuration table of tabling look-up built in circuit rationally, by the contrast of the n-bit data to reading back, wherein 1
Represent to control the pre-calibration pulse in the pseudo- bit line column path in this road to be adapted to store IP in working environment, can correctly read storage battle array
Any cell value in row, 0 represents to control the pre-calibration pulse in the pseudo- bit line column path in this road to be not suitable for storing in working environment
IP, it is impossible to reliable to read storage unit values in storage array.As shown in Figure 6, by determining the lowest order 1 in n-bit data that reads back
Position (lowest order is the 1st, and highest order is n-th), you can it is determined that the pulse width needed for normal read-write, that is, Fig. 3
In corresponding configuration pulse width module sequence number.The two-dimensional data table that pulse configuration table is n × n of tabling look-up, including n kinds n
The efficient combination of place reading evidence, row represents sequence number of the n place readings according to corresponding n roads pre-calibration pulse signal, and row represent n kinds
N place readings are according to the value of a certain position, and n place readings are according to 0/1 sequence is predisposed to, and 1 represents this road pre-calibration pulse wherein in onboard data
The pulsewidth of signal i-th bit is adapted to store IP in current operating environment, can complete IP correct read-write operation, and 0 is the pre- school in this road
The pulsewidth of quasi- pulse signal i-th bit is not suitable for storing IP in current operating environment, it is impossible to complete IP correct read-write operation, n
Place reading with n kinds efficient combination in pulse configuration table according to being compared, if combining identical with i-th kind of n-bit data, read back number
The corresponding sequence number of the i-th tunnel pre-calibration pulse signal is sent to pulse configuration unit 402, i=1 according to comparison unit 401,2,3,,
n。
Fig. 7 is a dummy unit row block diagram, and a dummy unit row 51 is made up of two parts unit group：N preset unit 510
With m unit, n preset unit 510 connects with n dummy unit row respectively, and its storage inside value is predisposed to 1, so ensures
Data of reading back during correct reading should be 1, known by Fig. 6 codings, according to the coding for data 0/1 of reading back, produce normal read configuration
Signal；M unit, unit is as cells of memory arrays, and bit line, to being connected, is only used for simulation and deposited not with storage array neutrality line
Store up array word line load.On domain position, preset unit is poorer than the reading timing path of any unit in storage array.
Fig. 8 is that n dummy unit is arranged and with the sensitive amplification SA structural representations of preparatory function, in structure 60, includes n
Dummy unit row (each column is connected by unit 520 to be formed, and cell height is high consistent with being arranged in storage array), n sense amplifier SA
620 and prewired circuit 630 constitute, each row are connected with a preset unit 510 in dummy unit row 51 in Fig. 7, dummy unit
Arrange the load for analog storage array neutrality line pair；Sense amplifier SA 620 is used for the row dummy unit row bit line that will be connected
Voltage difference is amplified and exported, n place reading evidences are formed, each SA is read by a pre-calibration pulse width signal control data；
When prewired circuit 630 is used for upper electric on the set of SA output datas, device during electricity, the n place readings evidence that SA is exported is set to 0, this
Sample can distinguish whether the upper data of dummy unit row are correctly read, i.e. the numerical value 1 stored in Fig. 7 in preset unit 510 whether by
Amplification is read, if pre-calibration pulse width, which is less than, reads required pulse width, SA output datas maintain 0, otherwise are 1, root
According to n place readings, 0/1 numerical value is arranged in, it may be determined that be adapted to the work pulsewidth of memory I P optimization under this working environment.
Row decoding circuit 12 is received after the normal work pulse that pulse width selecting unit 213 is sent, and produces only one
The effective row gating signal in road, i.e. wordline open signal, make in storage array 10 only have a line storage unit be selected, choose
Line storage unit gate pipe is opened, in read operation process, and the complementary logic that memory cell is stored can be to the bit line pair that is connected
Discharged, make bit line to producing voltage difference recognizable SA in sensitive amplification and read/write circuit SA＆WR11；Lie Yima ＆MUX＆
Precharging circuit 14 is received after the normal work pulse that pulse width selecting unit 213 is sent, and multichannel is produced according to MUX structure
Effective column selection messenger, enables the row bit line chosen in storage array to pass to sense amplifier SA to voltage difference；It is sensitive to put
Big and read/write circuit SA＆WR11 is received after the normal work pulse that pulse width selecting unit 213 is sent, and produces opening for SA
Pulse is opened, within the effective SA working times, the bit line passed over is amplified processing to voltage difference, and by reading and writing electricity
Road WR is exported the valid data after amplification.
1 dummy unit row 25, including n preset unit 510, m memory cell 520；N preset unit 510 is pseudo- with n
Cell columns 26 are connected, and m memory cell 520 is not connected with storage array 10.N preset unit 510 receives upper electricity and reads to match somebody with somebody
Put and opened after the upper electric read strobe signal of the transmission of generation unit 403, each preset unit is that storage inside value is predisposed to 1 storage list
Member, preset unit is to the row bit line connected to discharging, and the bit line that generation n has voltage difference delivers to n to signal
Bit location row 26, each bit line pair is connected with the dummy unit row in 26.
N dummy unit row 26 include n row dummy units, each dummy unit row with every array storage unit in storage array 10
520 numbers are identical, and circuit and physical arrangement are consistent, and i-th of dummy unit arranges the bit line with i-th of preset unit 510 to being connected,
And bit line is respectively sent to i-th of sense amplifier SA620 in sensitive amplification SA modules 27 to voltage difference.
The content not being described in detail in description of the invention belongs to the known technology of those skilled in the art.
Claims (1)
1. the adaptive configurable memory IP structures of a kind of pulsewidth, it is characterised in that including storage array (10), sensitive amplification
And read/write circuit SA＆WR (11), row decoding circuit (12), Lie Yima ＆MUX＆ precharging circuits (14), distribute rationally circuit (20),
Pulse configuration module (22), 1 dummy unit row (25), n dummy unit row (26), sensitive amplification SA modules (27), wherein
Distribute circuit (20) rationally, including upper electricity reads configuration generation unit (403), read back comparing unit (401) and pulse
Option and installment unit (402)；Upper electricity reads configuration generation unit (403) and produces electric read strobe signal when upper electric to deliver to 1 puppet
Electric start pulse signal delivers to pulse choice dispensing unit (402) in n preset unit (510) in cell row (25), generation；
The comparing unit (401) that reads back receives the n place reading evidences of sensitive amplification SA modules (27) transmission, and with built-in pulse of tabling look-up
Allocation list is compared, it is determined that the optimal pulse width needed for normal read-write, and by the corresponding pre-calibration arteries and veins of optimal pulse width
The sequence number for rushing signal delivers to pulse choice dispensing unit (402)；The two-dimensional data table that pulse configuration table is n × n, bag of tabling look-up
The efficient combination of n kind n place reading evidences is included, row represents sequence number of the n place readings according to corresponding n roads pre-calibration pulse signal, row
Value of the n kind n place readings according to a certain position is represented, n place readings are according to 0/1 sequence is predisposed to, and 1 represents the pre- school in this road wherein in onboard data
The pulsewidth of quasi- pulse signal i-th bit is adapted to store IP in current operating environment, can complete IP correct read-write operation, and 0 is this road
The pulsewidth of the i-th bit of pre-calibration pulse signal is not suitable for storing IP in current operating environment, it is impossible to the correct read-write behaviour for completing IP
Make, i=1,2,3 ..., n；
Pulse choice dispensing unit (402) electricity on receiving reads the upper electric trigger pulse letter that configuration generation unit (403) is sent
After number, by pulse, along triggering generation, above electricity reads configuration signal, and upper electricity reading configuration signal is delivered in pulse configuration module (22)
N different pulse width unit；Reception read back comparing unit (401) transmission the corresponding pre-calibration of optimal pulse width
As normal read configuration signal after the sequence number of pulse signal, and the pulse width selecting unit delivered in pulse configuration module (22)
(213)；
Pulse configuration module (22), including n different pulse width units, pulse width selecting unit (213)；N different arteries and veins
Width unit is rushed, n roads pre-calibration pulse letter is produced after receiving the upper electricity reading configuration signal that pulse choice dispensing unit (402) is sent
Number deliver to sensitive amplification SA modules (27) and pulse width selecting unit (213)；The pulse of the n roads pre-calibration pulse signal is wide
Degree be respectively T, T+ ⊿ t ..., T+ (n-1) × ⊿ t；Pulse width selecting unit (213), receives n different pulse width unit
The n roads pre-calibration pulse signal of transmission, then receives normal read configuration signal that pulse choice dispensing unit (402) sends from n
The optimal pulse signal of pulsewidth is selected in road pre-calibration pulse signal as normal work pulse, and delivers to row decoding circuit
(12), Lie Yima ＆MUX＆ precharging circuits (14) and sensitive amplification and read/write circuit SA＆WR (11), wherein, pulse is wide on the basis of T
Du , ⊿ t are the tolerance of n different pulse widths；
Row decoding circuit (12), receives after the normal work pulse that pulse width selecting unit (213) is sent, produces all the way
Row gating signal simultaneously delivers to storage array (10)；
Storage array (10), including n rows, m row memory cell, receive the row gating signal all the way that row decoding circuit (12) is sent
The backgating corresponding line storage unit of road row gating signal, when read operation, the line storage unit is to the bit line pair that is connected
Discharged, make bit line to producing sensitive amplification and the recognizable voltage differences of read/write circuit SA＆WR (11)；Receive column decoding ＆
The multichannel column selection messenger that MUX＆ precharging circuits (14) are sent, makes respective column bit line pass to sensitive amplification and read-write electricity to voltage
Road SA＆WR (11)；
Lie Yima ＆MUX＆ precharging circuits (14), receive the normal work pulse that pulse width selecting unit (213) is sent
Afterwards, multichannel column selection messenger is produced according to MUX structure and delivers to control storage array (10)；
Sensitive amplification and read/write circuit SA＆WR (11), receive the normal work pulse arteries and veins that pulse width selecting unit (213) is sent
After width, produce sense amplifier SA unbalanced pulse, receive that storage array (10) sends bit line is to voltage difference and is amplified
Output data is obtained, output data is exported；Receive input data, and receive storage array (10) transmission bit line to voltage,
Write data into storage array (10)；
1 dummy unit row (25), including n preset unit (510), m memory cell (520)；In n preset unit (510)
Electricity reads opening unit after the upper electric read strobe signal that configuration generation unit (403) is sent in reception, and passes through depositing built in unit
Stored Value, to discharging, so as to generate n bit line to voltage difference, and delivers to n dummy unit row (26) respectively to the bit line that is connected, its
In, i-th of preset unit arranges i-th of dummy unit row in (26) with n dummy unit and is connected in n preset unit (510), i=1,
2,3,, n；The preset unit is the memory cell that storage inside value is predisposed to 1；
N dummy unit arranges (26), and each dummy unit row include n memory cell (520), and i-th of dummy unit row is received i-th
The bit line that preset unit (510) is sent is to delivering to i-th of sense amplifier SA in sensitive amplification SA modules (27) after voltage difference
(620)；
Sensitive amplification SA modules (27), including n sense amplifier SA (620), i-th of sense amplifier SA (620) receive n
I-th the i-th tunnels of tunnel pre-calibration pulse signal Bing that i-th of different pulse width unit is sent in individual different pulse width units are pre-
Gated during calibration pulse signal, receive the bit line of i-th of dummy unit row transmission in n dummy unit row (26) to voltage difference and right
Bit line is amplified to voltage difference, if the bit line that i-th of dummy unit row after amplification are sent is less than sensitive amplification to voltage difference
Built-in normal readable data pulse width threshold in SA modules (27), then on the contrary it is 0 that i-th bit, which reads data, then be 1, obtains n and reads
The comparing unit (401) that reads back distributed rationally in circuit (20) is delivered to after data.
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| CN1159058A (en) * | 1996-01-30 | 1997-09-10 | 株式会社日立制作所 | Semiconductor integrated circuit device having synchronous function with plurality of external clocks |
| CN1214516A (en) * | 1997-10-02 | 1999-04-21 | 株式会社日立制作所 | Semiconductor integrated circuit device |
| EP0973167A2 (en) * | 1998-07-17 | 2000-01-19 | Kabushiki Kaisha Toshiba | High-speed cycle clock-synchronous memory device |
| CN102171761A (en) * | 2011-04-18 | 2011-08-31 | 华为技术有限公司 | Timing processing method and circuit for synchronous static random accessible memory (SRAM) |
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