CN104636253A - Cross clock domain logic ASIC verification system and method based on metastable state injection - Google Patents
Cross clock domain logic ASIC verification system and method based on metastable state injection Download PDFInfo
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- CN104636253A CN104636253A CN201510015597.1A CN201510015597A CN104636253A CN 104636253 A CN104636253 A CN 104636253A CN 201510015597 A CN201510015597 A CN 201510015597A CN 104636253 A CN104636253 A CN 104636253A
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Abstract
The invention discloses a cross clock domain logic ASIC verification system and method based on metastable state injection. The system comprises an on-chip system for cross clock domain logic independent modularizing design, a parametric configuration unit for metastable state injection of a cross clock domain module, an ASIC logic analyzing unit for logic tracking of cross clock domain signals, a key node verification unit for data monitoring and result recording of cross clock domain signals, and a verification configuration file for embedded verification of cross clock domain logic. Compared with the prior art, the system and method have the advantages that the metastable state abstract modeling is added, the verification requirements for high-efficiency control, observation, result recording and the like of cross clock domain logic are met at the same time, and the system and method are effectual compensation for a traditional verification method and are high in practicability.
Description
Technical field
The present invention relates to computer chip technology field, specifically a kind of practical, based on metastable state inject cross clock domain logic ASIC verification system and method.
Background technology
Along with the continuous expansion in chip application field, multi-clock logic ubiquity in SOC (system on a chip).The correct transmission of cross clock domain signal becomes correct, the reliable and stable basic guarantee of SOC (system on a chip) function with reception.But asynchronous due to transmitting terminal and receiving end clock, both phase relations may be completely uncontrollable, even the transmission of asynchronous signal can change at any time, and the foundation/retention time likely causing asynchronous signal saltus step can not meet receiving register requires and produces the metastable state phenomenon of signal.Because traditional static timing analysis mode can only be analyzed the sequential relationship of stationary phase, fixed delay signal, and logic simulation mode also can only be observed the logic behavior under limited excitation space and specific delay condition, therefore can not directly adopt traditional ASIC checking means to carry out complete logic checking for this this chance phenomenon of asynchronous signal metastable state cannot avoided completely physically, metastable state phenomenon is a kind of physical phenomenon certainly existed in asynchronous signalling and receiving course.And, due to the randomness of asynchronous signal transmission, cause this phenomenon to be difficult to adopt common analysis verification means to test out in ASIC logic design process.
Traditional ASIC verification method mainly concentrates on two aspects: one is the structuring identification and analysis of cross clock domain logic; Two is the function point checkings directly being carried out system by logic simulation or Formal Verification means.The capability error that actual chips causes due to the metastable state of asynchronous signal can not accurately and be intactly got rid of, because these verification methods all do not characterize this chance phenomenon of metastable state by the analysis of these two aspects.
Based on this, a kind of cross clock domain logic ASIC verification system based on metastable state injection and method being now provided, by carrying out abstract modeling to metastable state, thus traditional direct ASIC verification method being improved.
Summary of the invention
Technical assignment of the present invention is for above weak point, provide a kind of practical, based on metastable state inject cross clock domain logic ASIC verification system and method.
Based on the cross clock domain logic ASIC verification system that metastable state is injected, its structure comprises:
Separate modularization design is in the cross clock domain logic of SOC (system on a chip);
Parametrization dispensing unit, realize the flexible configuration of the parameter to metastable state signal and synchronous logic, described parameter comprises: across shot clock cycle, the phase shift of clock signal, metastable state signal error threshold value, randomization, SYN register set up retention time, initiation parameter; The logical organization that this parametrization dispensing unit is integrated simultaneously carries out effective asynchronous signal and logical factor adjustment according to the parameter value of setting to cross clock domain logic;
ASIC logic analysis unit, by analyzing the propagation of cross clock domain signal in ASIC logic, determining the network node of easy occurrence logic mistake, it is classified as functional verification key node, realizing the logical tracing to cross clock domain logical signal;
Key node authentication unit, the key element of checking comprises modular excited data, the result, signal attribute, asserts, realizes the data monitoring to cross clock domain signal, outcome record;
Checking auxiliary file, associates parametrization dispensing unit, key node authentication unit with the cross clock domain logic realization of SOC (system on a chip), and for carrying out embedded authentication to cross clock domain logic.
Described ASIC verification system adopts SystemVerilog language to be made.
A kind of cross clock domain logic ASIC verification method injected based on metastable state, its specific implementation process is: ASIC logic analysis unit submits to key node authentication unit the cross clock domain checking key node extracted from SOC (system on a chip), and this key node authentication unit validation signal is monitored; On verification platform, parametrization dispensing unit, key node authentication unit and each cross clock domain logic module in SOC (system on a chip) and corresponding key node associate, for functional simulation or Formal Verification is completed according to analyzing the checking auxiliary file produced; The function of parameter configuration, metastable state injection, data monitoring, judgement, mistake and statistics record is completed in whole proof procedure.
A kind of cross clock domain logic ASIC verification system based on metastable state injection of the present invention and method, have the following advantages:
A kind of cross clock domain logic ASIC verification system based on metastable state injection of this invention and method add the abstract modeling to this chance phenomenon of metastable state in traditional checking means, meet simultaneously cross clock domain logic controlled efficiently, observe, the checking demand such as outcome record, being that the one that proposes traditional verification method is effective supplements; For SOC (system on a chip) anti-metastable state disturbance-proof design under the multi-clock zone condition of complexity provides a kind of checking means newly, practical, be easy to realize, be easy to promote.
Accompanying drawing explanation
Accompanying drawing 1 is verification system structural representation of the present invention.
Accompanying drawing 2 is cross clock domain logic embodiment figure of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described.
The metastable state phenomenon considering cross clock domain signal in the design process of SOC (system on a chip) and the logic error that may cause thereof are not easy the problem of observing and controlling, the present invention proposes a kind of cross clock domain logic ASIC verification system based on metastable state injection and method, the mode that this invention adopts a kind of parameterisable to configure, realize metastable state neatly to cross clock domain logic to inject, the key checking node simultaneously can treating verifying logic carries out data monitoring, outcome record etc.
ASIC verification system of the present invention and method make full use of the abstract behavioral scaling modeling ability of SystemVerilog language enrichment, and conventional authentication means are if logic simulation, Formal Verification are to comprehensive support of SystemVerilog language.Based on this language, build parameterisable configuration module, realize the flexible configuration of the numerous parameters to metastable state signal and synchronous logic at the higher level of abstract degree.On the other hand, the logical organization that parametrization configuration module is integrated can carry out effective asynchronous signal and logical factor adjustment according to the parameter value of setting to cross clock domain function logic.Verification system of the present invention can extract the key node causing logic error in SOC (system on a chip) due to asynchronous signal metastable state automatically, completes the function such as record of the metastable state signal injection to cross clock domain logic, the monitoring of verification msg, judgement, capability error and coverage rate result in the functional verification process of system.
As shown in Figure 1, a kind of cross clock domain logic ASIC verification system injected based on metastable state, its structure comprises:
Cross clock domain logic, the cross clock domain logic separate modularization design of SOC (system on a chip), this requirement is not only conducive to the reusability design of function logic, and very beneficial to the identification of its functional verification, packaging.
Parameterisable dispensing unit, it can be used for across shot clock cycle of clock signal, phase shift, metastable state signal error threshold value, randomization, the foundation/parameter such as retention time, initialization of SYN register is arranged, and realizes the injection controlled flexibly to metastable state signal.
ASIC logic analysis unit, by analyzing the propagation of cross clock domain logical signal in ASIC logic, determining the network node of easy occurrence logic mistake, it is classified as functional verification key node, realizing the logical tracing to cross clock domain signal.
Key node authentication unit, excited data, the result, the signal attribute of Universal, modular, to assert etc. and checking key element realizes the data monitoring to cross clock domain signal, outcome record.
Checking auxiliary file, associates parametrization dispensing unit, key node authentication unit with the cross clock domain logic realization of SOC (system on a chip), and for the associated documents of functional verification, for the embedded authentication to cross clock domain logic.
Can find out in the verification system structural representation shown in accompanying drawing 1, due to the separate modularization design in SOC (system on a chip) of cross clock domain logic, when this is convenient to the cross clock domain signal of ASIC logic analysis element analysis SOC (system on a chip), this synchronous logic be identified.Meanwhile, such process also facilitates parametrization dispensing unit to carry out parameter loading to cross clock domain logic.By the structure in this accompanying drawing, the present invention also provides a kind of cross clock domain logic ASIC verification method injected based on metastable state, its specific implementation process is: ASIC logic analysis unit submits to key node authentication unit the cross clock domain checking key node extracted from SOC (system on a chip), monitors for validation signal.On verification platform, parametrization dispensing unit, key node authentication unit and each cross clock domain logic module in SOC (system on a chip) and corresponding key node associate, for functional simulation or Formal Verification is completed according to analyzing the checking auxiliary file produced.The function of the outcome record such as parameter configuration, metastable state injection, data monitoring, judgement, mistake and statistics is completed in whole proof procedure.
Embodiment: a cross clock domain logic as shown in Figure 2 implements schematic diagram.
In this embodiment, the transmission of n-bit data between clock zone A to clock zone B is completed.Be two-stage register synchronization module in dotted line frame, namely the cross clock domain logic of these group data adopts separate modularization design.In the SOC (system on a chip) of reality, this n-bit data may be that synchronously to receive from multiple B clock zones of same a data also may be that the difference of different bit data synchronously receives.But convergence has appearred in the n-bit data after synchronous in this embodiment, namely n-bit data has converged to 1 bit data by combinational logic and has exported.This being designed with may cause the logical beat of data of A clock zone clapped reception by B clock zone mistake and occur logic error due to the metastable state phenomenon of each group of two-stage SYN register.By system and method for the present invention, when verifying, different parameter values can be set respectively to each group of two-stage SYN register and inject to the metastable state realizing different shape.ASIC logic analysis element analysis system logic determine synchronous before data 1 to data n sending point and synchronous after convergence point as checking key node.If n position sends data from different data bit, be necessary when verifying to check this n-bit data whether through Gray code at transmission key node place.At convergence key node place, be necessary whether checking metastable state phenomenon causes logic error.The record of all data monitorings, judgement, mistake and statistics all completes in respective key node authentication unit.Verification system of the present invention and method are that SOC (system on a chip) anti-metastable state disturbance-proof design under the multi-clock zone condition of complexity provides a kind of checking means newly.
Above-mentioned embodiment is only concrete case of the present invention; scope of patent protection of the present invention includes but not limited to above-mentioned embodiment; any according to the invention a kind of based on metastable state inject cross clock domain logic ASIC verification system and method claims and the those of ordinary skill of any described technical field to its suitable change done or replacement, all should fall into scope of patent protection of the present invention.
Claims (3)
1., based on the cross clock domain logic ASIC verification system that metastable state is injected, it is characterized in that, its structure comprises:
Separate modularization design is in the cross clock domain logic of SOC (system on a chip);
Parametrization dispensing unit, realize the flexible configuration of the parameter to metastable state signal and synchronous logic, described parameter comprises: across shot clock cycle, the phase shift of clock signal, metastable state signal error threshold value, randomization, SYN register set up retention time, initiation parameter; The logical organization that this parametrization dispensing unit is integrated simultaneously carries out effective asynchronous signal and logical factor adjustment according to the parameter value of setting to cross clock domain logic;
ASIC logic analysis unit, by analyzing the propagation of cross clock domain signal in ASIC logic, determining the network node of easy occurrence logic mistake, it is classified as functional verification key node, realizing the logical tracing to cross clock domain logical signal;
Key node authentication unit, the key element of checking comprises modular excited data, the result, signal attribute, asserts, realizes the data monitoring to cross clock domain signal, outcome record;
Checking auxiliary file, associates parametrization dispensing unit, key node authentication unit with the cross clock domain logic realization of SOC (system on a chip), and for carrying out embedded authentication to cross clock domain logic.
2. a kind of cross clock domain logic ASIC verification system injected based on metastable state according to claim 1, is characterized in that, described ASIC verification system adopts SystemVerilog language to be made.
3. the cross clock domain logic ASIC verification method injected based on metastable state, it is characterized in that, its specific implementation process is: ASIC logic analysis unit submits to key node authentication unit the cross clock domain checking key node extracted from SOC (system on a chip), and this key node authentication unit validation signal is monitored; On verification platform, parametrization dispensing unit, key node authentication unit and each cross clock domain logic module in SOC (system on a chip) and corresponding key node associate, for functional simulation or Formal Verification is completed according to analyzing the checking auxiliary file produced; The function of parameter configuration, metastable state injection, data monitoring, judgement, mistake and statistics record is completed in whole proof procedure.
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| CN112131807A (en) * | 2020-09-18 | 2020-12-25 | 山东云海国创云计算装备产业创新中心有限公司 | Cross-clock domain verification method, device, equipment and medium |
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| CN112131807A (en) * | 2020-09-18 | 2020-12-25 | 山东云海国创云计算装备产业创新中心有限公司 | Cross-clock domain verification method, device, equipment and medium |
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