CN104618055B - A kind of data verification method and device based on SDH Transmission systems - Google Patents
A kind of data verification method and device based on SDH Transmission systems Download PDFInfo
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- CN104618055B CN104618055B CN201410852024.XA CN201410852024A CN104618055B CN 104618055 B CN104618055 B CN 104618055B CN 201410852024 A CN201410852024 A CN 201410852024A CN 104618055 B CN104618055 B CN 104618055B
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Abstract
The invention discloses a kind of data verification method and device based on SDH Transmission systems, the data verification method includes：Data frame is divided into i part, i >=3, wherein, the size of part 1 and i-th section is less than other parts；Data frame after segmentation is stored in asynchronous buffer device, wherein, it is asynchronous that the data frame of deposit asynchronous buffer device reads and writes clock in asynchronous buffer device, and bit wide is identical；Data frame in asynchronous buffer device is recombinated by pre-defined rule and the data frame after restructuring is verified.The present invention is 1 byte so as to solve data frame minimum interval by being split the data frame in SDH Transmission systems, being recombinated；Minimum frame length is smaller than Ethernet nearly 2 times, so as to cause CRC check circuit can not linear speed verification the problem of, realize and may apply to CRC check in SDH Transmission systems.
Description
Technical field
The present invention relates to data processing field, it particularly relates to a kind of data verification method based on SDH Transmission systems
And device.
Background technology
In high rate data communication system, due to meeting when data flow (including pay(useful) load and controlling stream) is transmitted on the line
Because of the interference of the extraneous factors such as ray, temperature, the data flow that generation recipient receives and the data flow that sender sends are inconsistent
Phenomenon.In order to ensure that recipient can recognize that the data flow of mistake and notify occur error code on sender's circuit, then need pair
Communication process carries out Error Control.
At present, the error control method used on the line has ARQ (automatic repeat request mode), FEC (forward error correction sides
Formula) and HEC (hybrid error correction), conventional is ARQ modes, and the Error Control of ARQ modes only needs error detection function to use letter
Folk prescription is just.
Wherein, CRC CRCs (Cyclic Redundancy Check) are the most frequently used in data communication field
A kind of error check code, it is characterized in that the length of information field and check field can be with arbitrarily selected.Due to its error monitoring
Ability is strong, and antijamming capability is excellent, is widely used in the Error Control of circuit.
Generate the general principle of CRC code：Any one code being made up of bit string can be with a coefficient only
Multinomial for ' 0 ' and ' 1 ' value corresponds.Such as：Multinomial corresponding to code 1010111 is x6+x4+x2+x+1, and
Multinomial is code 101111 corresponding to x5+x3+x2+x+1.
The principle of CRC code collection selection：If setting code word size as N, information field is K positions, and check field is R positions (N=K+
R), then any code word concentrated for CRC code, exists and only exists a R order polynomial g (x) so that：
V (x)=A (x) g (x)=xRm (x)+r (x)；
Wherein：M (x) is K-1 message polynomial, and r (x) is R-1 check polynomial,
G (x) is referred to as generator polynomial：
G (x)=g0+g1x1+g2x2+...+g (R-1) x (R-1)+gRxR
Sender produces CRC code word by specified g (x), and recipient then verifies the CRC code received by the g (x)
Word.
The CRC and its multinomial of some standards is listed below：
CRC-4：X4+X+1
CRC-12：x12+x11+x3+x+1
CRC-16：x16+x15+x2+1
CRC-ITU：x16+x12+x5+1
CRC-32：x32+x26+x23+...+x2+x+1
CRC-32c：x32+x28+x27+...+x8+x6+1
At present in ethernet networks, the data flow of transmission can be verified by CRC, but in SDH Transmission systems
In also without a kind of verification scheme of data flow.
In SDH Transmission systems, such as OC192-c systems, the frame (type such as PPP, HDLC) filled in C-4-64c containers
Length minimum length can be 24 bytes, but for relative Ethernet system, reduce 40 bytes, that is to say, that OC192-c
For 10G Ethernets, in the case that bit wide is consistent, frequency is consistent, the CRC cycles of each frame of OC192-c system checks
Number wants short nearly 2 times；On the other hand, ethernet frame is at intervals of average 12 bytes, that is to say, that between nth frame and N+1 frames
The interval in a cycle, and minimum 1 byte of OC192-c system frame periods, for CRC check in 64bit systems at least be present
For, it, which verifies verification of the interval compared to the CRC of Ethernet, will reduce nearly 2 cycles, and general CRC check module will at least deposit
In the initialization cycle of a cycle, if without initialization cycle, verification next frame then occurs checking circuit exception or gone out
The problem of wrong.
In summary, in SDH Transmission systems, linear speed CRC check circuit realizes that difficulty is larger, therefore there is presently no
A kind of verification scheme of data flow is applied in SDH Transmission systems.
The problem of in correlation technique, effective solution is not yet proposed at present.
The content of the invention
The problem of in correlation technique, the present invention propose a kind of data verification method and dress based on SDH Transmission systems
Put, can realize that the situation for raw error code of being miscarried in SDH Transmission systems to data verifies.
The technical proposal of the invention is realized in this way：
According to an aspect of the invention, there is provided a kind of data verification method based on SDH Transmission systems, this method bag
Include：
Data frame is divided into i part, i >=3, wherein, the size of part 1 and i-th section is less than other parts；
Data frame after segmentation is stored in asynchronous buffer device, wherein, the data frame of asynchronous buffer device is stored in asynchronous
It is asynchronous that clock is read and write in buffer storage, and bit wide is identical；
Data frame in asynchronous buffer device is recombinated by pre-defined rule and the data frame after restructuring is verified.
In addition, the SDH Transmission systems in the above method include：OC192-c systems, OC12-c systems, OC48-c systems,
OC768-c systems.
Wherein, the read-write clock ratio k1 of asynchronous buffer device is more than processing expense and compares k2；
Wherein, the ratio for writing end clock and reading end clock that clock ratio k1 is asynchronous buffer device is read and write；
Asynchronous buffer device writes ratio of the end clock for the line rate and the bit wide of SDH Transmission systems of SDH Transmission systems；
The processing expense of asynchronous buffer device than k2=(a+b)/N, wherein, a represent part 1 data frame size, b tables
Show the size of i-th section data frame, N represents the size of whole data frame.
Wherein, the data frame in asynchronous buffer device is recombinated by pre-defined rule, including：
The data frame being successively read after the segmentation stored in asynchronous buffer device；
The data frame after segmentation is spliced according to predetermined splicing size；
Zero filling processing is carried out to the last remaining data frame that can not splice composition predefined size.
Wherein, the data frame after restructuring is verified, including：
Data frame after restructuring is sent to calibration equipment；
Multiple check results are drawn according to the virtual value of the data frame after restructuring；
The output result of calibration equipment is compared with multiple check results, verification situation is determined according to comparative result.
According to another aspect of the present invention, there is provided a kind of data calibration device based on SDH Transmission systems, the device bag
Include：
Split module, for data frame to be divided into i part, i >=3, wherein, part 1 and i-th section it is big slight
In other parts；
Module is stored in, for the data frame after segmentation to be stored in into asynchronous buffer device, wherein, deposit asynchronous buffer device
It is asynchronous that data frame reads and writes clock in asynchronous buffer device, and bit wide is identical；
Recombination module, for the data frame in asynchronous buffer device to be recombinated by pre-defined rule；
Correction verification module, for being verified to the data frame after restructuring.
In addition, SDH Transmission systems can include：OC192-c systems, OC12-c systems, OC48-c systems, OC768-c systems
System.
Wherein, the read-write clock ratio k1 of asynchronous buffer device is more than processing expense and compares k2；
Wherein, the ratio for writing end clock and reading end clock that clock ratio k1 is asynchronous buffer device is read and write；
Asynchronous buffer device writes ratio of the end clock for the line rate and the bit wide of SDH Transmission systems of SDH Transmission systems；
The processing expense of asynchronous buffer device than k2=(a+b)/N, wherein, a represent part 1 data frame size, b tables
Show the size of i-th section data frame, N represents the size of whole data frame.
In addition, said apparatus can include：
Read module, for being successively read the data frame after the segmentation stored in asynchronous buffer device；
Concatenation module, for being spliced the data frame after segmentation according to predetermined splicing size；
Processing module, for carrying out zero filling processing to the last remaining data frame that can not splice composition predefined size.
Wherein, said apparatus can also include：
Sending module, for the data frame after restructuring to be sent to calibration equipment；
Result-generation module, for drawing multiple check results according to the virtual value of the data frame after restructuring；
Comparison module, it is true according to comparative result for the output result of calibration equipment to be compared with multiple check results
Surely situation is verified.
The present invention by the data frame in SDH Transmission systems by being split, being recombinated, so as to solve between data frame minimum
It is divided into 1 byte；Minimum frame length is smaller than Ethernet nearly 2 times, so as to cause CRC check circuit can not linear speed verification the problem of, it is real
Show and may apply to CRC check in SDH Transmission systems, the data flow to be transmitted in SDH Transmission systems provides one kind can
The verification scheme leaned on, substantially increase the security and reliability of transmission data.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to institute in embodiment
The accompanying drawing needed to use is briefly described, it should be apparent that, drawings in the following description are only some implementations of the present invention
Example, for those of ordinary skill in the art, on the premise of not paying creative work, can also be obtained according to these accompanying drawings
Obtain other accompanying drawings.
Fig. 1 is the flow chart of the data verification method according to embodiments of the present invention based on SDH Transmission systems；
Fig. 2 is the structural representation according to the asynchronous buffer device of a specific embodiment of the invention；
Fig. 3 is the schematic diagram according to the sequential of the reading asynchronous buffer device of a specific embodiment of the invention；
Fig. 4 is the block diagram of the data calibration device according to embodiments of the present invention based on SDH Transmission systems.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, the every other embodiment that those of ordinary skill in the art are obtained, belong to what the present invention protected
Scope.
According to an embodiment of the invention, there is provided a kind of data verification method based on SDH Transmission systems, can realize
The situation of the raw error code of data miscarriage is verified in SDH Transmission systems.
SDH Transmission systems in the present invention can be OC192-c systems, OC12-c systems, OC48-c systems, OC768-c
System.
As shown in figure 1, the data verification method based on SDH Transmission systems according to embodiments of the present invention, including：
Step S101, data frame is divided into i part, i >=3, wherein, the size of part 1 and i-th section is less than it
His part；
Step S103, the data frame after segmentation is stored in asynchronous buffer device, wherein, the data of deposit asynchronous buffer device
It is asynchronous that frame reads and writes clock in asynchronous buffer device, and bit wide is identical；
Step S105, the data frame in asynchronous buffer device is recombinated by pre-defined rule and to the data frame after restructuring
Verified.
Wherein, the read-write clock ratio k1 of asynchronous buffer device is more than processing expense and compares k2；
Read-write clock ratio k1 is the ratio for writing end clock and reading end clock of asynchronous buffer device；
Asynchronous buffer device writes ratio of the end clock for the line rate and the bit wide of SDH Transmission systems of SDH Transmission systems；
The processing expense of asynchronous buffer device than k2=(a+b)/N, wherein, a represent part 1 data frame size, b tables
Show the size of i-th section data frame, N represents the size of whole data frame.
Wherein, the data frame in asynchronous buffer device is recombinated by pre-defined rule, including：
The data frame being successively read after the segmentation stored in asynchronous buffer device；
The data frame after segmentation is spliced according to predetermined splicing size；
Zero filling processing is carried out to the last remaining data frame that can not splice composition predefined size.
Wherein, the data frame after restructuring is verified, including：
Data frame after restructuring is sent to calibration equipment；
Multiple check results are drawn according to the virtual value of the data frame after restructuring；
The output result of calibration equipment is compared with multiple check results, verification situation is determined according to comparative result.
In a specific embodiment, SDH Transmission systems are OC192-c systems, and the present invention can be based on any compile
The hardware platform of journey, such as FPGA.The description below is to realize that CRC check circuit verifies to data stream in OC192-c systems
Process：
Each frame is divided into by 3 parts by frame separator first：4 words after 4 byte before frame, center section and frame
Section, then will be per asynchronous buffer buffer storages be partly input to, and asynchronous buffer buffer storages as shown in Fig. 2 enter again afterwards
The lower step processing of row.
The effect of frame separator is that solve frame and minimum 1 byte of frame period in OC192-c systems, gives CRC check electricity
Road bring can not linear speed verification the problem of because general CRC check module at least needs to exist the initialization week of a cycle
Phase, if without initialization cycle, checking circuit exception or the feelings of check results error occur when verifying next frame
Condition.
It is stored in that the read-write clock of every part of asynchronous buffer buffer storages is asynchronous, and bit wide is consistent, but asynchronous buffer delays
Depth in cryopreservation device per part is had any different, and is calculated by minimum frame 24bytes, wherein the buffer of asynchronous buffer buffer storages
Head and buffer Tail depth is the 1/24 of buffer Data；The clock of all parts requires, and writes end
Clock is：(OC192-c line rate 9.952Gbps)/system bit wide 64bit is 155.5Mhz, and reading end clock needs higher than when writing
Clock, the FPGA currently used for communications field OC192-c systems can reach the clock frequency of more than 500Mhz between register, and this is
It is 300Mhz that clock is read in system design, and in the case of parcel 24bytes, handling expense ratio is：
(4+4)/24=1/3
And read and write clock ratio and be：
155.5/300>0.5>1/3
So the read-write clock of asynchronous buffer buffer storages can meet the bandwidth at asynchronous buffer buffer storages both ends
Matching.
The purpose of frame reconstruction unit be from asynchronous buffer buffer storages read buffer Head, buffer Tail and
Buffer Data three parts data, reading sequential has strict demand, and reading sequential is shown in Figure 3, in order to which whole frame is sent into
To CRC check device, frame intermediate data part is read from 4 bytes, next cycle before buffer Head reading frames first, finally
One cycle read 4 bytes after frame.
After the data for reading each asynchronous buffer buffer storages, frame reconstruction unit needs 3 kinds of asynchronous buffer to more than
The data of buffer storage are spliced, and each frame, except frame, last cycle data carries out 8bytes alignment operations, period 1
8bytes concatenations are carried out for 4bytes buffer Head data and the buffer Data data of 4 bytes；Intermediate data
Splice for 4bytes of upper cycle and this cycle 4bytes data, by that analogy, last cycle data also produces for splicing, to most
The remaining data frame that can not realize alignment splicing also needs to progress one and fills out " 0 " operation afterwards.
In addition, the CRC types of Ethernet only have CRC32 a kind of, when realizing checking circuit, it is only necessary to judge regular length
, but in OC192-c systems, two kinds of CRC types be present：CRC16 and CRC32, for Ethernet, it is verified
When then need to switch between two kinds of circuits, and to carry out variable length verification, frame length also has two kinds.
In order to realize that CRC32 and CRC16 circuits coexist, the data frame stream after restructuring is sent to CRC32 by the present invention simultaneously
In the DataValid registers of a 2bit in CRC16 and CRC check device, using MagicNum methods, further according to
DataValid values, produce two 8 and select 1 circuit, i.e. 16 check results, by the result of CRC32 and CRC16 circuit outputs and 16
Individual check results compare, if one value of any of which matches with this 16 check results, it is just to illustrate current frame check
True, if the result of CRC32 and CRC16 circuit outputs is not wherein, it is wrong to illustrate current frame check.
According to an embodiment of the invention, a kind of data calibration device based on SDH Transmission systems, above-mentioned SDH are additionally provided
Transmission system can include：OC192-c systems, OC12-c systems, OC48-c systems, OC768-c systems.
As shown in figure 4, the device includes：
Split module 41, for data frame to be divided into i part, i >=3, wherein, the size of part 1 and i-th section
Less than other parts；
Module 42 is stored in, for the data frame after segmentation to be stored in into asynchronous buffer device, wherein, it is stored in asynchronous buffer device
Data frame to read and write clock in asynchronous buffer device asynchronous, and bit wide is identical；
Recombination module 43, for the data frame in asynchronous buffer device to be recombinated by pre-defined rule；
Correction verification module 44, for being verified to the data frame after restructuring.
Wherein, the read-write clock ratio k1 of asynchronous buffer device is more than processing expense and compares k2；
Read-write clock ratio k1 is the ratio for writing end clock and reading end clock of asynchronous buffer device；
Asynchronous buffer device writes ratio of the end clock for the line rate and the bit wide of SDH Transmission systems of SDH Transmission systems；
The processing expense of asynchronous buffer device than k2=(a+b)/N, wherein, a represent part 1 data frame size, b tables
Show the size of i-th section data frame, N represents the size of whole data frame.
In addition, said apparatus can include：
Read module (not shown), for being successively read the data frame after the segmentation stored in asynchronous buffer device；
Concatenation module (not shown), for being spliced the data frame after segmentation according to predetermined splicing size；
Processing module (not shown), for carrying out zero filling to the last remaining data frame that can not splice composition predefined size
Processing.
Wherein, said apparatus can also include：
Sending module (not shown), for the data frame after restructuring to be sent to calibration equipment；
Result-generation module (not shown), for drawing multiple check results according to the virtual value of the data frame after restructuring；
Comparison module (not shown), for the output result of calibration equipment to be compared with multiple check results, according to than
Relatively result determines verification situation.
In summary, by means of the above-mentioned technical proposal of the present invention, by the way that the data frame in SDH Transmission systems is divided
Cut, be then passed in asynchronous buffer device, and the read-write clock ratio of the asynchronous buffer device is more than processing expense ratio, and according to
Timing requirements are read out to the data frame after splitting in asynchronous buffer device, according still further to predefined size to the data frame after segmentation
Splicing restructuring is carried out, so as to overcome minimum 1 byte of frame period in SDH Transmission systems, minimum frame length is smaller than Ethernet by nearly 2
Times so as to CRC check circuit bring can not linear speed verification the problem of；Data frame stream after restructuring is sent to SDH simultaneously to pass
CRC32 and CRC16 in defeated system, and according to MagicNum and DataValid values so as to judge the correctness of current frame check,
And then CRC32 and CRC16 coexisting in SDH Transmission systems are realized, CRC check may apply in SDH Transmission systems,
Data flow to be transmitted in SDH Transmission systems provides a kind of reliable verification scheme, substantially increases the safety of transmission data
Property and reliability.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
God any modification, equivalent substitution and improvements made etc., should be included in the scope of the protection with principle.
Claims (8)
- A kind of 1. data verification method based on SDH Transmission systems, it is characterised in that including：Data frame is divided into i part, i >=3, wherein, the size of part 1 and i-th section is less than other parts；Data frame after segmentation is stored in asynchronous buffer device, wherein, the data frame of the asynchronous buffer device is stored in described It is asynchronous that clock is read and write in asynchronous buffer device, and bit wide is identical；Data frame in the asynchronous buffer device is recombinated by pre-defined rule and the data frame after restructuring is verified；Wherein, the data frame in the asynchronous buffer device is recombinated by pre-defined rule, including：The data frame being successively read after the segmentation stored in the asynchronous buffer device；The data frame after segmentation is spliced according to predetermined splicing size；Zero filling processing is carried out to the last remaining data frame that can not splice composition predefined size.
- 2. methods described according to claim 1, it is characterised in that the SDH Transmission systems include：OC192-c systems, OC12-c systems, OC48-c systems, OC768-c systems.
- 3. methods described according to claim 1, it is characterised in that the read-write clock ratio k1 of the asynchronous buffer device is more than place Reason expense compares k2；Wherein, the read-write clock ratio k1 is the ratio for writing end clock and reading end clock of the asynchronous buffer device；The asynchronous buffer device writes end clock as the line rate of the SDH Transmission systems and the position of the SDH Transmission systems Wide ratio；The processing expense of the asynchronous buffer device than k2=(a+b)/N, wherein, a represent part 1 data frame size, b tables Show the size of i-th section data frame, N represents the size of whole data frame.
- 4. methods described according to claim 1, it is characterised in that the data frame after restructuring is verified, including：Data frame after restructuring is sent to calibration equipment；Multiple check results are drawn according to the virtual value of the data frame after the restructuring；The output result of the calibration equipment is compared with the multiple check results, verification feelings are determined according to comparative result Condition.
- A kind of 5. data calibration device based on SDH Transmission systems, it is characterised in that including：Split module, for data frame to be divided into i part, i >=3, wherein, the size of part 1 and i-th section is less than it His part；Module is stored in, for the data frame after segmentation to be stored in into asynchronous buffer device, wherein, it is stored in the asynchronous buffer device It is asynchronous that data frame reads and writes clock in the asynchronous buffer device, and bit wide is identical；Recombination module, for the data frame in the asynchronous buffer device to be recombinated by pre-defined rule；Correction verification module, for being verified to the data frame after restructuring；Wherein, read module, for being successively read the data frame after the segmentation stored in the asynchronous buffer device；Concatenation module, for being spliced the data frame after segmentation according to predetermined splicing size；Processing module, for carrying out zero filling processing to the last remaining data frame that can not splice composition predefined size.
- 6. described device according to claim 5, it is characterised in that the SDH Transmission systems include：OC192-c systems, OC12-c systems, OC48-c systems, OC768-c systems.
- 7. described device according to claim 5, it is characterised in that the read-write clock ratio k1 of the asynchronous buffer device is more than place Reason expense compares k2；Wherein, the read-write clock ratio k1 is the ratio for writing end clock and reading end clock of the asynchronous buffer device；The asynchronous buffer device writes end clock as the line rate of the SDH Transmission systems and the position of the SDH Transmission systems Wide ratio；The processing expense of the asynchronous buffer device than k2=(a+b)/N, wherein, a represent part 1 data frame size, b tables Show the size of i-th section data frame, N represents the size of whole data frame.
- 8. described device according to claim 5, it is characterised in that including：Sending module, for the data frame after restructuring to be sent to calibration equipment；Result-generation module, for drawing multiple check results according to the virtual value of the data frame after the restructuring；Comparison module, for the output result of the calibration equipment to be compared with the multiple check results, tied according to comparing Fruit determines verification situation.
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| CN1431594A (en) * | 2003-01-27 | 2003-07-23 | 西安电子科技大学 | Method for parallel computing code of CRC in multiple channels and multiple bits |
| CN1859397A (en) * | 2006-03-03 | 2006-11-08 | 华为技术有限公司 | Data transmission method in mobile communication network |
| CN101488834A (en) * | 2009-01-20 | 2009-07-22 | 重庆邮电大学 | 3G link recognition recombinant processing system and method based on FPGA |
| CN101834664A (en) * | 2010-04-29 | 2010-09-15 | 西安电子科技大学 | SDH (Synchronous Digital Hierarchy) multi-domain comprehensive test device and test method thereof |
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| US7472231B1 (en) * | 2001-09-07 | 2008-12-30 | Netapp, Inc. | Storage area network data cache |
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|---|---|---|---|---|
| CN1431594A (en) * | 2003-01-27 | 2003-07-23 | 西安电子科技大学 | Method for parallel computing code of CRC in multiple channels and multiple bits |
| CN1859397A (en) * | 2006-03-03 | 2006-11-08 | 华为技术有限公司 | Data transmission method in mobile communication network |
| CN101488834A (en) * | 2009-01-20 | 2009-07-22 | 重庆邮电大学 | 3G link recognition recombinant processing system and method based on FPGA |
| CN101834664A (en) * | 2010-04-29 | 2010-09-15 | 西安电子科技大学 | SDH (Synchronous Digital Hierarchy) multi-domain comprehensive test device and test method thereof |
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