CN104617047B - Transistor and preparation method thereof - Google Patents
Transistor and preparation method thereof Download PDFInfo
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- CN104617047B CN104617047B CN201310543037.4A CN201310543037A CN104617047B CN 104617047 B CN104617047 B CN 104617047B CN 201310543037 A CN201310543037 A CN 201310543037A CN 104617047 B CN104617047 B CN 104617047B
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- 238000002360 preparation method Methods 0.000 title description 5
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 claims abstract description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 14
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 9
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 7
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- -1 carbon ion Chemical class 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 description 6
- 229910044991 metal oxide Inorganic materials 0.000 description 5
- 150000004706 metal oxides Chemical class 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000006835 compression Effects 0.000 description 4
- 238000007906 compression Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000053 physical method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Abstract
A kind of production method of transistor, including：Substrate is provided, forms the first pseudo- grid and the first side wall on substrate；Form first groove；The first stressor layers are formed in first groove；The first side wall is removed, the second side wall is formed in the side wall of the first pseudo- grid；The second pseudo- grid are formed in the first stressor layers；Expose the substrate between the first stressor layers；The second stressor layers are formed in substrate between the first stressor layers.The present invention also provides a kind of transistors, including substrate, the first stressor layers, the second stressor layers, the source region for being formed in the second stressor layers or drain region and grid, side wall on substrate.The present invention has the following advantages：By forming the first stressor layers around the second stressor layers for being used as transistor source region or drain region, and keep the stress direction of the first stressor layers opposite with the second stressor layers, increase the stress intensity of channel region in the transistor, and then promotes the electron mobility of transistor.
Description
Technical field
The present invention relates to field of semiconductor manufacture, and in particular to a kind of transistor and preparation method thereof.
Background technology
Metal oxide semiconductor device（Complementary Metal Oxide Semiconductor,CMOS）'s
Performance mainly can be by improving the gate capacitance of CMOS, improving carrier mobility or and three kinds of ways of reduction device channel length
Diameter is promoted.Traditional method for improving is all that the thickness of reduction channel length and gate dielectric layer, this method are referred to as crystal
The size reduction method of pipe.However the today reduced in cmos device size, simple minification by physics limit and are set
Device can not be made to reach estimated performance for the limitation of cost, improve channel carrier mobility as device work is further increased
Make one of the main path of speed.
Strained silicon technology can be applied in cmos device, to improve the performance of the metal oxide semiconductor device formed,
It is stretched through physical method or compresses silicon crystal lattice to reach the mobility for improving carrier in cmos device, improved with reaching
The purpose of cmos device performance.
For example, applying tensile stress (Tensile in the channel region of N-type metal-oxide semiconductor (MOS) (NMOS) device
Stress), the electron mobility in the NMOS device can be improved.Similarly, in P type metal oxide semiconductor (PMOS) device
Apply compression (Compressive stress) in channel region, the mobility in hole in PMOS device also can be improved.
At this point, how to further increase the stress of channel region in cmos device, becomes those skilled in the art and urgently solve
Certainly the problem of.
Invention content
Problems solved by the invention is to provide a kind of transistor and preparation method thereof, to improve the current-carrying of transistor channel region
Transport factor, and then optimize the performance of transistor.
To solve the above problems, the present invention provides a kind of production method of transistor, including：
Substrate is provided,
The first pseudo- grid and the first side wall on the described first pseudo- grid side wall are formed over the substrate；
Using first side wall as mask, first groove is formed in the substrate of the described first pseudo- grid both sides respectively；
It is respectively formed the first stressor layers in the first groove of the described first pseudo- grid both sides；
First side wall is removed, and the second side wall is formed in the side wall of the described first pseudo- grid；
The second pseudo- grid are formed in first stressor layers that second side wall exposes；
The described first pseudo- grid are removed, part of the substrate between the first stressor layers is exposed；
The second stressor layers are formed in part of the substrate between the first stressor layers, what second stressor layers provided
Stress is opposite with the stress types that first stressor layers provide；
Source region or drain region are formed in second stressor layers.
Optionally, in the step of providing substrate, the substrate is silicon substrate.
Optionally, in the step of forming the first pseudo- grid, the described first pseudo- grid are using silicon as material.
Optionally, in the step of forming the first side wall, first side wall is silicon nitride spacer or monox lateral wall.
Optionally, in the step of forming first groove, the first groove is ∑ type groove.
Optionally, the ∑ type groove is formed using dry etching and wet etching.
Optionally, the wet etching uses tetramethylammonium hydroxide as etchant.
Optionally, in the step of forming the first stressor layers, described first is formed by the way of selective epitaxial growth
Stressor layers.
Optionally, in the step of forming the second side wall, second side wall is silicon nitride or monox lateral wall.
Optionally, in the step of forming the second pseudo- grid, the described second pseudo- grid are using silicon as material.
Optionally, in the step of forming the second pseudo- grid, it is pseudo- that described second is formed by the way of selective epitaxial growth
Grid.
Optionally, in the step of removing the first pseudo- grid, using the described first pseudo- grid of method removal of selective etch.
Optionally, the step of the second stressor layers of formation include：
Part of the substrate between the first stressor layers is removed, to form second groove；
Second stressor layers are formed in the second groove.
Optionally, the substrate is removed using the method for selective etch.
Optionally, in the step of forming the second stressor layers, described second is formed by the way of selective epitaxial growth
Stressor layers.
Optionally, the step of the second stress of formation includes：
Ion doping is carried out to part of the substrate between the first stressor layers, to form doped region in the substrate,
The doped region is second stressor layers.
Optionally, the transistor is NMOS, and the substrate is silicon substrate, ion doping is carried out using carbon ion, with shape
At the second stressor layers of carbofrax material.
Optionally, in the step of forming the first stressor layers, first stressor layers are germanium silicon stressor layers；Forming second
In the step of stressor layers, second stressor layers are silicon carbide stressor layers.
In addition, the present invention also provides a kind of transistors, including：
Substrate；
At least two first stressor layers being respectively arranged in the substrate；
The second stressor layers between first stressor layers, the stress and described first that second stressor layers provide
The stress types that stressor layers provide are opposite；
It is formed in source region or the drain region of second stressor layers；
Gate structure on the substrate, the gate structure are corresponding with the position of the first stressor layers.
Optionally, first stressor layers are germanium silicon stressor layers, and second stressor layers are silicon carbide stressor layers.
Compared with prior art, technical scheme of the present invention has the following advantages：
By forming the first stressor layers in the channel region in transistor, and second is formed at source region or drain region position
Stressor layers, and keep the stress of the second stressor layers similar with the stress of the first stressor layers on the contrary, first stressor layers and second are answered
Power layer is combined the stress that can increase channel region in the transistor, and then promotes the carrier mobility of transistor.
Further, the ∑ type groove can preferably be formed using dry etching and wet etching.
Further, more uniform first stressor layers can be formed by the way of selective epitaxial growth.
Further, the doped region for being used to form second stressor layers is formed by the way of ion doping, it can be direct
Second stressor layers are formed, reduce making step to a certain extent.
Description of the drawings
Fig. 1 is the flow diagram of one embodiment of production method of transistor of the present invention.
Fig. 2 to Fig. 6 is the structural schematic diagram of each step transistor in Fig. 1.
Fig. 7 is the structural schematic diagram of one embodiment of transistor of the present invention.
Specific implementation mode
Present invention firstly provides a kind of production methods of transistor, by being used as the first stress of source region or drain region setting
Second stressor layers opposite with the stress types of the first stressor layers are arranged in channel region, are answered by the first stressor layers and second for layer
Power layer is combined, and is increased to transistor channel region stress, and then improves the mobility of channel region carrier, optimizes transistor
Performance.
With reference to figure 1, show preparation method of transistor of the present invention embodiment one flow diagram.The present embodiment one with
For NMOS device, the method for making NMOS device includes：
Step S1, provides substrate；
Step S2 forms the first pseudo- grid and the first side wall on the described first pseudo- grid side wall over the substrate；
Step S3 forms the first ditch in the substrate of the described first pseudo- grid both sides respectively using first side wall as mask
Slot；
Step S4 is respectively formed the first stressor layers in the first groove of the described first pseudo- grid both sides；
Step S5 removes first side wall, and forms the second side wall in the side wall of the described first pseudo- grid；
Step S6 forms the second pseudo- grid in first stressor layers that second side wall exposes；
Step S7, the described first pseudo- grid of removal, exposes part of the substrate between the first stressor layers；
Step S8 removes part of the substrate between the first stressor layers, to form second groove；
Step S9, forms second stressor layers in the second groove, the stress that second stressor layers provide with
The stress types that first stressor layers provide are opposite；
Step S10 forms source region or drain region in second stressor layers.
Through the above steps, first groove is defined by the first pseudo- grid of setting, and forms in the first groove the
One stressor layers, first stressor layers are located at the channel region position of transistor；Then institute is defined by the described second pseudo- grid
Second groove is stated, and forms second stressor layers opposite with the first groove stress types in the second groove, it is described
Second stressor layers are located at the source region of transistor and the position in drain region, and being combined by the first stressor layers and the second stressor layers can be with
Increase the stress of transistor channel region, and then increases the electron mobility of NMOS device.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment one be described in detail.
With reference to figure 2, step S1 is executed, substrate 100 is provided；
In the present embodiment, the substrate 100 is silicon substrate.But the invention is not limited in this regard, it can also be used
The substrate of its material.
Step S2 is continued to execute, forms the first pseudo- grid on the substrate 100（Dummy Gate）110 and positioned at described the
The first side wall 111 on one 110 side wall of pseudo- grid.
In the present embodiment, the described first pseudo- grid 110 use silicon identical with the substrate 100 as material, such
It is advantageous in that, in subsequent steps, can disposably remove the described first pseudo- grid 110 and section substrate 100.
First side wall 111 is for the mask layer in subsequent steps as the first pseudo- grid 110.
In the present embodiment, first side wall 111 is using silicon nitride as material, and still, the present invention does not limit this
It is fixed, other materials can also be used（Such as silica, the other oxides or nitride of silicon）As first side wall 111
Material, this is not limited by the present invention.
With reference to figure 3, step S3 is executed, is mask with first side wall 111, respectively in the described first 110 both sides of pseudo- grid
Substrate 100 in form first groove 101a and 101b.
The first groove 101a and 101b for forming first stressor layers in subsequent steps.
Since this first embodiment is by taking NMOS device as an example, in the present embodiment, the first groove 101a and 101b
For ∑ type groove.
In the present embodiment, formed the ∑ type groove further include it is following step by step：
Step S31 forms arc-shaped groove by dry etching in the substrate 100；
Step S32 is handled the arc-shaped groove by wet etching, to form the ∑ type groove（First
Groove 101a and 101b）.
In the present embodiment, using tetramethylammonium hydroxide（TMAH）As etchant, still, the present invention does not appoint this
What is limited.
It is that this field makes ∑ type groove step by step above（First groove 101a and 101b）Common method, the present invention
This is not repeated.
Referring to Fig. 4, step S4 is executed, in the first groove 101a and 101b of the described first 110 both sides of pseudo- grid respectively
Form the first stressor layers 102a and 102b.
Due to the first groove 101a and 101b be ∑ type groove, institute so, described in the present embodiment first answers
Power layer 102a and 102b are the germanium silicon for generating compression（SiGe）Stressor layers.
In the present embodiment, the first stressor layers 102a and 102b are formed by the way of selective epitaxial growth,
Ideal germanium silicon stressor layers can be formed in this way.
It should be noted that the present invention does not limit this, the germanium silicon stressor layers can also be formed using other modes.
With continued reference to Fig. 4, step S5 is executed, removes first side wall 111, and in the side wall of the described first pseudo- grid 110
Form the second side wall 112.
Due to mask layer of first side wall 111 in step S3 before as the first pseudo- grid 110, first side
The edge of wall 111 is by certain damage（As shown in dashed circle in Fig. 3）, it is unfavorable in subsequent step as described in formation
The mask of second pseudo- grid, so, first side wall 111 is removed, and form shape in the side wall of the described first pseudo- grid 110 again
The second side wall 112 that more complete, surface is flushed with the surface of the first pseudo- grid 110, in order to the shape of the subsequent second pseudo- grid
At.
In the present embodiment, this step S5 include it is following step by step：
Step S51 removes first side wall 111；
Step S52, the blanket dielectric layer on the described first pseudo- grid 110, and cover mask layer on the dielectric layer；
Step S53, the graphical mask layer, loses using patterned mask layer as mask and to the dielectric layer
It carves, to form second side wall 112.
Since patterned mask layer plays preferable protective effect, thus the second side wall 112 formed to dielectric layer
Top edge at will not form fillet, to form that side wall is substantially perpendicular with substrate 100 and top surface is substantially with first
The second side wall 112 that the surface of pseudo- grid 110 is flush.
It is only the method employed in the present embodiment step by step above, how the present invention is for remove first side wall
111 and formed the second side wall 112 be not limited in any way.
In addition, in the present embodiment, second side wall 112 is using silicon nitride as material.But the present invention to this not
It is restricted, other materials can also be used（Such as silica, the other oxides or nitride of silicon）As the second side
The material of wall 112.
With continued reference to Fig. 4, execute step S6, be mask with second side wall 112, the first stressor layers 102a with
And the second pseudo- grid 120 are formed on 102b.
It is a surface and the first pseudo- grid 110 since 112 edge of the second side wall formed in step S5 is not damaged
The side wall that surface flushes, therefore the second side wall 112 surrounds more vertical opening with substrate 100.In the present embodiment, with described
Second side wall 112 is used as growth mask, forms the described second pseudo- grid 120 in the opening by way of selective epitaxial growth,
The second ideal puppet grid 120 can be formed.
Described second pseudo- grid 120 use silicon as material, but the present invention is not limited this.
With reference to figure 5, execute step S7, the described first pseudo- grid 110 of removal, expose substrate 100 the first stressor layers 102a with
And the part between 102b.
In the present embodiment, the described first pseudo- grid 110 are removed by the way of selective etch, to reduce to peripheral devices
Influence.
In the present embodiment, it before etching the described first pseudo- grid 110, also covers and covers above the described second pseudo- grid 120
Mould, to prevent the second pseudo- grid 120 described in etching process to be affected.
With continued reference to Fig. 5, step S8 is executed, part of the substrate 100 between the first stressor layers is removed, to form the
Two grooves 103.The second groove 103 is used to form second stressor layers.（This Fig. 5 only depicts the first stressor layers 102a
And the second groove 103 between 102b）
In the present embodiment, the section substrate 100 is removed using the method for selective etch, to reduce to second groove
The influence of first stressor layers 102a and 102b of 103 both sides.
Since the first groove 101a and 101b where the first stressor layers 102a and 102b are ∑ type groove, institute
With the shape of the second groove 103 be with first groove 101a and 101b shown in Fig. 5 at mirror-symmetrical " anti-∑ type
Groove ".
It should be noted that the present invention is not limited the parameters such as specific etchant and etching ratio, but according to reality
Border situation makes corresponding adjustment.
With reference to figure 6, step S9 is executed, forms second stressor layers 104 in the second groove 103, described second
The stress that stressor layers 104 provide is opposite with the stress types that the first stressor layers 102a and 102b are provided.
In the present embodiment, since device to be formed is NMOS device, the first stressor layers 102a and 102b are
The germanium silicon stressor layers of compression are generated, correspondingly, second stressor layers 104 are to generate the silicon carbide of tensile stress（SiC）Stress
Layer.
Step S10 is executed, forms source region or drain region in second stressor layers 104.
The production method of transistor of the present invention further includes：The pseudo- grid 120 of removal second, the shape at the position of the second pseudo- grid 120
At metal gates.Same as the prior art, details are not described herein.
Second stressor layers 104 are used to form the source region of NMOS device or drain region in the present embodiment, at this point, described
The substrate of one positions stressor layers 102a and 102b is used to form grid, therefore, the first stressor layers 102a（102b）
Positioned at the channel region of the NMOS device.The stress and the first stressor layers 102a and 102b generated due to the second stressor layers 104
The stress types of generation under the collective effect of the first stressor layers 102a and the second stressor layers 104 on the contrary, can be improved NMOS device
Channel region tensile stress, and then the electron mobility of the channel region of the NMOS device is made to get a promotion.
In addition, the present invention also provides another embodiments two：
The step S1 of the present embodiment is identical as embodiment one to step S7.With reference to figure 6, the present embodiment two and above-described embodiment
One difference lies in：
In the step of forming the second stressor layers, after the described first pseudo- grid 110 of removal, using the method for ion doping,
Doped region is formed in part between substrate the first stressor layers 102a and 102b, is used to form second stressor layers 104.
In the present embodiment, since the first the stressor layers 102a and 102b formed in before the step of is germanium silicon stress
Layer, in order to make the second stressor layers 104 to be formed for providing the stress different from the first stressor layers 102a and 102b, using carbon
As Doped ions, to form the second stressor layers 104 of carbofrax material.
It should be noted that the present invention does not limit doping method.
In addition, referring to Fig. 7, the present invention also provides a kind of transistors, including：
Substrate 200；
At least two first stressor layers 202a and 202b being respectively arranged in the substrate 200；
The second stressor layers 204 between the first stressor layers 202a and 202b, second stressor layers 104 carry
The stress types of confession are opposite with the stress types that the first stressor layers 202a and 202b are provided；
It is formed in source region or the drain region of second stressor layers 204；
Gate structure 220 on the substrate 200, the gate structure 220 and the first stressor layers 202a with
And the position of 202b is corresponding；Wherein, the gate structure 220 includes：High-k dielectric layer on substrate 200 is located at high k
Metal gates on dielectric layer（It is not marked in figure）With the side wall 212 in high-k dielectric layer and metal gates side wall.
It should be noted that the shape of the side wall 212 is more complete, the table on the surface and gate structure 220 of side wall 212
Face flushes.
In the present embodiment by taking NMOS device as an example, the first stressor layers 202a and 202b are germanium silicon stressor layers, institute
It is silicon carbide stressor layers to state the second stressor layers 204.
The stress types phase provided with the second stressor layers 204 by the first stressor layers 202a and 202b stress provided
Instead, the first stressor layers 202a and 202b and the second stressor layers 204 are big to the total stress of the channel region generation of NMOS device
It is small to there is a degree of increase, the electron mobility in the channel region of the NMOS device to obtain compared to existing NMOS device
To promotion.
It should be noted that the transistor arrangement can be, but not limited to obtain using above-mentioned production method.
It should also be noted that, above-described embodiment is illustrated by taking NMOS device as an example, but the present invention does not limit this
System, in other embodiments, the transistor can also be PMOS device, correspondingly, substrate is silicon, be located at the of channel region
One stressor layers are silicon carbide, and it is SiGe to be located at the second stressor layers at source region or drain region position.First stressor layers and second
Stressor layers are combined the compression size for improving PMOS device channel region, and those skilled in the art can be according to above-described embodiment
The present invention change, replace and deform accordingly.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (18)
1. a kind of production method of transistor, which is characterized in that including：
Substrate is provided,
The first pseudo- grid and the first side wall on the described first pseudo- grid side wall are formed over the substrate；
Using first side wall as mask, first groove is formed in the substrate of the described first pseudo- grid both sides respectively；
It is respectively formed the first stressor layers in the first groove of the described first pseudo- grid both sides；
First side wall is removed, and the second side wall is formed in the side wall of the described first pseudo- grid；
The second pseudo- grid are formed in first stressor layers that second side wall exposes；
The described first pseudo- grid are removed, part of the substrate between the first stressor layers is exposed；
The second stressor layers, the stress that second stressor layers provide are formed in part of the substrate between the first stressor layers
It is opposite with the stress types that first stressor layers provide；
Source region or drain region are formed in second stressor layers.
2. production method as described in claim 1, which is characterized in that in the step of providing substrate, the substrate serves as a contrast for silicon
Bottom.
3. production method as described in claim 1, which is characterized in that in the step of forming the first pseudo- grid, described first is pseudo-
Grid are using silicon as material.
4. production method as described in claim 1, which is characterized in that in the step of forming the first side wall, first side
Wall is silicon nitride spacer or monox lateral wall.
5. production method as described in claim 1, which is characterized in that in the step of forming first groove, first ditch
Slot is ∑ type groove.
6. production method as claimed in claim 5, which is characterized in that form the ∑ using dry etching and wet etching
Type groove.
7. production method as claimed in claim 6, which is characterized in that the wet etching uses tetramethylammonium hydroxide conduct
Etchant.
8. production method as described in claim 1, which is characterized in that in the step of forming the first stressor layers, using selection
The mode of property epitaxial growth forms first stressor layers.
9. production method as described in claim 1, which is characterized in that in the step of forming the second side wall, the second side
Wall is silicon nitride or monox lateral wall.
10. production method as described in claim 1, which is characterized in that in the step of forming the second pseudo- grid, described second is pseudo-
Grid are using silicon as material.
11. production method as described in claim 1, which is characterized in that in the step of forming the second pseudo- grid, using selectivity
The mode of epitaxial growth forms the described second pseudo- grid.
12. production method as described in claim 1, which is characterized in that in the step of removing the first pseudo- grid, using selectivity
The described first pseudo- grid of method removal of etching.
13. production method as described in claim 1, which is characterized in that formed the second stressor layers the step of include：Described in removal
Part of the substrate between the first stressor layers, to form second groove；
Second stressor layers are formed in the second groove.
14. production method as claimed in claim 13, which is characterized in that remove the lining using the method for selective etch
Bottom.
15. production method as claimed in claim 13, which is characterized in that in the step of forming the second stressor layers, using choosing
The mode of selecting property epitaxial growth forms second stressor layers.
16. production method as described in claim 1, which is characterized in that formed the second stress the step of include：To the substrate
Part between the first stressor layers carries out ion doping, and to form doped region in the substrate, the doped region is described
Second stressor layers.
17. production method as claimed in claim 16, which is characterized in that the transistor is NMOS, and the substrate serves as a contrast for silicon
Bottom carries out ion doping, to form the second stressor layers of carbofrax material using carbon ion.
18. production method as described in claim 1, which is characterized in that in the step of forming the first stressor layers, described first
Stressor layers are germanium silicon stressor layers；In the step of forming the second stressor layers, second stressor layers are silicon carbide stressor layers.
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| US7023018B2 (en) * | 2004-04-06 | 2006-04-04 | Texas Instruments Incorporated | SiGe transistor with strained layers |
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