CN104615554A - Memory module detecting method, memory control circuit unit and storing device - Google Patents
Memory module detecting method, memory control circuit unit and storing device Download PDFInfo
- Publication number
- CN104615554A CN104615554A CN201310537831.8A CN201310537831A CN104615554A CN 104615554 A CN104615554 A CN 104615554A CN 201310537831 A CN201310537831 A CN 201310537831A CN 104615554 A CN104615554 A CN 104615554A
- Authority
- CN
- China
- Prior art keywords
- memorizer
- circuit unit
- control circuit
- bus
- logic level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
A method for detecting a rewritable nonvolatile memory module includes: setting an output voltage of a write protect pin of a memory interface as a first logical potential, issuing a read state command and receiving a first state message. The present method further includes: determining whether bit data corresponding to the first state message is a state meeting the corresponding first logical potential; and if so, identifying that the rewritable nonvolatile memory module is already connected to the memory interface.
Description
Technical field
The invention relates to a kind of detect reproducible nonvolatile memorizer module method and the memorizer control circuit unit using the method and memorizer memory devices.
Background technology
Due to type nonvolatile (rewritable non-volatile memory) there is data non-volatile, power saving, the characteristic such as volume is little, mechanical structure, read or write speed are fast, therefore, type nonvolatile industry becomes a ring quite popular in electronic industry in recent years.Such as, using flash memory as the solid state hard disc of Storage Media widespread use as the hard disk of main frame, to promote the access usefulness of computing machine.When user carries out park mode (sleep mode), host computer system can the power supply of interrupt storage storage device and memory buffer as shutdown.In addition, when user is for being returned to normal operation from park mode, memorizer memory devices needs to reinitialize.Such as, in general, the memorizer control circuit unit of memorizer memory devices can seriatim by each reproducible nonvolatile memorizer module in activation memorizer memory devices and according to detecting in response to the signal on the Ready/Busy pin of memory interface the memory interface whether each type nonvolatile operated in memorizer memory devices is connected to memorizer control circuit unit smoothly.But, be not connected in the example of the memory interface of memorizer control circuit unit smoothly in type nonvolatile, memorizer control circuit unit need Ready/Busy pin in one section of Preset Time (namely, overtime) do not respond ready state (such as, ' 0 ') could confirm time that type nonvolatile is not connected to the memory interface of memorizer control circuit unit smoothly, and send error message.
Summary of the invention
The invention provides a kind of method, memorizer control circuit unit and the memorizer memory devices that detect reproducible nonvolatile memorizer module, whether it type nonvolatile rapidly in determining storage device storage device can be connected to memorizer control circuit unit.
Accordingly, the present invention one exemplary embodiment proposes a kind of method detecting reproducible nonvolatile memorizer module, for detecting reproducible nonvolatile memorizer module by memorizer control circuit unit by memory interface.The method of this detection reproducible nonvolatile memorizer module comprises: the output voltage of the write protection pin of the control bus of memory interface is set as the first logic level by (a); reading state instruction is assigned by control bus; and receive the first status message by the data bus of memory interface, wherein control bus and data bus are bus independent of each other.The method of this detection reproducible nonvolatile memorizer module also comprises: (c) judges whether the corresponding bit data of the first status message is the state meeting corresponding first logic level; And if (d) the first corresponding bit data of status message when being the state meeting corresponding first logic level, identify that above-mentioned reproducible nonvolatile memorizer module is connected to memory interface.
In one example of the present invention embodiment, the method of above-mentioned detection reproducible nonvolatile memorizer module also comprises: the output voltage of the write protection pin of control bus is set as the second logic level by (b), assign reading state instruction by control bus, and receive the second status message by data bus; And (c) judges whether the corresponding bit data of the second status message is the state meeting corresponding second logic level, wherein only when the corresponding bit data of the first status message be meet the state of corresponding first logic level and the corresponding bit data of the second status message is the state meeting corresponding second logic level time, reproducible nonvolatile memorizer module just can be identified and be connected to memory interface.
In one example of the present invention embodiment, the method for above-mentioned detection reproducible nonvolatile memorizer module assigns reset indication by control bus before being also included in and performing above-mentioned steps (a).
In one example of the present invention embodiment, the method for above-mentioned detection reproducible nonvolatile memorizer module sends chip enable signal by the chip enable pin of control bus before being also included in and assigning above-mentioned reset indication by control bus.
In one example of the present invention embodiment, above-mentioned steps (a), above-mentioned steps (b) and above-mentioned steps (c) are performed when above-mentioned memorizer control circuit unit powers at every turn.
In one example of the present invention embodiment, the control bus of above-mentioned memory interface is not configured with Ready/Busy pin.
The present invention one exemplary embodiment proposes a kind of memorizer control circuit unit, and it comprises memory interface and memory management circuitry.Memory interface comprises control bus and data bus, and wherein control bus comprises write protection pin and control bus and data bus are bus independent of each other.Memory management circuitry is electrically connected to memory interface, in order to the output voltage of write protection pin is set as the first logic level, assigns reading state instruction by control bus, and receives the first status message by data bus.Moreover memory management circuitry is also in order to judge whether the corresponding bit data of the first status message is the state meeting corresponding first logic level, and whether the corresponding bit data judging the second status message is the state meeting corresponding second logic level.If when the corresponding bit data of the first status message is the state meeting corresponding first logic level, memory management circuitry identification reproducible nonvolatile memorizer module is connected to memory interface.
In one example of the present invention embodiment, memory management circuitry is also set as the second logic level in order to the output voltage of the write protection pin by control bus, assigns reading state instruction by control bus, and receives the second status message by data bus.Memory management circuitry is also in order to judge whether the corresponding bit data of the second status message is the state meeting corresponding second logic level, wherein only when the corresponding bit data of the first status message is meet the state of corresponding first logic level and the corresponding bit data of the second status message is the state meeting corresponding second logic level, memory management circuitry just can identify that reproducible nonvolatile memorizer module is connected to memory interface.
In one example of the present invention embodiment, above-mentioned memory management circuitry is also in order to assign reset indication by control bus.
In one example of the present invention embodiment, above-mentioned memory management circuitry, also in order to before assigning reset indication by control bus, sends chip enable signal by the chip enable pin of control bus.
In one example of the present invention embodiment, the control bus of above-mentioned memory interface also comprises instruction breech lock activation pin, address latch activation pin and chip enable pin.
In one example of the present invention embodiment, the control bus of above-mentioned memory interface is not configured with Ready/Busy pin.
The present invention one exemplary embodiment proposes a kind of memorizer memory devices, and it comprises connecting interface unit, reproducible nonvolatile memorizer module and memorizer control circuit unit.Connecting interface unit is in order to be electrically connected to host computer system.Reproducible nonvolatile memorizer module has multiple physics erased cell.Memorizer control circuit unit is electrically connected to connecting interface unit and reproducible nonvolatile memorizer module, and comprises memory interface.Memorizer control circuit unit is in order to be set as the first logic level by the output voltage of write protection pin; reading state instruction is assigned by control bus; and receive the first status message by data bus, wherein control bus and data bus are bus independent of each other.Moreover memorizer control circuit unit is also in order to judge whether the corresponding bit data of the first status message is the state meeting corresponding first logic level.If when the corresponding bit data of the first status message is the state meeting corresponding first logic level, memorizer control circuit unit identification reproducible nonvolatile memorizer module is connected to memory interface.
In one example of the present invention embodiment; above-mentioned memorizer control circuit unit is also set as the second logic level in order to the output voltage of the write protection pin by control bus; assign reading state instruction by control bus, and receive the second status message by data bus.In addition, memorizer control circuit unit is also in order to judge whether the corresponding bit data of the second status message is the state meeting corresponding second logic level, wherein only when the corresponding bit data of the first status message is meet the state of corresponding first logic level and the corresponding bit data of the second status message is the state meeting corresponding second logic level, memorizer control circuit unit just can identify that reproducible nonvolatile memorizer module is connected to memory interface.
In one example of the present invention embodiment, above-mentioned memorizer control circuit unit is also in order to assign reset indication by control bus.
In one example of the present invention embodiment, above-mentioned memorizer control circuit unit, also in order to before assigning reset indication by control bus, sends chip enable signal by the chip enable pin of control bus.
The present invention one exemplary embodiment proposes a kind of memorizer memory devices, and it comprises connecting interface unit, reproducible nonvolatile memorizer module and memorizer control circuit unit.Connecting interface unit is in order to be electrically connected to host computer system.Reproducible nonvolatile memorizer module has multiple physics erased cell.Memorizer control circuit unit is electrically connected to connecting interface unit and reproducible nonvolatile memorizer module, and comprises the memory interface with control bus and data bus.Control bus comprises write protection pin, instruction breech lock activation pin, address latch activation pin and chip enable pin; and write protection pin, instruction breech lock activation pin, address latch activation pin and chip enable pin are electrically connected to reproducible nonvolatile memorizer module respectively, and wherein the control bus of memory interface is not configured with Ready/Busy pin.
Based on above-mentioned, the method for the detection reproducible nonvolatile memorizer module of above-mentioned exemplary embodiment, memorizer control circuit unit and memorizer memory devices can shorten and detect reproducible nonvolatile memorizer module and whether be normally connected the required time.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawings to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the host computer system and memorizer memory devices that illustrate according to an exemplary embodiment.
Fig. 2 is the schematic diagram of computing machine, input/output device and the memorizer memory devices illustrated according to exemplary embodiment of the present invention.
Fig. 3 is the schematic diagram of host computer system and the memorizer memory devices illustrated according to exemplary embodiment of the present invention.
Fig. 4 is the schematic block diagram illustrating the memorizer memory devices shown in Fig. 1.
Fig. 5 is the schematic block diagram of the memorizer control circuit unit illustrated according to an exemplary embodiment.
Fig. 6 be according to the present invention one exemplary embodiment illustrate for the detailed block diagram of the memory interface of connected storage control circuit unit and reproducible nonvolatile memorizer module.
Fig. 7 is the process flow diagram of the method for the detection reproducible nonvolatile memorizer module illustrated according to an exemplary embodiment.
[label declaration]
1000: host computer system 1100: computing machine
1102: microprocessor 1104: random access memory
1106: input/output device 1108: system bus
1110: data transmission interface 1202: mouse
1204: keyboard 1206: display
1208: printer 1212: portable disk
1214: storage card 1216: solid state hard disc
1310: digital camera 1312:SD card
1314:MMC card 1316: memory stick
1318:CF card 1320: embedded storage device
100: memorizer memory devices 102: connecting interface unit
104: memorizer control circuit unit 106: reproducible nonvolatile memorizer module
202: memory management circuitry 204: host interface
206: memory interface 208: memory buffer
210: electric power management circuit 212: bug check and correcting circuit
410 (0) ~ 410 (N): physics erased cell 602: control bus
604: data bus 604
612: chip enable (chip enable, CE) pin
614: instruction breech lock activation (command latch enable, CLE) pin
616: address latch activation (address latch enable, ALE)
618: write protection (write protect, WP) pin
620: Ready/Busy (Ready/Busy) pin
S701, S703, S705, S707, S709, S711, S713, S715, S717: the step detecting the method for reproducible nonvolatile memorizer module
Embodiment
Generally speaking, memorizer memory devices (also known as, memory storage system) comprises reproducible nonvolatile memorizer module and controller (also known as, control circuit).Usual memorizer memory devices uses together with host computer system, data can be write to memorizer memory devices or read data from memorizer memory devices to make host computer system.
Fig. 1 is the host computer system and memorizer memory devices that illustrate according to an exemplary embodiment.
Please refer to Fig. 1, host computer system 1000 generally comprises computing machine 1100 and I/O (input/output, I/O) device 1106.Computing machine 1100 comprises microprocessor 1102, random access memory (randomaccess memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises as the mouse 1202 of Fig. 2, keyboard 1204, display 1206 and printer 1208.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Fig. 2, input/output device 1106 can also comprise other device.
In embodiments of the present invention, memorizer memory devices 100 is electrically connected by data transmission interface 1110 other element with host computer system 1000.Data can be write to memorizer memory devices 100 by microprocessor 1102, random access memory 1104 with the running of input/output device 1106 or read data from memorizer memory devices 100.Such as, memorizer memory devices 100 can be the type nonvolatile storage device of portable disk 1212, storage card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 etc. as shown in Figure 2.
Generally speaking, host computer system 1000 is to coordinate any system with storage data substantially with memorizer memory devices 100.Although in this exemplary embodiment, host computer system 1000 explains with computer system, but host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in another exemplary embodiment of the present invention.Such as, when host computer system is digital camera (video camera) 1310, type nonvolatile storage device is then its SD card 1312 used, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded storage device 1320 (as shown in Figure 3).Embedded storage device 1320 comprises embedded multi-media card (Embedded MMC, eMMC).It is worth mentioning that, embedded multi-media card is directly electrically connected on the substrate of host computer system.
Fig. 4 is the schematic block diagram illustrating the memorizer memory devices shown in Fig. 1.
Please refer to Fig. 4, memorizer memory devices 100 comprises connecting interface unit 102, memorizer control circuit unit 104 and reproducible nonvolatile memorizer module 106.
In this exemplary embodiment, connecting interface unit 102 is compatible with advanced annex (SerialAdvanced Technology Attachment, the SATA) standard of sequence.But, it must be appreciated, the present invention is not limited thereto, connecting interface unit 102 can also be meet advanced annex arranged side by side (Parellel AdvancedTechnology Attachment, PATA) standard, Institute of Electrical and Electric Engineers (Institute ofElectrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) standard, a hypervelocity generation (Ultra High Speed-I, UHS-I) interface standard, hypervelocity two generation (Ultra High Speed-II, UHS-II) interface standard, secure digital (SecureDigital, SD) interface standard, memory stick (Memory Stick, MS) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, compact flash (Compact Flash, CF) interface standard, integrated form drives electrical interface (Integrated Device Electronics, IDE) standard or other standard be applicable to.In this exemplary embodiment, connecting interface unit can with memorizer control circuit unit package in a chip, or is laid in one and comprises outside the chip of memorizer control circuit unit.
Memorizer control circuit unit 104 in order to perform with multiple logic gate of hardware pattern or firmware pattern implementation or steering order, and according to the instruction of host computer system 1000 carry out in reproducible nonvolatile memorizer module 106 data write, read and the running such as to erase.
Reproducible nonvolatile memorizer module 106 is electrically connected to memorizer control circuit unit 104, and in order to store the data that host computer system 1000 writes.Reproducible nonvolatile memorizer module 106 has physics erased cell 410 (0) ~ 410 (N).Such as, physics erased cell 410 (0) ~ 410 (N) can belong to same memory crystal grain (die) or belong to different memory crystal grain.Each physics erased cell has multiple physics programming unit respectively, and the physics programming unit wherein belonging to same physics erased cell can be written independently and side by side be erased.But it must be appreciated, the present invention is not limited thereto, each physics erased cell can be made up of 64 physics programming units, 256 physics programming units or other any physics programming unit.
In more detail, physics erased cell is the least unit of erasing.That is, each physics erased cell contain minimal amount in the lump by the storage unit of erasing.Physics programming unit is the minimum unit of programming.That is, physics programming unit is the minimum unit of write data.Each physics programming unit generally includes data bit district and redundant digit district.Data bit district comprises multiple physics access address in order to store the data of user, and redundant digit district is in order to the data (such as, control information and error correcting code) of stocking system.In this exemplary embodiment, 4 physics access addresses in the data bit district of each physics programming unit, can be comprised, and the size of a physics access address is 512 bytes (byte).But in other exemplary embodiment, can comprise the more or less physics access address of number in data bit district, the present invention does not limit size and the number of physics access address yet.Such as, in an exemplary embodiment, physics erased cell is physical blocks, and physics programming unit is physical page or physical sector, but the present invention is not as limit.
In this exemplary embodiment, reproducible nonvolatile memorizer module 106 is multi-level cell memory (Multi Level Cell, MLC) NAND flash memory module (that is, the flash memory module of 2 bit data can be stored in a storage unit).But, the present invention is not limited thereto, reproducible nonvolatile memorizer module 106 also single-order storage unit (Single Level Cell, SLC) NAND flash memory module (namely, the flash memory module of 1 bit data can be stored in a storage unit), multi-level cell memory (Trinary LevelCell, TLC) NAND flash memory module (that is, the flash memory module of 3 bit data can be stored in a storage unit), other flash memory module or other there is the memory module of identical characteristics.
Fig. 5 is the schematic block diagram of the memorizer control circuit unit illustrated according to an exemplary embodiment.
Please refer to Fig. 5, memorizer control circuit unit 104 comprises memory management circuitry 202, host interface 204 and memory interface 206.
Memory management circuitry 202 is in order to the overall operation of control store control circuit unit 104.Specifically, memory management circuitry 202 has multiple steering order, and when memorizer memory devices 100 operates, this little steering order can be performed to carry out data write, read and the running such as to erase.
In this exemplary embodiment, the steering order of memory management circuitry 202 carrys out implementation with firmware pattern.Such as, memory management circuitry 202 has microprocessor unit (not illustrating) and ROM (read-only memory) (not illustrating), and this little steering order is burned onto in this ROM (read-only memory).When memorizer memory devices 100 operates, this little steering order can by microprocessor unit perform to carry out data write, read and the running such as to erase.
In another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 can also procedure code pattern be stored in the specific region (such as, being exclusively used in the system region of storage system data in memory module) of reproducible nonvolatile memorizer module 106.In addition, memory management circuitry 202 has microprocessor unit (not illustrating), ROM (read-only memory) (not illustrating) and random access memory (not illustrating).Particularly, this ROM (read-only memory) has driving code, and when memorizer control circuit unit 104 is enabled, microprocessor unit first can perform this and drive code section the steering order be stored in reproducible nonvolatile memorizer module 106 to be loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can operate this little steering order with carry out data write, read and the running such as to erase.
In addition, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 a hardware pattern can also carry out implementation.Such as, memory management circuitry 202 comprises microcontroller, Storage Unit Management circuit, storer write circuit, memory reading circuitry, storer erase circuit and data processing circuit.Erase circuit and data processing circuit of Storage Unit Management circuit, storer write circuit, memory reading circuitry, storer is electrically connected to microcontroller.Wherein, Storage Unit Management circuit is in order to manage the physics erased cell of reproducible nonvolatile memorizer module 106; Storer write circuit is in order to assign write instruction data to be write in reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; Memory reading circuitry is in order to assign reading command to read data from reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; Storer erases circuit in order to assign instruction of erasing to reproducible nonvolatile memorizer module 106 data to be erased from reproducible nonvolatile memorizer module 106; And data processing circuit is in order to the data processed for writing to reproducible nonvolatile memorizer module 106 and the data read from reproducible nonvolatile memorizer module 106.
Host interface 204 is electrically connected to memory management circuitry 202 and in order to receive and to identify the instruction that transmits of host computer system 1000 and data.That is, the instruction that transmits of host computer system 1000 and data can be sent to memory management circuitry 202 by host interface 204.In this exemplary embodiment, host interface 204 is compatible with SATA standard.But, it must be appreciated and the present invention is not limited thereto, host interface 204 can also be compatible with PATA standard, IEEE1394 standard, PCI Express standard, USB standard, UHS-I interface standard, UHS-II interface standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other data transmission standard be applicable to.
Memory interface 206 is electrically connected to memory management circuitry 202 and in order to access reproducible nonvolatile memorizer module 106.That is, the data for writing to reproducible nonvolatile memorizer module 106 can be converted to the receptible form of reproducible nonvolatile memorizer module 106 via memory interface 206.
In the present invention one exemplary embodiment, memorizer control circuit unit 104 also comprises memory buffer 208, electric power management circuit 210 and bug check and correcting circuit 212.
Memory buffer 208 is electrically connected to memory management circuitry 202 and comes from the data and instruction of host computer system 1000 in order to temporary or come from the data of reproducible nonvolatile memorizer module 106.
Electric power management circuit 210 is electrically connected to memory management circuitry 202 and in order to the power supply of control store storage device 100.
Bug check and correcting circuit 212 are electrically connected to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives write instruction from host computer system 1000, bug check and correcting circuit 212 can be that the corresponding data that this writes instruction produce corresponding bug check and correcting code (Error Checking andCorrecting Code, ECC Code), and the data of this write instruction corresponding can write in reproducible nonvolatile memorizer module 106 with corresponding bug check and correcting code by memory management circuitry 202.Afterwards, can read bug check corresponding to these data and correcting code when memory management circuitry 202 reads data from reproducible nonvolatile memorizer module 106, and bug check and correcting circuit 212 can according to this bug check and correcting code to read data execution error inspection and correction programs simultaneously.
Fig. 6 be according to the present invention one exemplary embodiment illustrate for the detailed block diagram of the memory interface of connected storage control circuit unit and reproducible nonvolatile memorizer module.
Please refer to Fig. 6, memory interface 206 comprises control bus 602 and data bus 604.And, control bus 602 comprises chip enable (chip enable, CE) pin 612, instruction breech lock activation (commandlatch enable, CLE) pin 614, address latch activation (address latch enable, ALE) 616,
Write protection (write protect, WP) pin 618 and Ready/Busy (Ready/Busy) pin 620.
Memorizer control circuit unit 104 (or memory management circuitry 202) is assigned steering order to reproducible nonvolatile memorizer module 106 via control bus 602 and is obtained the state of reproducible nonvolatile memorizer module 106 by control bus 602.In addition, memorizer control circuit unit 104 (or memory management circuitry 202) transmits data via data bus 604 and receives data to reproducible nonvolatile memorizer module 106 or from reproducible nonvolatile memorizer module 106.Base this, by control bus 602 and data bus 604, memorizer control circuit unit 104 (or memory management circuitry 202) can reset (reset) running to reproducible nonvolatile memorizer module 106, write (write) operates, reading (read) operates, (erase) running etc. of erasing.
In this exemplary embodiment, when memorizer memory devices 100 powers on, memorizer control circuit unit 104 (or memory management circuitry 202) can send chip enable signal to reproducible nonvolatile memorizer module 106 by chip enable pin 612 and send reset indication to reproducible nonvolatile memorizer module 106 by instruction breech lock activation pin 614.Particularly, after replacement reproducible nonvolatile memorizer module 106, the output voltage of write protection pin 618 can be set as the first logic level by memorizer control circuit unit 104 (or memory management circuitry 202).Such as, in this exemplary embodiment, the first logic level is a logic high potential.
Then, memorizer control circuit unit 104 (or memory management circuitry 202) can be sent reading state instruction (read status command) by instruction breech lock activation pin 614 and be received the first status message of this reading state instruction of response by data bus 604.And; memorizer control circuit unit 104 (or memory management circuitry 202) can judge the bit data of corresponding write protection pin 618 in the first status message (such as; whether the 8th bit data (that is, ' bit7 ') in the first status message is the output voltage of corresponding write protection pin 618 state when being set to the first logic level.Such as, be in the example of logic high potential at the first logic level, the state when output voltage of corresponding write protection pin 618 is set to the first logic level is ' 0 '.If during state when the non-output voltage for corresponding write protection pin of the bit data of corresponding write protection pin 618 is set to the first logic level in the first status message, memorizer control circuit unit 104 (or memory management circuitry 202) can judge that reproducible nonvolatile memorizer module 106 is not connected to memory interface 206.
If when in the first status message, the bit data of corresponding write protection pin 618 is state when being set to the first logic level of the output voltage of corresponding write protection pin, the output voltage of write protection pin 618 can be set as the second logic level by memorizer control circuit unit 104 (or memory management circuitry 202) again.Such as, in this exemplary embodiment, the second logic level is a logic low potential.
Then, memorizer control circuit unit 104 (or memory management circuitry 202) can be sent reading state instruction by instruction breech lock activation pin 614 and be received the second status message of this reading state instruction of response by data bus 604.And; memorizer control circuit unit 104 (or memory management circuitry 202) can judge the bit data of corresponding write protection pin 618 in the second status message (such as; whether the 8th bit data (that is, ' bit7 ') in the second status message is the output voltage of corresponding write protection pin 618 state when being set to the second logic level.Such as, be in the example of logic high potential at the second logic level, the state when output voltage of corresponding write protection pin 618 is set to the second logic level is ' 1 '.If during state when the non-output voltage for corresponding write protection pin 618 of the bit data of corresponding write protection pin 618 is set to the second logic level in the second status message, memorizer control circuit unit 104 (or memory management circuitry 202) can judge that reproducible nonvolatile memorizer module 106 is not connected to memory interface 206.
If in the first status message the bit data of corresponding write protection pin 618 be state when being set to the first logic level of the output voltage of corresponding write protection pin 618 and in the second status message, the bit data of corresponding write protection pin 618 is state when being set to the second logic level of the output voltage of corresponding write protection pin 618 time, memorizer control circuit unit 104 (or memory management circuitry 202) can judge that reproducible nonvolatile memorizer module 106 has been connected to memory interface 206.
In this exemplary embodiment; after judging that reproducible nonvolatile memorizer module 106 is not connected to memory interface 206 passing through the state of the logic level responding write protection pin 618; memorizer control circuit unit 104 (or memory management circuitry 202) just can send error message to host computer system 100, and comes from the signal of Ready/Busy pin 620 without the need to continuous wait.
It must be appreciated, although in this exemplary embodiment, be detect a reproducible nonvolatile memorizer module 106 to explain, the present invention is not limited thereto.Such as, in the memorizer memory devices with multiple reproducible nonvolatile memorizer module, its memorizer control circuit unit (or memory management circuitry) synchronously can perform the running of above-mentioned detection and judgement to the many groups control bus and data bus that connect so far a little reproducible nonvolatile memorizer module.Particularly; have in the memorizer memory devices example of multiple reproducible nonvolatile memorizer module at this, can confirm whether each reproducible nonvolatile memorizer module is successfully connected to memorizer control circuit unit more quickly by the write protection pin of each control bus.
In addition, it is worth mentioning that, although in this exemplary embodiment, Ready/Busy pin 620 still can operate normally, and memorizer control circuit unit 104 (or memory management circuitry 202) to know whether reproducible nonvolatile memorizer module 106 is in by the signal in Ready/Busy pin 620 idle or busy.But in another exemplary embodiment of the present invention, control bus 602 also can not be configured with Ready/Busy pin 620.Specifically; when memorizer memory devices 100 powers on, by the state of the logic level of response write protection pin 618, memorizer control circuit unit 104 (or memory management circuitry 202) can judge whether reproducible nonvolatile memorizer module 106 is connected to memory interface 206.Then, in reproducible nonvolatile memorizer module 106 operation process, memorizer control circuit unit 104 (or memory management circuitry 202) can send reading state instruction by instruction breech lock activation pin 614, by data bus 604 receive the instruction of response reading state status message and according to the bit data in status message judge reproducible nonvolatile memorizer module 106 be in idle or busy.Therefore, Ready/Busy pin 620 also can not need configuration and be connected between memorizer control circuit unit 104 and reproducible nonvolatile memorizer module 106.
Fig. 7 is the process flow diagram of the method for the detection reproducible nonvolatile memorizer module illustrated according to an exemplary embodiment.
Please refer to Fig. 7, when memorizer memory devices 100 powers on, in step s 701, memorizer control circuit unit 104 (or memory management circuitry 202) can send chip enable signal by chip enable pin 612 and send reset indication by control bus 602 (such as, instruction breech lock activation pin 614).
Afterwards, in step S703, the output voltage of the write protection pin 618 of the control bus 602 of memory interface 206 can be set as the first logic level by memorizer control circuit unit 104 (or memory management circuitry 202).
Then, in step S705, memorizer control circuit unit 104 (or memory management circuitry 202) can assign reading state instruction by control bus 602, and receives the first status message of this reading state of response by data bus 604.Further, in step S707, memorizer control circuit unit 104 (or memory management circuitry 202) can judge whether the corresponding bit data of the first status message is the state meeting the first logic level.Specifically; as mentioned above; the 8th bit data in the status message of response reading state instruction (namely; bit7) be the state of corresponding write protection pin 618, and the value that memorizer control circuit unit 104 (or memory management circuitry 202) understands this bit data determines whether to conform to the state responding the first logic level being set to write protection pin 618.
If the corresponding bit data of the first status message non-for meet the first logic level state time, in step S709, memorizer control circuit unit 104 (or memory management circuitry 202) can judge that reproducible nonvolatile memorizer module 106 is not connected to memorizer control circuit unit 104 and output error message.
If when the corresponding bit data of the first status message is the state meeting the first logic level; in step S711, the output voltage of the write protection pin 618 of the control bus 602 of memory interface 206 can be set as the second logic level by memorizer control circuit unit 104 (or memory management circuitry 202).
Then, in step S713, memorizer control circuit unit 104 (or memory management circuitry 202) can assign reading state instruction by control bus 602, and receives the second status message of this reading state of response by data bus 604.Further, in step S715, memorizer control circuit unit 104 (or memory management circuitry 202) can judge whether the corresponding bit data of the second status message is the state meeting the second logic level.
If the corresponding bit data of the second status message non-for meet the second logic level state time, then step S709 can be performed.Otherwise in step S717, memorizer control circuit unit 104 (or memory management circuitry 202) can judge that reproducible nonvolatile memorizer module 106 has been connected to memorizer control circuit unit 104.Such as, after step S717, memorizer control circuit unit 104 (or memory management circuitry 202) can perform initialization running according to the state of reproducible nonvolatile memorizer module 106.
It must be appreciated, although in this exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) can judge that whether the corresponding bit data of the corresponding bit data of the first status message as the state and the second status message that meet the first logic level be as under the state meeting the second logic level at the same time, just identifies that reproducible nonvolatile memorizer module 106 has been connected to memorizer control circuit unit 104.But, the present invention is not limited thereto, in another exemplary embodiment of the present invention, memorizer control circuit unit 104 (or memory management circuitry 202) also under the corresponding bit data of the first status message is the state meeting the first logic level, can just judge that reproducible nonvolatile memorizer module 106 has been connected to memorizer control circuit unit 104.That is, above-mentioned steps S713 and S715 can omit.
In sum; the method of the detection reproducible nonvolatile memorizer module of exemplary embodiment of the present invention, memorizer control circuit unit and memorizer memory devices are output voltages by setting write protection pin and confirm whether reproducible nonvolatile memorizer module is normally connected according to reading state, can shorten the time detected needed for reproducible nonvolatile memorizer module thus.
Claims (19)
1. one kind is detected the method for reproducible nonvolatile memorizer module, for detecting a reproducible nonvolatile memorizer module by a memorizer control circuit unit by a memory interface, the method for this detection reproducible nonvolatile memorizer module comprises:
A the output voltage of one write protection pin of one control bus of this memory interface is set as one first logic level by this memorizer control circuit unit by (), a reading state instruction is assigned by this control bus by this memorizer control circuit unit, and receive one first status message by this memorizer control circuit unit by a data bus of this memory interface, wherein this control bus and this data bus are bus independent of each other;
B whether () is meet should the state of the first logic level by a corresponding bit data of this this first status message of memorizer control circuit unit judges; And
If this corresponding bit data of (c) this first status message be meet to should the state of the first logic level time, be connected to this memory interface by this this reproducible nonvolatile memorizer module of memorizer control circuit unit identification.
2. the method for detection reproducible nonvolatile memorizer module according to claim 1, also comprises:
By this memorizer control circuit unit, the output voltage of this write protection pin of this control bus is set as one second logic level, assigns this reading state instruction by this control bus, and receive one second status message by this data bus; And
Be whether meet should the state of the second logic level by this corresponding bit data of this this second status message of memorizer control circuit unit judges,
Wherein only when this corresponding bit data of this first status message be meet to should the state of the first logic level and this corresponding bit data of this second status message be meet to should the state of the second logic level time, this reproducible nonvolatile memorizer module just can be identified and be connected to this memory interface.
3. the method for detection reproducible nonvolatile memorizer module according to claim 1, also comprises:
Before execution above-mentioned steps (a), assign a reset indication by this memorizer control circuit unit by this control bus.
4. the method for detection reproducible nonvolatile memorizer module according to claim 3, also comprises:
Before assigning this reset indication by this control bus, send a chip enable signal by this memorizer control circuit unit by a chip enable pin of this control bus.
5. the method for detection reproducible nonvolatile memorizer module according to claim 1, wherein above-mentioned steps (a), above-mentioned steps (b) are be performed when this memorizer control circuit unit powers at every turn with above-mentioned steps (c).
6. the method for detection reproducible nonvolatile memorizer module according to claim 1, wherein this control bus of this memory interface is not configured with a Ready/Busy pin.
7. a memorizer control circuit unit, comprising:
One memory interface, comprises a control bus and a data bus, and wherein this control bus comprises a write protection pin and this control bus and this data bus are bus independent of each other; And
One memory management circuitry, is electrically connected to this memory interface, in order to the output voltage of this write protection pin is set as one first logic level, assigns a reading state instruction by this control bus, and receives one first status message by this data bus,
Wherein this memory management circuitry is also in order to judge that whether one of this first status message corresponding bit data is meet should the state of the first logic level,
If wherein this corresponding bit data of this first status message be meet to should the state of the first logic level time, this memory management circuitry identification one reproducible nonvolatile memorizer module has been connected to this memory interface.
8. memorizer control circuit unit according to claim 7; wherein this memory management circuitry is also set as one second logic level in order to the output voltage of this write protection pin by this control bus; this reading state instruction is assigned by this control bus; and receive one second status message by this data bus
Wherein this memory management circuitry is also in order to judge that whether this corresponding bit data of this second status message is meet should the state of the second logic level,
Wherein only when this corresponding bit data of this first status message is meet should the state of the first logic level and this corresponding bit data of this second status message be meet should the state of the second logic level, this memory management circuitry just can identify that this reproducible nonvolatile memorizer module has been connected to this memory interface.
9. memorizer control circuit unit according to claim 7, wherein this memory management circuitry is also in order to assign a reset indication by this control bus.
10. memorizer control circuit unit according to claim 9, wherein this memory management circuitry is also in order to before assigning this reset indication by this control bus, sends a chip enable signal by a chip enable pin of this control bus.
11. memorizer control circuit unit according to claim 7, wherein this control bus of this memory interface also comprises an instruction breech lock activation pin, an address latch activation pin and a chip enable pin.
12. memorizer control circuit unit according to claim 11, wherein this control bus of this memory interface is not configured with a Ready/Busy pin.
13. 1 kinds of memorizer memory devices, comprising:
One connecting interface unit, in order to be electrically connected to a host computer system;
One reproducible nonvolatile memorizer module, has multiple physics erased cell; And
One memorizer control circuit unit, is electrically connected to this connecting interface unit and this reproducible nonvolatile memorizer module, and comprises a memory interface,
Wherein this memorizer control circuit unit is set as one first logic level in order to the output voltage of a write protection pin of the control bus by this memory interface; a reading state instruction is assigned by this control bus; and receive one first status message by a data bus of this memory interface; wherein this control bus and this data bus are bus independent of each other
Wherein this memorizer control circuit unit is also in order to judge that whether one of this first status message corresponding bit data is meet should the state of the first logic level,
If wherein this corresponding bit data of this first status message be meet to should the state of the first logic level time, this this reproducible nonvolatile memorizer module of memorizer control circuit unit identification has been connected to this memory interface.
14. memorizer memory devices according to claim 13; wherein this memorizer control circuit unit is also set as one second logic level in order to the output voltage of this write protection pin by this control bus; this reading state instruction is assigned by this control bus; and receive one second status message by this data bus
Wherein this memorizer control circuit unit is also in order to judge that whether this corresponding bit data of this second status message is meet should the state of the second logic level,
Wherein only when this corresponding bit data of this first status message is meet should the state of the first logic level and this corresponding bit data of this second status message be meet should the state of the second logic level, this memorizer control circuit unit just can identify that this reproducible nonvolatile memorizer module has been connected to this memory interface.
15. memorizer memory devices according to claim 13, wherein this memorizer control circuit unit is also in order to assign a reset indication by this control bus.
16. memorizer memory devices according to claim 15, wherein this memorizer control circuit unit is also in order to before assigning this reset indication by this control bus, sends a chip enable signal by a chip enable pin of this control bus.
17. memorizer memory devices according to claim 13, wherein this control bus of this memory interface also comprises an instruction breech lock activation pin, an address latch activation pin and a chip enable pin.
18. memorizer memory devices according to claim 17, wherein this control bus of this memory interface is not configured with a Ready/Busy pin.
19. 1 kinds of memorizer memory devices, comprising:
One connecting interface unit, in order to be electrically connected to a host computer system;
One reproducible nonvolatile memorizer module, has multiple physics erased cell; And
One memorizer control circuit unit, is electrically connected to this connecting interface unit and this reproducible nonvolatile memorizer module, and comprises a memory interface with a control bus and a data bus,
Wherein this control bus comprises a write protection pin, an instruction breech lock activation pin, an address latch activation pin and a chip enable pin; and this write protection pin, this instruction breech lock activation pin, this address latch activation pin and this chip enable pin are electrically connected to this reproducible nonvolatile memorizer module respectively
Wherein this control bus of this memory interface is not configured with a Ready/Busy pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310537831.8A CN104615554B (en) | 2013-11-04 | 2013-11-04 | Memory module detection method, memorizer control circuit unit and storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310537831.8A CN104615554B (en) | 2013-11-04 | 2013-11-04 | Memory module detection method, memorizer control circuit unit and storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104615554A true CN104615554A (en) | 2015-05-13 |
| CN104615554B CN104615554B (en) | 2018-11-23 |
Family
ID=53150008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310537831.8A Active CN104615554B (en) | 2013-11-04 | 2013-11-04 | Memory module detection method, memorizer control circuit unit and storage device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104615554B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109273032A (en) * | 2017-07-17 | 2019-01-25 | 群联电子股份有限公司 | Memorizer control circuit unit, memory storage apparatus and its control method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101295285A (en) * | 2007-04-25 | 2008-10-29 | 群联电子股份有限公司 | Integrated data processing system, flash memory system and flash memory controller |
| CN101477838A (en) * | 2008-12-31 | 2009-07-08 | 深圳市同洲电子股份有限公司 | Condition detection apparatus, system and electronic device for NAND flash memory body |
| CN101740105A (en) * | 2008-11-24 | 2010-06-16 | 联发科技股份有限公司 | System and method for accessing memory card |
-
2013
- 2013-11-04 CN CN201310537831.8A patent/CN104615554B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101295285A (en) * | 2007-04-25 | 2008-10-29 | 群联电子股份有限公司 | Integrated data processing system, flash memory system and flash memory controller |
| CN101740105A (en) * | 2008-11-24 | 2010-06-16 | 联发科技股份有限公司 | System and method for accessing memory card |
| CN101477838A (en) * | 2008-12-31 | 2009-07-08 | 深圳市同洲电子股份有限公司 | Condition detection apparatus, system and electronic device for NAND flash memory body |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109273032A (en) * | 2017-07-17 | 2019-01-25 | 群联电子股份有限公司 | Memorizer control circuit unit, memory storage apparatus and its control method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104615554B (en) | 2018-11-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103035282B (en) | Memorizer memory devices, Memory Controller and method for managing temperature | |
| CN104732153A (en) | Data erasing method, storage control circuit unit and storage storing device | |
| US9032135B2 (en) | Data protecting method, memory controller and memory storage device using the same | |
| CN104423888A (en) | Data writing method, memory control circuit unit and memory storage device | |
| CN105005450A (en) | Data writing method, memory storage device, and memory control circuit unit | |
| US9383929B2 (en) | Data storing method and memory controller and memory storage device using the same | |
| CN104765569A (en) | Data write-in method, memory control circuit unit and memory storing device | |
| CN103377129A (en) | Data writing-in method, memory controller and memory storage device | |
| CN103514096A (en) | Data storage method, memory controller and memory storage device | |
| TWI486765B (en) | Memory management method, memory controller and memory storage device using the same | |
| CN102890645B (en) | Memorizer memory devices, Memory Controller and method for writing data | |
| US10191533B2 (en) | Method of enabling sleep mode, memory control circuit unit and storage apparatus | |
| CN111078146B (en) | Memory management method, memory storage device and memory control circuit unit | |
| CN102446137B (en) | Method for writing data, Memory Controller and memorizer memory devices | |
| CN103678162A (en) | System data storage method, memorizer controller and memorizer storing device | |
| CN106325764B (en) | Memory management method, memory control circuit unit and memory storage device | |
| CN103544118A (en) | Memory storage device, memory controller thereof and data writing method | |
| CN103513930A (en) | Memorizer management method, memorizer controller and memorizer storage device | |
| CN103577344A (en) | Data writing method, memory controller and memory storage device | |
| CN104765625A (en) | Sleep mode starting method, memory control circuit unit and storing equipment | |
| CN104657083A (en) | Data writing method, storing device of memory, and control circuit unit of memory | |
| TWI494944B (en) | Method of detecting memory modules, memory control circuit unit and storage appartus | |
| CN102087632B (en) | Data storage method for flash memory, controller and storage system | |
| TWI512623B (en) | Method of enabling sleep mode, memory control circuit unit and storage apparatus | |
| CN104615554A (en) | Memory module detecting method, memory control circuit unit and storing device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |