CN104603882B - MRAM wordline power control programs - Google Patents

Abstract

System, circuit and method for the WL power levels at wordline (WL) place for controlling magnetoresistive RAM (MRAM).WL power levels are supplied and controlled to disclosed power control scheme using the existing read/write command associated with MRAM and existing power generation module, thereby eliminates by the grand relatively large and expensive power control switchings of MRAM and control circuit system to control the die size of the cost of the scheme of WL power and increase.

Description

MRAM wordline power control programs

Open field

The disclosure relates generally to the power control techniques for electronic circuit.More specifically, this disclosure relates to for controlling It is supplied to system, circuit and the method for the wordline power of magnetoresistive RAM (MRAM).

Background technology

Computing device (for example, desk-top and portable computer, mobile phone, PDA, tablet device etc.) has become increasingly It is powerful, while the demand of memory capabilities is also being increased.Memory can be classified as volatibility or non-volatile.It is volatile Property memory need constant power to maintain stored information.The most common type of memory found in a computer is Volatile random access memory (RAM).Volatibility RAM key character includes fast read/write speed and easy rewrite capability.Will Storing information on conventional volatibility RAM requires electric current through RAM.When system power supply is closed, hard drive is not replicated to Any information of device can lose.

On the contrary, nonvolatile memory does not need constant power.Thus, it is non-volatile when system power supply is closed The information stored in memory is also retained.The example of nonvolatile memory includes non-volatile ram and non-volatile Read memory (ROM).Flash memory is the ROM for the common type commonly used in USB flash disk and MP3 player.Although nonvolatile memory With maintain content in the case of not applying power the advantages of, but they with volatile memory compared with typically with relatively low Read/write speed and relatively limited life-span.

A kind of nonvolatile memory of emerging type is magnetoresistive RAM (MRAM).MRAM is by magnetic device It is combined resistance to obtain non-volatile, high speed read/write operation, unrestricted read/write with the microelectronic component based on silicon of standard Long property and the composite attribute such as data retention and low cell leakage.Different from other kinds of RAM, the data quilt in MRAM It is stored as magnetic memory rather than electric charge.Each mram cell includes transistor, the magnetic tunnel-junction (MTJ) for data storage Device, bit line, digital line and wordline.Data are read as the resistance of MTJ tunnel knot.Stored using magnetic state With two kinds of principal benefits.First, magnetic polarization will not mirror charge leaked away like that with the time, therefore information even in system electricity Source is also stored when closing.Secondly, magnetic polarization is switched between the two states without known wear mechanism.

Conventional MRAM MTJ includes fixed magnetic layer, thin dielectric tunnel potential barrier and free magnetic layer.MTJ is in free layer Magnetic moment has low resistance when parallel with fixed bed, and has high electricity when free layer magnetic moment and fixed bed magnetic moment are anti-parallel orientated Resistance.This resistance variations with device magnetic state are known as the effect of magnetic resistance, then entitled " magnetic resistance " RAM.MRAM can lead to The resistance for crossing measurement MTJ is read.For example, specific MTJ can be by activating its associated word line transistors (this self-alignment in future The current switching of line is into by the MTJ) it is selected for read operation.Due to tunnel magneto-resistance effect, MTJ resistance is based on Polarity orientation in two magnetospheres and change.Resistance in any specific MTJ can be according to electric caused by the polarity of free layer Stream determines.Routinely, if fixed bed and free layer have identical polarity, resistance is that low and " 0 " is read.Gu if Given layer and free layer have opposite polarity, then resistance is higher and " 1 " is read.Conventional MRAM write operation is magnetic operator. Correspondingly, word line transistors turn off during write operation.For current spread by bit line and digital line to establish magnetic field, the magnetic field can Influence the polarity of MTJ free layer and therefore influence MRAM logic state.

Different from conventional MRAM, spin transfer torque magnetoresistive random access memory (STT-MRAM), which uses, works as through film It is changed into the electronics of spin polarization when (spin filter).STT-MRAM be also referred to as spin transfer torque RAM (STT-RAM), from Revolve Torque Transfer Magnetization switching RAM (Spin-RAM) and spin momentum transfer (SMT-RAM).During write operation, spin polarization Electronics to free layer apply torque, the polarization of this changeable free layer.Read operation and conventional MRAM similarity are, electric Stream is used to detect resistance/logic state of MTJ storage element, as described earlier.For typical STT-MRAM, the list Member includes MTJ, transistor, bit line and wordline.Wordline coupled to transistor gate with for both read and write operations by transistor Conducting, thus electric current is allowed to flow through MTJ, so as to which logic state can be read or written.Read/write circuit system is in bit line and source line Between generation write voltage.Depending on the polarity of voltage between bit line and source line, the polarity of MTJ free layer can change, and phase Ying Di, logic state can be written into mram cell.Equally, during read operation, read current is generated, the read current is in bit line and source MTJ is flowed through between line.When word line transistors, which are activated, to be flowed through with permitting current, MTJ resistance (logic state) can be based on position Voltage difference between line and source line determines.

STT-MRAM electronics write operation eliminates the scaling problem caused by the magnetic write operation in MRAM.This Outside, STT-MRAM complex circuit designs are relatively low.However, core operating voltage Vdd fluctuation may cause unit read current Approach or higher than write current threshold value, and thus cause invalid write operation and/or the potential damage to system component.On the contrary, Vdd Fluctuation can drive operating voltage to drop to undesirable low level, and this can reduce systematic function and potentially hinder system rightly to rise Act on or system is not worked completely.These and other problem following has authorized U.S. by what disclosure assignee was possessed State's patent and published solve：United States Patent (USP) No.7,742,329, United States Patent (USP) No.8,107,280, United States Patent (USP) No.8,004,880, United States Patent (USP) No.8,027,206, United States Patent (USP) No.8,159,864 and announcement U.S. Patent application No.2009-0103354-A1.Above-mentioned patent and published are all included in this by quoting.

Specifically, United States Patent (USP) No.7,742,329 (patents of ' 329) solve the reading electricity that wordline is put on due to obscuring Press and put on wordline write voltage and caused by invalid read/write operation the problem of.The patent of ' 329 by for write operation by One voltage supply is supplied to wordline crystal to word line transistors and by the second voltage less than first voltage during read operation Pipe solves this problem in that.

The important design goal of integrated circuit include reducing the quantity of element for being used to performing Given task, size and into This.Cost is reduced to perform task and reduce the die size of integrated circuit with less and relatively inexpensive element.Accordingly Ground, it is expected that offer provides different capacity level to MRAM wordline and also optimizes the electricity of the size and cost of mram cell simultaneously Road, system and method.

General introduction

The exemplary embodiment of the present invention is related to the word put on for control in magnetoresistive RAM (MRAM) System, circuit and the method for the wordline power of line transistor.

One embodiment of the invention may include that memory module includes magnetic resistance together with power generation module, the memory module Random access memory (MRAM), the power generation module include selector, the selector be configured in response to write order or At least one of read command provides different capacity level to the wordline of the MRAM.

In another embodiment of the invention, write order causes the selector to provide the first power level to MRAM, and reads Order causes the selector to provide the second power level to MRAM.First power level can be higher than the second power level.

In another embodiment of the invention, the power generation module can be implemented as low voltage difference (LDO) adjuster, and The selector can be implemented as multiplexer, and wherein the multiplexer selects the first power level in response to write order, and wherein The multiplexer selects the second power level in response to read command.

Another embodiment of the present invention may include a kind of method of wordline power of control to MRAM, comprise the following steps： Read command and write order are coupled to power generation module；And the selector of control power generation module in response to read command or At least one of write order provides different capacity level to MRAM wordline.

In further embodiment of the present invention, write order causes the selector to provide the first power level to MRAM, and Read command causes the selector to provide the second power level to MRAM.First power level can be higher than the second power level.

In further embodiment of the present invention, the power generation module can be implemented as low voltage difference (LDO) adjuster, and And the selector can be implemented as multiplexer, wherein the multiplexer selects the first power level, and its in response to write order In the multiplexer the second power level is selected in response to read command.

Another embodiment of the present invention may include a kind of equipment, and the equipment has the device for data storage, for giving birth to The device of success rate and the device for being used for data storage to this in response at least one of write order or read command Wordline provides the device of different capacity level.

In further embodiment of the present invention, write order causes this to be used to provide the device of different capacity level to the word Line provides the first power level, and read command causes the device for being used to provide different capacity level to provide the second work(to the wordline Rate level.First power level can be higher than the second power level.

In another embodiment of the invention, the device for being used for data storage can be implemented as MRAM, and this is used to generate The device of power can be implemented as low voltage difference (LDO) adjuster, and the device for being used to provide different capacity level can be by reality It is now the device for selecting the first power level and the device for selecting the second power level.This is used to select the first power The device of level and for select the second power level device can be implemented as multiplexer, wherein the multiplexer in response to write life Make and select the first power level, and wherein the multiplexer selects the second power level in response to read command.

Another embodiment of the present invention may include a kind of method, and this method has the step of being used for data storage, for giving birth to The step of success rate and in response at least one of write order or read command to this be used for data storage the step of Wordline provides the step of different capacity level.

In further embodiment of the present invention, the step of write order causes this to be used to provide different capacity level, is to the word The step of line provides the first power level, and read command causes this to be used to provide different capacity level provides the second work(to the wordline Rate level.First power level can be higher than the second power level.

In further embodiment of the present invention, the step of this is used for data storage can by data storage in a mram come Realize, the step of this is used to generate power can be by generating power to realize via low voltage difference (LDO) adjuster, and this is used for There is provided different capacity level the step of can be implemented as be used for select the first power level the step of and for selecting the second power The step of level.This is used for the step of the first power level of selection and can pass through offer for the step of the second power level of selection Multiplexer realizes that wherein the multiplexer selects the first power level in response to write order, and wherein the multiplexer responds The second power level is selected in read command.

Each embodiment can be integrated at least one semiconductor element.

The medium of each embodiment may include the equipment that each embodiment can be integrated into, and the equipment, which is selected from, includes the following Group：Set top box, music player, video player, amusement unit, navigation equipment, communication equipment, personal digital assistant (PDA), fixed position data cell and computer.

Brief description

Accompanying drawing is provided to help that the embodiment of the present invention is described, and accompanying drawing is provided and is only used for explaining embodiment rather than right It is defined.

Fig. 1 is the rough schematic view of known MRAM wordline powers control program.

Fig. 2 is the timing diagram of the power control scheme of key diagram 1.

Fig. 3 is the rough schematic view of the MRAM wordline power control programs of disclosed embodiment.

Fig. 4 is the rough schematic view of the more detailed example for the embodiment for showing Fig. 3.

Fig. 5 is the timing diagram of the power control scheme of key diagram 3 and 4.

It is described in detail

Each aspect of the present invention is disclosed in below for the description of the specific embodiment of the invention and relevant accompanying drawing.Can be with Alternative embodiment is designed without departing from the scope of the present invention.In addition, well-known element will not be retouched in detail in the present invention State or will be removed in order to avoid falling into oblivion the correlative detail of the present invention.

Wording " exemplary " is used herein to mean that " being used as example, example or explanation ".Here depicted as " example Any embodiment of property " is not necessarily to be construed as advantageous over or surpassed other embodiment.Equally, term " various embodiments of the present invention " is simultaneously Not requiring all embodiments of the present invention all includes discussed feature, advantage or mode of operation.

Term used herein merely for description specific embodiment purpose, and be not intended as limit the present invention reality Apply example.As it is used herein, " one " of singulative, " certain " and "the" are intended to also include plural form, unless context is another Clearly dictate otherwise.It will also be understood that term " comprising ", " having ", "comprising" and/or " containing " indicate that institute is old as used herein The presence of feature, integer, step, operation, element, and/or the component stated, but it is not precluded from other one or more features, whole Number, step, operation, element, component and/or the presence of its group or addition.

In addition, many embodiments are described according to by the action sequence of the element execution by such as computing device.Will Recognize, various actions described herein can by special circuit (for example, application specific integrated circuit (ASIC)), by just by one Multiple computing devices programmed instruction or performed by combination of the two.In addition, these action sequences described herein It can be considered as to be embodied in completely in any type of computer-readable recording medium, be stored with once execution with regard to phase will be made The corresponding computer instruction set of the computing device functionality described here of association.Therefore, various aspects of the invention can To be embodied with several multi-forms, all these forms have all been contemplated to fall in the scope of subject content claimed It is interior.In addition, for each embodiment described herein, the corresponding form of any such embodiment can be described herein as example Such as " logic for being configured to perform described action ".

Integrated circuit (IC) described herein can be achieved in various applications, including mobile phone, hand-held personal communication System (PCS) unit, portable data units (such as personal digital assistant), the equipment for enabling GPS, navigation equipment, set top box, Music player, video player, amusement unit, fixed position data cell (such as meter reading equipment) or storage or retrieval number According to or computer instruction any other equipment, or its any combinations.Although Fig. 3-5 is illustrated according to the teaching of the disclosure IC, but the disclosure is not limited to the exemplary cell that these are explained.The presently disclosed embodiments be may be adapted for use at including active In any equipment of IC system (including memory and on-chip circuit system for testing and characterizing).

Apparatus and method disclosed above are commonly designed and are configured in the GDSII of storage on a computer-readable medium In GERBER computer documents.These files so be provided to manufacture processor, these manufacture processors be based on these text Part manufactures device.As a result the product obtained is semiconductor wafer, and it is then cut into semiconductor element and is packaged into partly Conductor chip.These chips then use in equipment described herein.

The disclosure describes the memory cell of the disclosed embodiments using term MRAM.Generic term MRAM is intended to wrap Any kind of MRAM of disclosed wordline power scheme, including but not limited to conventional MRAM, spin transfer can be used by including Torque magnetoresistive random access memory (STT-MRAM), spin transfer torque RAM (STT-RAM), spinning moment transfer magnetization are cut Change RAM (Spin-RAM) and spin momentum transfer (SMT-RAM).

The presently disclosed embodiments includes integrated circuit (IC) power generation module, and it can be realized as low voltage difference (LDO) electricity Press adjuster.It is grand that the IC of disclosed embodiment also includes MRAM.However, the feature of disclosed embodiment and operation are equally applicable In the self-support MRAM cell with internal power maker.Correspondingly, the operation grand to disclosed MRAM herein is all Description is equally applicable to the grand realizations for being changed to self-support MRAM cell of wherein MRAM.Similarly, herein to disclosed power Generation module and LDO operation are described the reality for being equally applicable to that wherein power generation module is internal power maker It is existing.

Turning now to the general view to associated operating environments, the disclosed embodiments are used as having various upper blocks (including to deposit Reservoir is grand) conventional IC a part.Conventional memory by pairs with create the various electronic building bricks of memory cell (for example, Transistor and capacitor) form, memory cell represents a data (0 or 1).Memory cell is aligned in columns and rows, row It is the dummy unit address of storage information with capable intersection point.Read and write-in information is by measuring or changing particular memory cell Electronic values at address and occur.

If IC memory macros include MRAM, power must be provided to the word line transistors of selected mram cell with from Selected mram cell reads data or writes data to selected mram cell.However, because read operation and write operation all pass through Make electric current pass through MRAM MTJ to perform, therefore read operation be present and upset the potentially possible of the data that are stored in MTJ Property.If for example, read current in amplitude similar to or greater than write current threshold value, read operation may have very big chance will upset MTJ logic state, the integrity of memory is thus set to degrade.(' 329 are special by previously described United States Patent (USP) No.7,742,329 Profit) first voltage is supplied to for write operation by word line transistors by offer and the first electricity will be less than during read operation The second voltage of pressure is supplied to MRAM circuit systems and the control of word line transistors to solve this problem in that.More specifically, ' 329 Patent provides the word line driver circuit system 432 shown in Fig. 4 A, 4B, 7 and 8.WL shown in Fig. 7 of the patent of ' 329 drives Dynamic device 432 includes selection logic 710, is configured to together with controlled switching devices 720,730, the controlled switching devices 720,730 In response to write enable signal wr_en and select first voltage Vpp for perform write operation, and in response to read enable signal Rd_en and select second voltage Vdd for perform read operation.

The presently disclosed embodiments includes providing different capacity level to wordline grand MRAM and also optimization MRAM is mono- simultaneously The circuit of the size and cost of member, system and method.Outer read/write order controls and indicates that existing IC power generation module is being read The first power level is supplied to wordline during operation, and the second work(of the first power level is will differ from during write operation Rate level is supplied to wordline.The existing power generation module of disclosed embodiment can be implemented as IC low voltage difference (LDO) voltage Adjuster.Because conventional LDO generally includes to allow the feature that its output power levels changes according to adjustment code, thus it is disclosed LDO can be by being configured to change its wordline power level according to outer read/write order come economically real by the LDO of embodiment It is existing.Using the parameter described in the disclosure, person of ordinary skill in the relevant can be embodied directly in hardware, in by computing device Software module in or realize in its any combinations LDO configurations described herein.In conventional IC technology, LDO is piece The Voltage Reference that upper piece (such as numeral, simulation and RF) offer is stablized.Preferable LDO inputs unregulated electricity from voltage source Pressure, and the constant output voltage of substantially noiseless or burr is provided.A LDO quality factor are dropout voltages.Pressure difference electricity Pressure is that output voltage is maintained to the minimum voltage across adjuster needed for correct level.Less power supply is needed compared with low drop voltage Voltage simultaneously causes the power of adjuster internal dissipation less.

Thus, it is complete using existing external command signal and existing power generation module under the disclosed embodiments Into the different wordline power level needed for read/write operation, thereby eliminate via MRAM it is grand on SWITCHING CIRCUITRY supply Answer the cost and die size needed for different wordline power level.The example of the known wordline power control program based on switch Described below in conjunction with Fig. 1 and 2.

Fig. 1 is the rough schematic view of the IC with known MRAM wordline power control programs.Fig. 2 is the power of key diagram 1 The timing diagram of the operation of control program.As shown in fig. 1, integrated circuit (IC) 10 includes low voltage difference (LDO) 20 and magnetic resistance is random Access memory (MRAM) 30.LDO 20 to MRAM 30 provide stable output voltage (for example, wordline write voltage-VWL_WR, With core supply voltage-VDDX), wherein having between the voltage level for entering LDO 20 voltage level and leaving LDO 20 There is alap difference (that is, " low voltage difference ").LDO 20 includes the divider electricity formed by resistive element R1, R2, R3 and R4 Road system, these resistive elements are coupled to the voltage follower circuit system formed by operational amplifier 22,24.Bleeder circuit System R1-R4 produces two voltages VWL_WR and VDDX, and each of which is input voltage (Vio) and negative supply or ground voltage (Vss) fraction of the difference between.VWL_WR is caused by bleeder circuit system R1-R4 first node 26, and VDDX is caused by bleeder circuit system R1-R4 section point 28.Operational amplifier 22 is just connecing at it at (+) terminal VWL_WR is received as input voltage, and operational amplifier 24 receives VDDX as input voltage at it just at (+) terminal.From fortune Calculate voltage of the output voltage of amplifier 22,24 substantially respectively equal at the positive input terminal of each operational amplifier.By This, operational amplifier 22,24 each be configured as by its respective output signal VWL_WR and VDDX with it, just (+) is defeated Enter the voltage follower that the voltage received at terminal is kept apart, thus draw considerably less power from its signal source and avoid " adding Carry " effect.

Continue Fig. 1 rough schematic view, MRAM 30 includes power switch circuit system 32, command decoder circuit system 34th, MTJ 36, transistor 46, bit line (BL), wordline (WL) and source line (SL).MRAM 30 receives stable and isolation VWL_WR With VDDX power signals as the input to power switch circuit system 32.VDDX act on for read operation provide power level with And the dual-use function of the core power signal as memory macro.Correspondingly, VDDX is additionally provided to command decoder circuit system System 34 (and IC 10 other assemblies-be not shown).Command decoder circuit system 34 is in response to entering command decoder electricity The control signal (CS) of road system 34 and write and enable (WE) signal and generate read/write command 48.Power switch circuit system 32 connects Receive the read/write command 48 from command decoder circuit system 34.

Fig. 2 is the timing diagram 60 of the operation of the known wordline power control program shown in key diagram 1.Specifically, when Sequence Figure 60 shows MTJ 36 behavior and some signals (CS, WE, VWL_WR, VDDX, WL) during write and read operates.Sequential Figure 60 transverse axis represents the time, and the longitudinal axis of timing diagram 60 represents the power level of signal listed on the left of the figure.Wordline work( Rate level VWL_WR and VDDX can actively be driven in some times and not driven actively in other times.When signal quilt When actively driving, the signal is depicted as solid line.When signal is not driven actively, it can be drawn high or drawn by resistor It is low, or can be allowed to be floating.When not being driven actively signal, the timing diagram is portrayed as dotted line.It is if empty Line is high or is low, then can be assumed that and draw high or drag down the state that resistor is just maintaining the signal.

Referring now to Fig. 2 timing diagram and Fig. 1 both rough schematic view, MRAM 30 read/write operation is by command signal CS and WE is enabled.Negative/no-voltage on both CS and WE indicates command decoder circuit system 34 via read/write command 48 Disable power switch circuit system 32, and WL power levels remain it is negative/zero.For write operation, above carried in both CS and WE For positive pulse, it indicates that command decoder circuit system 34 enables power switch circuit system 32 simultaneously via read/write command 48 VWL_WR signals are connected to WL and reach the scheduled time.Thus, WL is changed into and VWL_WR identicals in the predetermined amount of time Power level, and write operation 62 is performed at MTJ 36.For read operation, positive pulse is provided on CS and WE remain zero/ Negative, it indicates command decoder circuit system 34 via read/write command 48 to enable power switch circuit system 32 and by VDDX It is connected to WL and reaches the scheduled time.Thus, WL be changed into the predetermined amount of time with VDDX identical power levels, and Read operation 64 is performed at MTJ 36.VWL_WR and VDDX is in different capacity level, and correspondingly, during write operation on WL Power level is different from the power level during read operation on WL.

Fig. 3 is the rough schematic view of the MRAM wordline power control programs of disclosed embodiment.Fig. 3 is illustrated with power The IC 70 of generation module 72 and MRAM grand 90.Power generation module 72 provides the defeated of stabilization to MRAM grand 90 mram cell 91 Go out voltage (for example, VWL), wherein having alap difference between input voltage and output voltage.Power generation module 72 include voltage input circuit system 74 and data selector 76.Optionally, power generation module 72 can further comprise every From circuit system 78.In addition to read/write control function is provided, control signal (CS) and writes and enable (WE) signal and be also supplied to Data selector 76, data selector 76 are configured to CS and WE controlling letter with the external power of rate of doing work generation module 72 Number.Using the parameter described in the disclosure, person of ordinary skill in the relevant can be embodied directly in hardware, in by computing device Software module in or realize in its any combinations data selector 76.Voltage input circuit system 74 is to data selector 76 provide first voltage level 82 and second voltage level 84.In order to which clearly read operation and write operation are differentiated, the first electricity Voltage level 82 is different from second voltage level 84.Under external command signal CS and WE control, data selector 76 selects simultaneously Export first voltage level 82 or second voltage level 84.More specifically, under outside read/write command CS and WE control, number Selected according to selector 76 in the case of CS and WE instruction write operations and export first voltage level 82, or indicated in CS and WE Selected in the case of read operation and export second voltage level 84.Optional isolation circuit system 78 receives to be selected from data The single output voltage of device 76 simultaneously forwards it to the WL of mram cell 91.Output from isolation circuit system 78 is substantially first-class In its input voltage, the input voltage is received from data selector 76.Thus, isolation circuit system 78 outputs it signal Input and be isolated with it, thus draw considerably less power from input signal source and avoid " loading " effect.Mram cell 91 passes through Stable and isolation VWL signals are received by wordline (WL).

Fig. 4 is the more detailed example of the disclosed embodiment explained in Fig. 3.As shown in Figure 4, Fig. 3 power generator Module 72 can be implemented as LDO 80.Because conventional LDO generally includes to allow its output power levels according to for example adjusting code The feature of change, therefore the LDO 80 of disclosed embodiment can be by the way that conventional LDO to be configured to be changed according to outer read/write order Its power output is economically realized.Voltage input circuit system 74 can be implemented as with resistive element R5, R6, R7, R8, The divider of one node 100 and section point 102.First node 100 produces VWL_WR, and section point 102 produces VDDX. VWL_WR and VDDX is individually the fraction of the difference between input voltage (Vio) and negative supply or ground voltage (Vss).In order to clear Chu read operation and write operation are differentiated, resistive element R5-R8 value is chosen so that first voltage level 100 is different from Second voltage level 102.Data selector 76 can be implemented as multiplexer circuit 104 and buffer 110.Buffer 110 receives Outer read/write command signal CS and WE, and the selection that selection signal 112 is exported to multiplexer circuit 104 inputs (SEL).It is multiple VWL_WR is received an input and receive VDDX in the second input with device circuit 104.If the instruction of selection signal 112 is write Operation, then multiplexer SEL inputs select VWL_WR power levels and provide VWL_WR power levels in multiplexer output, and such as Fruit selection signal 112 indicates read operation, then multiplexer SEL inputs select VDDX power levels and provided in multiplexer output VDDX power levels.Isolation circuit system 78 can be implemented as having the first operational amplifier 106 and the second operational amplifier 108 Voltage follower circuit.Operational amplifier 106 receives multiplexer output voltage (VWL) in its plus end (+) input, and transports Calculate amplifier 108 its just (+) terminal input receive section point 102 voltage (VDDX).Each operational amplifier 106, 108 are in voltage-follower arrangement, to cause the output voltage of each operational amplifier to be substantially equal to its plus end (+) input Voltage.Thus, voltage follower operational amplifier 106,108 outputs it signal and its plus end input signal is isolated, by This draws considerably less power from input signal source and is avoided " loading " effect.

Continue Fig. 4 rough schematic view, MRAM grand 90 includes mram cell 91, MTJ 92, word line transistors 94, bit line (BL), wordline (WL) and source line (SL).MRAM grand 90 further comprises command decoder circuit system 96, and it receives storage core The core power supply (VDDX) of piece, control signal (CS) and write and enable signal (WE) to control MRAM grand 90 various operations, including Read operation and write operation.MRAM grand 90 receives stable and isolation VWL power signals on WL.Known to shown in Fig. 1 MRAM 30 is contrasted, and disclosed embodiment eliminates provides relatively large and expensive power switch circuit on MRAM is grand System (power switch circuit system 32, read/write command 48 in Fig. 1) controls the needs for the power level for putting on WL.

Fig. 5 is the timing diagram 120 of the operation of the MRAM wordline power control programs shown in key diagram 3 and 4.It is specific and Speech, timing diagram 120 show MTJ 92 behavior and some signals (CS, WE, VWL, VDDX, WL) during write and read operates. The transverse axis of timing diagram 120 represents the time, and the longitudinal axis of timing diagram 120 represents the power level of signal listed on the left of the figure. For power line VWL and VDDX, the power level of these signals can actively be driven in some times and in other times not Actively driven.When signal is actively driven, the signal is depicted as solid line.When signal is not driven actively, It can be drawn high or dragged down by resistor, or can be allowed to be floating.When not being driven actively signal, the timing diagram will It is portrayed as dotted line.If dotted line is high or is low, it can be assumed that and draw high or drag down the state that resistor is just maintaining the signal.

Referring now to both Fig. 5 timing diagram and Fig. 3 and 4 rough schematic view, MRAM grand 90 read/write operation is by CS Controlled with WE.The data selector 76 of negative/no-voltage indicated horsepower generation module 72 (or LDO 80) on both CS and WE Output it voltage and be pulled to negative/null value, WL power is thus pulled to negative or zero.For write operation, provided on both CS and WE Positive pulse, it indicates that command decoder circuit system 96 initiates grand to MRAM 90 read operation.Positive pulse on both CS and WE The data selector 76 of also indicated horsepower generation module 72 outputs it the power level that voltage is pulled at first node 100, by VWL is pulled to VWL_WR and reaches the scheduled time by this.Thus, the power level of the VWL on WL is changed into the predetermined amount of time With VWL_WR identical power levels, and concomitantly at MTJ 92 perform write operation 122.For read operation, above carried in CS For positive pulse WE remain it is negative/zero, it indicates that command decoder circuit system 96 initiates grand to MRAM 90 read operation.Work as WE Remain it is negative/zero when positive pulse also indicated horsepower generation module 72 on CS data selector 76 output it voltage and be pulled to Power level at section point 102, VWL is thus pulled to VDDX and reaches the scheduled time.Thus, VWL power level is described Be changed into predetermined amount of time with VDDX identical power levels, and concomitantly at MTJ 92 perform read operation 124.Note Meaning, VWL are in the power level of first node 100 during write operation 122, and are in section point during read operation 124 102 power level, the power level of section point 102 are different from the power level of first node 100.

It may be noted here that rise and the power level being lowered on WL single line mean that there will be fringe time 126 from a power level by WL to move to another power level.Correspondingly, needed between write operation 122 and read operation 124 Stand-by period 128 with allow WL power levels change.Stand-by period 128 can be by the data selector 76 in Fig. 3 or by Fig. 4 Buffer 110 provide.

Thus, it is complete using existing external command signal and existing power generation module under the disclosed embodiments Into the different wordline power level needed for read/write operation, thereby eliminate and opened via MRAM is grand relatively large and expensive Circuit system is closed to supply cost and die size needed for different wordline power level.

Skilled artisans will appreciate that any one of various different technologies and skill can be used for information and signal Represent.For example, data, instruction, order, information, signal, position (bit), symbol and chip that above description may be quoted from the whole text It can be represented by voltage, electric current, electromagnetic wave, magnetic field or magnetic particle, light field or light particle or its any combinations.

In addition, skilled artisans will appreciate that, patrolled with reference to the various illustratives that the embodiments described herein describes Volume block, module, circuit and algorithm steps can be implemented as electronic hardware, computer software, or both combination.For clearly This interchangeability of hardware and software is explained, various illustrative components, block, module, circuit and step are with its work(above The form of energy property makees vague generalization description.Such feature is implemented as hardware or software depends on concrete application and application In the design constraint of total system.Technical staff can realize described function for every kind of application-specific with different modes Property, but such realize that decision-making should not be interpreted to cause departing from the scope of the present invention.

With reference to the embodiments described herein describe method, sequence and/or algorithm can be embodied directly in hardware, in by Embodied in the software module that reason device performs or in combination of the two.Software module can reside in RAM memory, flash memory, Institute in ROM memory, eprom memory, eeprom memory, register, hard disk, removable disk, CD-ROM or this area In the storage medium for any other form known.Exemplary storage medium be coupled to processor with enable the processor from/to The storage medium reading writing information.Alternatively, storage medium can be integrated into processor.

Correspondingly, embodiments of the invention may include computer-readable medium, and the computer-readable medium is embodied for controlling Make to the method for MRAM WL power.Correspondingly, the present invention be not limited to explained example and it is any be used for perform text institute Functional means of description are included in an embodiment of the present invention.

Although the illustrative embodiment of the present invention is shown disclosed above, it is noted that can make wherein each The scope of the present invention that kind is changed and change defines without departing from such as appended claims.According to described herein hair Function, step and/or the action of the claim to a method of bright embodiment need not be performed by any certain order.In addition, although The key element of the present invention is probably to be described or claimed with odd number, but plural number and contemplated, unless explicitly State to be defined in odd number.

Claims (14)

1. one kind is controlled to the device of the wordline power of magnetoresistive RAM (MRAM), including：

Memory module including magnetoresistive RAM (MRAM) and command decoder, the command decoder are used to connect Write order and read command are received to control the write operation of the MRAM and read operation；And

Power generation module, it includes：

Buffer, it is used to receive write order and read command and provides the stand-by period；

Selector, it is coupled to the buffer and is not couple to the command decoder, and the selector is configured at least Different capacity level is provided to the wordline of the MRAM in response to write order and read command, wherein the write order causes the choosing Select device and provide the first power level to the wordline of the MRAM；And the read command causes the selector to described The MRAM wordline provides the second power level, wherein the selector is further configured to selecting first power The stand-by period is applied between level and selection second power level；And

Isolation circuit, it is configured to the output coupling of the selector to the wordline.

2. device as claimed in claim 1, it is characterised in that：

The MRAM includes spin transfer torque MRAM；And

First power level is higher than second power level.

3. device as claimed in claim 1, it is characterised in that the power generation module includes low voltage difference (LDO) adjuster.

4. device as claimed in claim 1, it is characterised in that：

The selector includes multiplexer；

The multiplexer selects first power level in response to the write order；And

The multiplexer selects second power level in response to the read command.

5. one kind control extremely includes the wordline work(of the memory module of magnetoresistive RAM (MRAM) and command decoder The method of rate, including：

Write order and read command are received at the command decoder to control the write operation of the MRAM and read operation；

The buffer that write order is coupled in power generation module；

The buffer that read command is coupled in the power generation module；

The stand-by period is provided by the buffer；

Control the selector of the power generation module at least responsive to the write order and the read command to the MRAM's Wordline provides different capacity level, wherein the write order causes the selector to provide first to the wordline of the MRAM Power level, and the read command causes the selector to provide the second power level to the wordline of the MRAM, its Described in selector coupled to the buffer and the command decoder is not couple to, wherein the selector is further matched somebody with somebody It is set to and is selecting to apply the stand-by period between first power level and selection second power level；And

Using isolation circuit by the output coupling of the selector to the wordline.

6. method as claimed in claim 5, it is characterised in that：

The MRAM includes spin transfer torque MRAM；And

First power level is higher than second power level.

7. method as claimed in claim 5, it is characterised in that the power generation module includes low voltage difference (LDO) adjuster.

8. method as claimed in claim 5, it is characterised in that：

The selector includes multiplexer；

The multiplexer selects first power level in response to the write order；And

The multiplexer selects second power level in response to the read command.

9. one kind is controlled to the equipment of the wordline power of magnetoresistive RAM (MRAM), including：

The device for data storage including magnetoresistive RAM (MRAM) and command decoder；

For receiving write order and read command at the command decoder to control the write operation of the MRAM and read operation Device；

For the device for the buffer that write order is coupled in power generation module；

For the device for the buffer that read command is coupled in the power generation module；

For providing the device of stand-by period by the buffer；

For in the power generation module at least responsive to write order and read command to the device for data storage Wordline the device of different capacity level is provided, wherein the write order causes the device for being used to provide different capacity level There is provided the first power level to the wordline, and the read command cause the device for being used to providing different capacity level to The wordline provides the second power level, wherein the device for being used to providing different capacity level coupled to the buffer and The command decoder is not couple to, wherein the device for being used to provide different capacity level is further configured to selecting The stand-by period is applied between first power level and selection second power level；And

For using device of the isolation circuit by the output coupling of the selector to the wordline.

10. equipment as claimed in claim 9, it is characterised in that：

The device for data storage includes spin transfer torque MRAM；And

First power level is higher than second power level.

11. equipment as claimed in claim 9, it is characterised in that the device for being used to generate power includes low voltage difference (LDO) Adjuster.

12. equipment as claimed in claim 9, it is characterised in that the device for being used to provide different capacity level includes：

For selecting the device of first power level in response to the write order；And

For selecting the device of second power level in response to the read command.

13. equipment as claimed in claim 12, it is characterised in that the device bag for being used to select first power level Include multiplexer.

14. equipment as claimed in claim 12, it is characterised in that the device bag for being used to select second power level Include multiplexer.