CN104601395B - Intelligent record analysis system based on substation's digital communication - Google Patents
Intelligent record analysis system based on substation's digital communication Download PDFInfo
- Publication number
- CN104601395B CN104601395B CN201410730990.4A CN201410730990A CN104601395B CN 104601395 B CN104601395 B CN 104601395B CN 201410730990 A CN201410730990 A CN 201410730990A CN 104601395 B CN104601395 B CN 104601395B
- Authority
- CN
- China
- Prior art keywords
- module
- port
- character
- network
- encryption
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004891 communication Methods 0.000 title claims abstract description 22
- 230000008054 signal transmission Effects 0.000 claims abstract description 36
- 239000011159 matrix material Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 14
- 238000013144 data compression Methods 0.000 claims description 12
- 230000009466 transformation Effects 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000007906 compression Methods 0.000 claims description 3
- 230000006835 compression Effects 0.000 claims description 3
- 238000013500 data storage Methods 0.000 claims description 3
- 238000013507 mapping Methods 0.000 claims description 3
- 238000004364 calculation method Methods 0.000 claims 1
- 230000006870 function Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 6
- 238000012544 monitoring process Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 238000007726 management method Methods 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000009440 infrastructure construction Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Landscapes
- Storage Device Security (AREA)
Abstract
Intelligent record analysis system based on substation's digital communication belongs to record analysis technical field more particularly to a kind of intelligent record analysis system based on substation's digital communication.The present invention provides a kind of safe, good compatibility, the intelligent record analysis system based on substation's digital communication that work efficiency is high.The present invention is including being primary module, first serial module, second serial module, first network module, second network module, power module, human-machine exchange module, memory module and encrypting module, the signal transmission port of its structural feature primary module signal input port with first serial module respectively, the signal output port of second serial module, the signal output port of first network module, the signal input port of second network module, the signal transmission port of human-machine exchange module, the signal transmission port of encrypting module is connected, the signal transmission port of encrypting module is connected with the signal transmission port of memory module.
Description
Technical Field
The invention belongs to the technical field of record analysis, and particularly relates to an intelligent record analysis system based on substation digital communication.
Background
With the infrastructure construction and old equipment transformation of the national power grid, the intelligentization of primary equipment and the networking of secondary equipment of the transformer substation are gradually promoted, the digital/intelligent transformer substation test project constructed based on IEC61850 is emerging at home, and the traditional secondary equipment interface is gradually replaced by the network interface. How to verify the network interface of the intelligent substation and the communication interface and system configuration of the traditional substation, how to realize the monitoring of the abnormity and fault of the automation system, provide visual tools for network communication of operation and maintenance personnel, and assist the operation and maintenance personnel in correctly positioning the fault reason, has become the problem that is urgently solved by the digital/intelligent substation.
Disclosure of Invention
Aiming at the problems, the invention provides an intelligent record analysis system based on the digital communication of the transformer substation, which has high safety, good compatibility and high working efficiency.
The main module comprises a signal input port, a signal output port, a signal input port, a signal transmission, The power input port of the first network module, the power input port of the second network module, the power input port of the man-machine exchange module, the power input port of the storage module and the power input port of the encryption module are connected.
As a preferred scheme, a signal input port of the second serial port module is respectively connected with a signal output port of a serial port channel and a signal output port of an integrated acquisition device (a comprehensive automatic communication management device of a transformer substation can be adopted), a signal transmission port of the serial port channel is connected with a signal transmission port of the integrated acquisition device, the signal transmission port of the integrated acquisition device is connected with a signal transmission port of a data network switch, and the signal output port of the data network switch is connected with a signal input port of the first network module; the signal output port of the first serial port module is connected with the signal input port of the master station, and the signal output port of the second network module is connected with the signal input port of the master station.
As another preferable scheme, the main module of the present invention uses an STM32F103VCT6 chip.
As another preferred scheme, the first network module and the second network module of the invention adopt a DM9000 chip U4, pins 3 and 4 of U4 are connected to a signal output port of a data network switch through a network transformer, and pins 7 and 8 of U4 are connected to a signal input port of a master station through a network transformer; u4's 3 feet link to each other with resistance R16 one end, the R16 other end respectively with resistance R15 one end, electric capacity C17 one end links to each other, the R15 other end links to each other with U4's 4 feet, the C17 other end, the ground wire, electric capacity C18 one end links to each other, the C18 other end, resistance R17 one end, resistance R18 one end links to each other, the resistance R17 other end links to each other with U4's 8 feet, the resistance R18 other end links to each other with U4's 7 feet.
As another preferred scheme, the first serial port module and the second serial port module of the present invention use a MAX232 chip U3, pin 14 of U3 is connected to a signal input port of the master station and one end of the first 3K resistor, pin 13 of U3 is connected to a signal output port of the serial port channel and a signal output port of the comprehensive acquisition device, and one end of the second 3K resistor, the other end of the first 3K resistor is connected to an anode of LED D3, a cathode of D3, a ground line, and a cathode of LED D4, and an anode of D4 is connected to the other end of the second 3K resistor.
As another preferred scheme, the data storage module of the present invention employs an AT24C04 chip, wherein a pin 5 of the AT24C04 chip is connected to one end of a resistor R2 and a signal transmission port of the encryption module, a pin 6 of the AT24C04 chip is connected to one end of a resistor R1 and a signal transmission port of the encryption module, and the other end of the resistor R1 and the other end of the resistor R2 are connected to a power output port of the power module.
As another preferable scheme, the encryption module of the present invention uses an LKT4200 chip.
As another preferred scheme, the invention firstly collects the electric power network protocol through the network module and the data network switch through the network cable connection, and the serial port module is connected to the receiving and sending of the serial port channel through the twisted pair to respectively collect the electric power serial port messages; secondly, the collected messages are analyzed and sorted by the protocol analysis module of the main module, then data compression is carried out by the data compression module of the main module, and the compressed data is transmitted to the storage module for storage after passing through the encryption module; extracting data in the storage module and transmitting the data to the master station through a forwarding module of the main module, wherein the data is encrypted by the encryption module; the power module controls the power supply to be stopped when each module does not work.
Secondly, the power module firstly provides output voltage for each module; collecting output voltage and current, and judging the stability of the voltage and the current; if the current or the voltage is unstable, the output voltage is adjusted to be stable, and if the adjustment is unsuccessful, an alarm is sent to indicate that the voltage and the current have problems.
The data compression module for data compression comprises the following steps.
1) And sorting the symbols according to the sequence of the occurrence probability of the symbols.
2) The two symbols with the smallest probability are combined into a node P1.
3) And (3) repeating the step (2) to obtain nodes P2, P3, P4 and P …, wherein PN forms a tree, and the PN is called a root node.
4) Starting from the root node PN to the leaves of each symbol, from top to bottom, the subscripts are 0 (upper branch) and 1 (lower branch), the probability is 1 as large, and the probability is 0 as small.
5) The code for each symbol is written separately from the root node PN along the branch to each leaf.
The compression formula is as follows.
。
In addition, the encryption process of the encryption module of the present invention operates on a Byte matrix of 4 × 4, the initial value of which is a plaintext block (one element size in the matrix is a Byte in the plaintext block). during encryption, each round of encryption (except the last round) includes the following 4 steps.
1) Each byte in the matrix is subjected to XOR operation with the key of the next round; each subkey is generated by a key generation scheme.
2) Each byte is replaced by the corresponding byte in a look-up table manner through a non-linear replacement function.
3) Each row in the matrix is cyclically shifted.
4) The four bytes of each column are mixed using a linear transformation.
Step 4) is omitted in the last encryption round) and replaced with another step 1).
The encryption module is transformed in the following manner.
1) Each byte of the input or intermediate state is mapped to another byte; the mapping method comprises the following steps: the high 4 bits of the input byte are taken as row values and the low 4 bits as column values, and then the elements corresponding to the row and column are taken out as output.
2) The column aliasing transformation is performed by the method.
。
Wherein,the number representation within { x } is a byte; expressed as a matrix。
3) And (4) line shift conversion.
On the row of the intermediate state, row 0 is stationary, row 1 is shifted left by 1 byte cyclically, row 2 is shifted left by 2 bytes cyclically, and row 3 is shifted left by 3 bytes cyclically.
4) Round key plus transform.
Each column of the input or intermediate state S is associated with a key word W i]Performing a bitwise exclusive-or, wherein,generated from the original key by key expansion.
The protocol analysis module scans the matching character string from right to left from the first character at the rightmost end of the matching string, and moves the pattern string to the right by using two rules until matching is realized once mismatching occurs; the two rules are a good suffix rule and a bad character rule.
Good suffix rules.
Assuming that there is no match at the character x [ i ] = a of the pattern string, the character y [ i + j ] = b of the pattern string, i.e., x [ i +1.. m-1] = y [ i + j +1.. j + m-1] = u, and x [ i ] = y [ i + j ]; there are two situations that occur.
1) If a good suffix u is also included at other positions after x and the character x [ i-n ] = c adjacent to u at the left end is not equal to x [ i ] = a, then u occurring at other positions after x is aligned with u in y and x [ i-n ] is compared with y [ i + j ].
2) If no string identical to u occurs then finding the longest prefix u of x identical to the suffix of u shifts x to the right, making v correspond to the suffix of u in y.
Bad character rules.
1) During scanning from right to left, x [ i ] is found to be different from y [ j ], if one character x [ k ] is the same as y [ i ] and k < i exists in x, x is directly shifted to the right to align x [ k ] with y [ i ], and then matching is performed from right to left.
2) If there are no characters in x that are identical to y i, then the first character of x is directly aligned with the next character of y i and the comparison is made from right to left.
And when the text character string is not matched with the mode character, taking the larger of the deviation value calculated by the function bad character rule and the good suffix rule.
1) If the array storing the bad character rule is BadChar [ ], BadChar [ c ] = min { i |1 ≦ i ≦ m-1 and x [ m-1-i ] = c }, if c does not appear in the pattern character, BadChar [ c ] m (m is the length of x).
2) If the array in which the suffix rule is stored is GoodSuffix [ ], suff [ i ] = max { k | y [ i-k +1.. i ] = x [ m-k.. m-1], 1 ≦ i < m }; i.e., suff is the longest general suffix for P [0.. i ] and T; calculating the suff array makes calculating the GoodSuffix function concise GoodSuffix [ m-1-suff [ i ] ] = m-1-i.
Finally, the maximum value of BadChar [ c ] and GoodSuffix [ c ] is taken.
Secondly, when the text character string is not matched with the mode character, the Dist [ ] array is initialized through a function Dist (x), and then the character string is matched; dist (x) -m + j is the distance of right shift of Pattern calculated according to the text character x corresponding to the current sample character P [ j ] and the relationship between x and m characters of the sample P [1 … m ] when a matching failure occurs once; the definition domain of the Dist (x) function is the character table Σ, and the value domain is {1, …, m }.
。
Where j = Max { k | P k = x,1 ≦ k < m }.
The invention has the beneficial effects.
The signal transmission port of the encryption module is connected with the signal transmission port of the storage module, so that the uploaded data is ensured to be safe and reliable, and the data is prevented from being stolen by people.
The power protocol receiving device comprises a first serial port module, a second serial port module, a first network module and a second network module, supports multiple ports to receive, can physically realize interconnection and intercommunication between a serial port and a network port access device, and then collects, analyzes, compresses, stores and uploads a power protocol.
The invention has high integration level, good compatibility, small volume and various functions, can carry out online monitoring on network communication data of a transformer substation of an electric power system, carries out online alarm monitoring on network communication faults and abnormity, realizes rapid identification of channel system and equipment faults, shortens emergency repair time, saves labor and material cost, and greatly improves working efficiency, thereby improving economic benefit, management level and working efficiency of the operation of the electric power dispatching system.
Drawings
The invention is further described with reference to the following figures and detailed description. The scope of the invention is not limited to the following expressions.
Fig. 1 is a schematic block diagram of the circuit of the present invention.
Fig. 2 is a schematic circuit diagram of the power module of the present invention.
Fig. 3 is a circuit schematic of the network module of the present invention.
Fig. 4 is a schematic circuit diagram of a serial module of the present invention.
FIG. 5 is a schematic circuit diagram of a memory module of the present invention.
Fig. 6 is a circuit schematic of an encryption module of the present invention.
FIGS. 7 and 8 are schematic diagrams of the good suffix rule of the present invention.
FIGS. 9 and 10 are schematic diagrams of the bad character rule of the present invention.
Detailed Description
As shown in the figure, the invention comprises a main module, a first serial port module, a second serial port module, a first network module, a second network module, a power supply module, a man-machine exchange module, a storage module and an encryption module, and is structurally characterized in that a signal transmission port of the main module is respectively connected with a signal input port of the first serial port module, a signal output port of the second serial port module, a signal output port of the first network module, a signal input port of the second network module, a signal transmission port of the man-machine exchange module and a signal transmission port of the encryption module, the signal transmission port of the encryption module is connected with a signal transmission port of the storage module, a power output port of the power supply module is respectively connected with a power input port of the main module, a power input port of the first serial port module, a power input port of the second serial port module, and the power input port of the second network module, the power input port of the man-machine exchange module, the power input port of the storage module and the power input port of the encryption module are connected.
The signal input port of the second serial port module is respectively connected with the signal output port of the serial port channel and the signal output port of the comprehensive acquisition device, the signal transmission port of the serial port channel is connected with the signal transmission port of the comprehensive acquisition device, the signal transmission port of the comprehensive acquisition device is connected with the signal transmission port of the data network switch, and the signal output port of the data network switch is connected with the signal input port of the first network module; the signal output port of the first serial port module is connected with the signal input port of the master station, and the signal output port of the second network module is connected with the signal input port of the master station.
The main module adopts an STM32F103VCT6 chip.
The first network module and the second network module adopt a DM9000 chip U4, pins 3 and 4 of a U4 are connected with a signal output port of a data network switch through a network transformer, and pins 7 and 8 of a U4 are connected with a signal input port of a master station through the network transformer; u4's 3 feet link to each other with resistance R16 one end, the R16 other end respectively with resistance R15 one end, electric capacity C17 one end links to each other, the R15 other end links to each other with U4's 4 feet, the C17 other end, the ground wire, electric capacity C18 one end links to each other, the C18 other end, resistance R17 one end, resistance R18 one end links to each other, the resistance R17 other end links to each other with U4's 8 feet, the resistance R18 other end links to each other with U4's 7 feet. The DM9000 is a fully integrated and cost-effective, single chip fast ethernet MAC controller. It has a general processing interface, an 10/100M adaptive PHY and SRAM with 4K DWORD values. Its purpose is to support the tolerance of 3.3V and 5V in low power consumption and high performance process, and the DM9000 also provides a media independent interface to connect all home phone line network devices or other transceivers that provide the function of supporting the media independent interface. The DM9000 supports 8-bit, 16-bit and 32-bit interfaces to access internal memory to support different processors. The DM9000 physical protocol layer interface fully supports the use of 10MBps class 3, class 4 and class 5 unshielded twisted pair and 100MBps class 5 unshielded twisted pair. This is fully compliant with the IEEE 802.3u specification. Its auto-coordination function will automatically complete the configuration to best fit its line bandwidth. IEEE 802.3x full duplex flow control is also supported. The DM9000 is very simple in this work, so that a user can easily port drivers under any system.
The first serial port module and the second serial port module adopt MAX232 chips U3, pins 14 of U3 are respectively connected with a signal input port of a main station and one end of a first 3K resistor, pins 13 of U3 are respectively connected with a signal output port of a serial port channel and a signal output port of a comprehensive acquisition device, one end of a second 3K resistor is connected, the other end of the first 3K resistor is connected with an anode of an LED D3, a cathode of the LED 3, a ground wire and a cathode of the LED D4 are connected, and an anode of the D4 is connected with the other end of the second 3K resistor. The serial port access module is used for collecting field serial data streams, selects a single power supply level conversion chip MAX232 chip specially designed for RS-232 standard serial ports by American trusted (MAXIM) company, and supplies power by using a +5v single power supply. The MAX232 chip line driver/receiver is designed for EIA/TIA-232E and V.28/V.24 communication interfaces, especially for applications that cannot provide a 12V power supply. These devices are particularly suited for battery powered systems because their low power off mode can reduce power consumption to within 5 uW. The MAX232 chip requires no external components and is recommended for applications where the printed circuit board area is limited. The method is characterized in that: the on-chip charge pump meets all RS-232C technical standards, only needs a single +5V power supply to supply power, has the capabilities of boosting voltage and reversing voltage polarity, can generate +10V and-10V voltages V +, V-, and has low power consumption, typical supply current of 5mA, 2 RS-232C drivers integrated inside, high integration level and minimum off-chip capacitance of 4 capacitors.
The data storage module adopts an AT24C04 chip, a pin 5 of the AT24C04 chip is respectively connected with one end of a resistor R2 and a signal transmission port of the encryption module, a pin 6 of the AT24C04 chip is respectively connected with one end of a resistor R1 and a signal transmission port of the encryption module, and the other end of the resistor R1, the other end of the resistor R2 and a power supply output port of the power supply module are connected. AT24C04 is 2KB of Ateml company and gets electrically erasable memory chip, adopts two-wire serial bus and singlechip communication, and the voltage can reach 2.5V AT the lowest, and rated current is 1mA, and quiescent current 10uA (5.5V), and data in the chip can be preserved for 100 years under the circumstances of outage, and adopt 8 foot's DIP encapsulation, convenient to use. In short, the AT24C02 is a chip that stores data in the event of a sudden power loss, i.e., a power-down memory chip.
The encryption module adopts an LKT4200 chip. The LKT 420032-bit high-end encryption IC is an anti-piracy encryption chip with the highest performance in the current industry, the chip adopts a 32-bit CPU (an intelligent card chip for obtaining EAL5+ with the highest global security level) and 10KRAM, supports ISO7816 and UART communication, and has the highest communication rate of nearly 1 Mbps; the user program storage capacity can be up to 420 kbytes. The speed greatly surpasses that of a common 8-bit or 16-bit encryption chip while the encryption is carried out at an ultra-high security level.
Firstly, a network module and a data network switch are connected through a network cable to acquire a power network protocol, and a serial port module is connected to the receiving and sending of a serial port channel through a twisted pair to respectively acquire power serial port messages; secondly, the collected messages are analyzed and sorted by the protocol analysis module of the main module, then data compression is carried out by the data compression module of the main module, and the compressed data is transmitted to the storage module for storage after passing through the encryption module; extracting data in the storage module and transmitting the data to the master station through a forwarding module of the main module, wherein the data is encrypted by the encryption module; the power module controls the power supply to be stopped when each module does not work.
The power module first provides an output voltage to each module; collecting output voltage and current, and judging the stability of the voltage and the current; if the current or the voltage is unstable, the output voltage is adjusted to be stable, and if the adjustment is unsuccessful, an alarm is sent to indicate that the voltage and the current have problems.
The data compression module for data compression comprises the following steps.
1) And sorting the symbols according to the sequence of the occurrence probability of the symbols.
2) The two symbols with the smallest probability are combined into a node P1.
3) And (3) repeating the step (2) to obtain nodes P2, P3, P4 and P …, wherein PN forms a tree, and the PN is called a root node.
4) Starting from the root node PN to the leaves of each symbol, from top to bottom, the subscripts are 0 (upper branch) and 1 (lower branch), the probability is 1 as large, and the probability is 0 as small.
5) The code for each symbol is written separately from the root node PN along the branch to each leaf.
The compression formula is as follows.
。
The encryption process of the encryption module operates on a Byte matrix of 4 × 4, the initial value of which is a plaintext block (one element in the matrix is one Byte in the plaintext block), and each encryption cycle (except the last round) includes the following 4 steps.
1) Each byte in the matrix is subjected to XOR operation with the key of the next round; each subkey is generated by a key generation scheme.
2) Each byte is replaced by the corresponding byte in a look-up table manner through a non-linear replacement function.
3) Each row in the matrix is cyclically shifted.
4) The four bytes of each column are mixed using a linear transformation.
Step 4) is omitted in the last encryption round) and replaced with another step 1).
The encryption module is transformed in the following manner.
1) Each byte of the input or intermediate state is mapped to another byte; the mapping method comprises the following steps: the high 4 bits of the input byte are taken as row values and the low 4 bits as column values, and then the elements corresponding to the row and column are taken out as output.
2) The column aliasing transformation is performed by the method.
。
Wherein,the number representation within { x } is a byte; expressed as a matrix.
。
3) And (4) line shift conversion.
On the row of the intermediate state, row 0 is stationary, row 1 is shifted left by 1 byte cyclically, row 2 is shifted left by 2 bytes cyclically, and row 3 is shifted left by 3 bytes cyclically.
4) Round key plus transform.
Each column of the input or intermediate state S is associated with a key word W i]Performing a bitwise exclusive-or, wherein,generated from the original key by key expansion.
The protocol analysis module scans the matching character string from right to left from the first character at the rightmost end of the matching string, and moves the pattern string to the right by using two rules until matching is realized once mismatching occurs; the two rules are a good suffix rule and a bad character rule.
Good suffix rules.
Assuming that there is no match at the character x [ i ] = a of the pattern string, the character y [ i + j ] = b of the pattern string, i.e., x [ i +1.. m-1] = y [ i + j +1.. j + m-1] = u, and x [ i ] = y [ i + j ]; there are two situations that occur.
1) If a good suffix u is also included at other positions after x and the character x [ i-n ] = c adjacent to u at the left end is not equal to x [ i ] = a, then aligning u occurring at other positions after x with u in y and comparing x [ i-n ] with y [ i + j ]; as shown in fig. 7, u appears with the character c before the position | = a.
2) If no character string same as u appears, finding the longest prefix u of x same as the suffix of u and moving x rightwards, so that v corresponds to the suffix of u in y; as shown in fig. 8, only a portion of the prefix of u appears in x.
Bad character rules.
1) Finding that x [ i ] is different from y [ j ] in the scanning process from right to left, if one character x [ k ] is the same as y [ i ] and k < i exists in x, directly moving x to right to align x [ k ] with y [ i ], and then matching from right to left; as shown in fig. 9, a does not match b, which appears in x.
2) If there is no character in x identical to y [ i ], directly aligning the first character of x with the next character of y [ i ], and comparing from right to left; as shown in fig. 10, a does not match b, b is not present in x.
And when the text character string is not matched with the mode character, taking the larger of the deviation value calculated by the function bad character rule and the good suffix rule.
1) If the array storing the bad character rule is BadChar [ ], BadChar [ c ] = min { i |1 ≦ i ≦ m-1 and x [ m-1-i ] = c }, if c does not appear in the pattern character, BadChar [ c ] m (m is the length of x).
2) If the array in which the suffix rule is stored is GoodSuffix [ ], suff [ i ] = max { k | y [ i-k +1.. i ] = x [ m-k.. m-1], 1 ≦ i < m }; i.e., suff is the longest general suffix for P [0.. i ] and T; calculating the suff array makes calculating the GoodSuffix function concise GoodSuffix [ m-1-suff [ i ] ] = m-1-i.
Finally, the maximum value of BadChar [ c ] and GoodSuffix [ c ] is taken.
It should be understood that the detailed description of the present invention is only for illustrating the present invention and is not limited by the technical solutions described in the embodiments of the present invention, and those skilled in the art should understand that the present invention can be modified or substituted equally to achieve the same technical effects; as long as the use requirements are met, the method is within the protection scope of the invention.
Claims (6)
1. The intelligent record analysis system based on the digital communication of the transformer substation comprises a main module, a first serial port module, a second serial port module, a first network module, a second network module, a power supply module, a man-machine exchange module, a storage module and an encryption module, and is characterized in that a signal transmission port of the main module is respectively connected with a signal input port of the first serial port module, a signal output port of the second serial port module, a signal output port of the first network module, a signal input port of the second network module, a signal transmission port of the man-machine exchange module and a signal transmission port of the encryption module, a signal transmission port of the encryption module is connected with a signal transmission port of the storage module, a power output port of the power supply module is respectively connected with a power input port of the main module, a power input port of the first serial port module, a power input port of, The power input port of the first network module, the power input port of the second network module, the power input port of the man-machine exchange module, the power input port of the storage module and the power input port of the encryption module are connected;
the signal input port of the second serial port module is respectively connected with the signal output port of the serial port channel and the signal output port of the comprehensive acquisition device, the signal transmission port of the serial port channel is connected with the signal transmission port of the comprehensive acquisition device, the signal transmission port of the comprehensive acquisition device is connected with the signal transmission port of the data network switch, and the signal output port of the data network switch is connected with the signal input port of the first network module; the signal output port of the first serial port module is connected with the signal input port of the master station, and the signal output port of the second network module is connected with the signal input port of the master station;
firstly, a network module and a data network switch are connected through a network cable to acquire a power network protocol, and a serial port module is connected to the receiving and sending of a serial port channel through a twisted pair to respectively acquire power serial port messages; secondly, the collected messages are analyzed and sorted by the protocol analysis module of the main module, then data compression is carried out by the data compression module of the main module, and the compressed data is transmitted to the storage module for storage after passing through the encryption module; extracting data in the storage module and transmitting the data to the master station through a forwarding module of the main module, wherein the data is encrypted by the encryption module; the power supply module controls to stop supplying power when each module does not work;
the power module first provides an output voltage to each module; collecting output voltage and current, and judging the stability of the voltage and the current; if the current or the voltage is unstable, adjusting the output voltage to keep stable, and if the adjustment is unsuccessful, sending an alarm to prompt that the voltage and the current have problems;
the data compression module for data compression comprises the following steps:
1) sorting the symbols according to the order of the occurrence probability of the symbols;
2) forming two symbols with the minimum probability into a node P1;
3) repeating the step 2 to obtain nodes P2, P3, P4 and P …, wherein PN is called a root node, and a tree is formed;
4) from the root node PN to the leaf of each symbol, the subscripts are respectively 0 and 1 from top to bottom, the probability is 1 when being large, and the probability is 0 when being small;
5) writing out the code of each symbol from the root node PN to each leaf along the branch;
the compression formula is as follows:
；
the encryption process of the encryption module operates on a byte matrix of 4 × 4, the initial value of the encryption module is a plaintext block, and each round of encryption cycle comprises the following 4 steps during encryption:
1) each byte in the matrix is subjected to XOR operation with the sub-key of the next round; each subkey is generated by a key generation scheme;
2) replacing each byte with a corresponding byte by a non-linear replacement function in a lookup table manner;
3) cyclically shifting each row in the matrix;
4) mixing the four bytes of each column using a linear transformation;
step 4) is omitted in the last encryption cycle and replaced by another step 1);
the encryption module is transformed in the following way:
1) each byte of the input or intermediate state is mapped to another byte; the mapping method comprises the following steps: taking the high 4 bits of the input byte as a row value and the low 4 bits as a column value, and then taking out the elements corresponding to the row and the column as output;
2) the method for carrying out the column confusion transformation comprises the following steps:
wherein,the number representation within { x } is a byte; expressed as a matrix
3) Line shift conversion
On the line of the intermediate state, the 0 th line is fixed, the 1 st line is circularly moved left by 1 byte, the 2 nd line is circularly moved left by 2 bytes, and the 3 rd line is circularly moved left by 3 bytes;
4) round key plus transform
Each column of the input or intermediate state S is associated with a key word W i]Performing a bitwise exclusive-or, wherein,generated by the original key through key expansion;
the protocol analysis module scans the matching character string from right to left from the first character at the rightmost end of the matching string, and moves the pattern string to the right by using two rules until matching is realized once mismatching occurs; the two rules are a good suffix rule and a bad character rule;
good suffix rule:
assuming that there is no match at the character x [ i ] = a of the pattern string, the character y [ i + j ] = b of the pattern string, i.e., x [ i +1.. m-1] = y [ i + j +1.. j + m-1] = u, and x [ i ] = y [ i + j ]; there are two situations that occur:
1) if a good suffix u is also included at other positions after x and the character x [ i-n ] = c adjacent to u at the left end is not equal to x [ i ] = a, then aligning u occurring at other positions after x with u in y and comparing x [ i-n ] with y [ i + j ];
2) if no character string same as u appears, finding the longest prefix u of x same as the suffix of u and moving x rightwards, so that v corresponds to the suffix of u in y;
bad character rule:
1) finding that x [ i ] is different from y [ j ] in the scanning process from right to left, if one character x [ k ] is the same as y [ i ] and k < i exists in x, directly moving x to right to align x [ k ] with y [ i ], and then matching from right to left;
2) if there is no character in x identical to y [ i ], directly aligning the first character of x with the next character of y [ i ], and comparing from right to left;
when the text character string is not matched with the mode character, the larger of the text character string and the mode character string is selected according to the deviant calculated by the function bad character rule and the good suffix rule;
1) if the array storing the bad character rule is BadChar [ ], BadChar [ c ] = min { i |1 ≦ i ≦ m-1 and x [ m-1-i ] = c }, if c does not appear in the pattern character, BadChar [ c ] m, m is the length of x;
2) if the array in which the suffix rule is stored is GoodSuffix [ ], suff [ i ] = max { k | y [ i-k +1.. i ] = x [ m-k.. m-1], 1 ≦ i < m }; i.e., suff is the longest general suffix for P [0.. i ] and T; calculating the suff array so that the calculation of the GoodSuffix function becomes concise GoodSuffix [ m-1-suff [ i ] ] = m-1-i;
finally, taking the maximum value of BadChar [ c ] and GoodSuffix [ c ];
when the text character string is not matched with the mode character, initializing a Dist [ ] array through a function Dist (x), and then matching the character string; dist (x) -m + j is the distance of right shift of Pattern calculated according to the text character x corresponding to the current sample character P [ j ] and the relationship between x and m characters of the sample P [1 … m ] when a matching failure occurs once; the definition domain of the Dist (x) function is the character table Σ, and the value domain is {1, …, m };
where j = Max { k | P k = x,1 ≦ k < m }.
2. The intelligent recording and analyzing system based on substation digital communication of claim 1, characterized in that the main module adopts STM32F103VCT6 chip.
3. The intelligent recording and analyzing system based on the substation digital communication as claimed in claim 2, wherein the first network module and the second network module adopt a DM9000 chip U4, pins 3 and 4 of U4 are connected with a signal output port of a data network switch through a network transformer, and pins 7 and 8 of U4 are connected with a signal input port of a master station through a network transformer; u4's 3 feet link to each other with resistance R16 one end, the R16 other end respectively with resistance R15 one end, electric capacity C17 one end links to each other, the R15 other end links to each other with U4's 4 feet, the C17 other end, the ground wire, electric capacity C18 one end links to each other, the C18 other end, resistance R17 one end, resistance R18 one end links to each other, the resistance R17 other end links to each other with U4's 8 feet, the resistance R18 other end links to each other with U4's 7 feet.
4. The intelligent recording and analyzing system based on substation digital communication according to claim 3, wherein the first serial port module and the second serial port module adopt MAX232 chips U3, pin 14 of U3 is connected with a signal input port of a master station and one end of a first 3K resistor respectively, pin 13 of U3 is connected with a signal output port of a serial port channel and a signal output port of a comprehensive acquisition device and one end of a second 3K resistor respectively, the other end of the first 3K resistor is connected with an anode of an LED D3, a cathode of D3, a ground wire and a cathode of LED D4, and an anode of D4 is connected with the other end of the second 3K resistor.
5. The intelligent recording and analyzing system based on the substation digital communication as claimed in claim 4, wherein the data storage module adopts an AT24C04 chip, 5 pins of the AT24C04 chip are respectively connected with one end of a resistor R2 and a signal transmission port of the encryption module, 6 pins of the AT24C04 chip are respectively connected with one end of a resistor R1 and a signal transmission port of the encryption module, and the other end of the resistor R1 and the other end of the resistor R2 are connected with a power supply output port of the power supply module.
6. The intelligent record analysis system based on substation digital communication according to claim 5, characterized in that the encryption module adopts LKT4200 chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410730990.4A CN104601395B (en) | 2014-12-05 | 2014-12-05 | Intelligent record analysis system based on substation's digital communication |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410730990.4A CN104601395B (en) | 2014-12-05 | 2014-12-05 | Intelligent record analysis system based on substation's digital communication |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104601395A CN104601395A (en) | 2015-05-06 |
| CN104601395B true CN104601395B (en) | 2018-11-13 |
Family
ID=53126919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410730990.4A Active CN104601395B (en) | 2014-12-05 | 2014-12-05 | Intelligent record analysis system based on substation's digital communication |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104601395B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105468444B (en) * | 2015-11-18 | 2019-01-04 | 国电南瑞南京控制系统有限公司 | A kind of dispatching method of event information |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102142720A (en) * | 2011-04-29 | 2011-08-03 | 珠海市鸿瑞软件技术有限公司 | Network communication recorder and network communication record analysis system |
| CN202840688U (en) * | 2012-09-11 | 2013-03-27 | 南京新和普电力科技有限公司 | Intelligent station recording and network logging integrated device |
| CN203352292U (en) * | 2013-06-30 | 2013-12-18 | 安徽中兴继远信息技术股份有限公司 | Power distribution network monitoring automation system having encryption function |
| CN203368148U (en) * | 2013-07-12 | 2013-12-25 | 国家电网公司 | Intelligent substation network message recording analyzer system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101289957B1 (en) * | 2011-03-30 | 2013-07-31 | (주)넥스챌 | Substation automation system and method for collecting information using the system |
-
2014
- 2014-12-05 CN CN201410730990.4A patent/CN104601395B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102142720A (en) * | 2011-04-29 | 2011-08-03 | 珠海市鸿瑞软件技术有限公司 | Network communication recorder and network communication record analysis system |
| CN202840688U (en) * | 2012-09-11 | 2013-03-27 | 南京新和普电力科技有限公司 | Intelligent station recording and network logging integrated device |
| CN203352292U (en) * | 2013-06-30 | 2013-12-18 | 安徽中兴继远信息技术股份有限公司 | Power distribution network monitoring automation system having encryption function |
| CN203368148U (en) * | 2013-07-12 | 2013-12-25 | 国家电网公司 | Intelligent substation network message recording analyzer system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104601395A (en) | 2015-05-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101282275B (en) | Telecommunication Ethernet system and repeater | |
| CN106254381A (en) | Protocol analysis method, device and comprise the Layer2 switching system of protocol analysis device | |
| CN201682520U (en) | Device for conversion of Ethernet to DMX512 network | |
| CN109272733A (en) | It is a kind of that multilist is supported to close the multiterminal multimode Internet of Things communicating terminal and its meter register method copied | |
| CN109634397A (en) | A kind of system and method for realizing intelligent network adapter or more Electricity Functional | |
| CN108564776A (en) | Equipment debugging system, apparatus debugging method and computer storage media | |
| CN206775651U (en) | A kind of intelligent converter based on power line carrier | |
| CN104601395B (en) | Intelligent record analysis system based on substation's digital communication | |
| CN101566661A (en) | Electricity quality online monitoring system based on transparent transmission technology | |
| CN110167193A (en) | WiFi matches network method and WiFi equipment automatically | |
| CN206575515U (en) | Computer peripheral equipment netting twine extender and remote computer control device | |
| CN209216280U (en) | A kind of multi-protocol conversion device | |
| CN109067760A (en) | A kind of distribution DTU device and its method for accessing smart machine | |
| CN109920232A (en) | Electric power multi service access terminal and management system based on NB-loT | |
| CN107977333A (en) | A kind of cipher card and the method for communication | |
| CN105991214A (en) | Data transmission method and data transmission device | |
| CN104967574A (en) | Soft switch device | |
| CN108449434A (en) | A kind of building energy consumption data collecting system | |
| CN210807299U (en) | Transformer substation's dispatch data network safety alarm device | |
| CN109756576B (en) | Photoelectric network system | |
| CN103457645A (en) | Method for maintaining industrial device on posts through Bluetooth wireless technology | |
| CN101986512A (en) | Method for designing communication protocol of high-voltage and direct-current (HVDC) thyristor valve base electronic equipment | |
| CN208156104U (en) | PSE test fixture | |
| CN109462487A (en) | It is a kind of without management POE power supply for exchange power regulating method | |
| CN208257833U (en) | Ammeter collector |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |