CN104598670B

CN104598670B - A kind of ungratified method of solution FPGA retention time

Info

Publication number: CN104598670B
Application number: CN201410806609.8A
Authority: CN
Inventors: 周玉龙; 童元满; 李仁刚
Original assignee: Inspur Electronic Information Industry Co Ltd
Current assignee: Inspur Electronic Information Industry Co Ltd
Priority date: 2014-12-23
Filing date: 2014-12-23
Publication date: 2019-03-12
Anticipated expiration: 2034-12-23
Also published as: CN104598670A

Abstract

The present invention discloses a kind of ungratified method of solution FPGA retention time, it is related to FPGA design field, it is area-constrained by being carried out to module, physical location restrictions are carried out to the position of Block RAM (block memory), increase the data path(data path with the interface signal of Block RAM) and physical location restrictions are carried out to the interface signal of Block RAM；It solves the problems, such as that the Block RAM bring hold time of example XILINX in FPGA is ungratified, can quickly and easily solve the sequence problem of certain hold time, meet requirement of the entire design to timing.

Description

A kind of ungratified method of solution FPGA retention time

Technical field

The present invention relates to FPGA design fields, specifically a kind of ungratified method of solution FPGA retention time.

Background technique

With the continuous development of EDA (Electronic Design Automatic) technology and semiconductor fabrication process, core The function of piece is more and more stronger, and device architecture becomes increasingly complex.According to Moore's Law, the complexity of verifying is flat with chip area Side is directly proportional, and as capacity every 18 months double on chip unit area, the complexity of verifying can also be turned over for every 6-9 months ?.Verifying work is a job of most time and effort consuming in current chip design process, it can account for entire design work The 50-80% of amount is the bottleneck of current chip design.It is traditional since chip hardware number of modules is numerous, embedded software is complicated Logic-based simulation verification mode it is no longer feasible, especially its in soft or hard co-verification, the length of simulated time makes us difficult To endure.In order to shorten the chip checking time, the rapid system prototype (Rapid System Prototype) based on FPGA is tested Card, i.e. Hardware prototype and software prototype combine verifying, have become the important means in chip design cycle.

FPGA device has a development at full speed in density and complexity at present, the Stratix series of altera corp with And the Virtex family chip of Xilinx company can reach millions of scales, and millions of FPGA devices are all embedded with Microprocessor, IP logic module and multiple high-speed interface standards.Since the feature of FPGA maximum is exactly with static programmable Characteristic or online dynamic restructuring characteristic modify the function of hardware can equally by programming with software.Thus make to design Modification becomes very convenient, and real-time is good.Product development cycle can be made to greatly shorten, development cost reduces.

But be for fpga chip resource it is fixed, it is more complicated in temporal constraint, due to comparing in the utilization of resources In the case where more, the more complicated requirement for being just able to satisfy design of temporal constraint.In view of the fpga chip utilization of resources is relatively more or When person is relatively high to timing requirements to some module in design, when especially in the design example RAM IP Core, hold Time is frequently encountered the ungratified problem of timing and causes entirely to design timing and is unsatisfactory for, and tracing it to its cause is clock path (clock path) is than data path(data path) caused by delay is big, therefore the delay for increasing data path in the design can To solve the problems, such as hold Time, but constrain and excessive will affect the setup Time(setting time) satisfaction.

Summary of the invention

Present invention seek to address that being constantly present a clock offset in design when example Block RAM IP CORE, cause The ungratified problem of hold time, and a kind of ungratified method of solution FPGA retention time is provided.

A kind of ungratified method of solution FPGA retention time of the present invention solves the technology that the technical problem uses Scheme is as follows: the solution FPGA retention time ungratified method, area-constrained by carrying out to module, to Block RAM The position of (block memory) carries out physical location restrictions, increases the data path(data path with the interface signal of Block RAM) Physical location restrictions are carried out with the interface signal to Block RAM；The Block RAM for solving example XILINX in FPGA is brought The ungratified problem of hold time, can quickly and easily solve the sequence problem of certain hold time, satisfaction is entirely set Count the requirement to timing.

A kind of solution FPGA retention time ungratified method of the invention has the advantage that compared with prior art Be: the present invention only need to negate twice data, then keep this signal by primitive, can increase data path satisfaction The requirement of hold time；Significantly modification design is avoided, while also avoiding significantly carrying out temporal constraint.

Detailed description of the invention

Attached drawing 1 is temporal constraint schematic diagram of the present invention；

Attached drawing 2 is temporal constraint of the present invention specific implementation figure.

Specific embodiment

To make the objectives, technical solutions, and advantages of the present invention clearer, it below in conjunction with specific embodiment, and refers to Attached drawing, to a kind of solution FPGA retention time ungratified method further description of the present invention.

A kind of ungratified method of solution FPGA retention time of the present invention, it is main to consider the example XILINX in FPGA Block RAM IP CORE (the block memory IP kernel heart) the ungratified situation of bring hold time of (match company, Sentos), passes through It is area-constrained to module progress, physical location restrictions are carried out to the position of Block RAM (block memory), are increased and Block RAM Interface signal data path(data path) and physical location restrictions are carried out to the interface signal of Block RAM, to solve It has determined the ungratified problem of Block RAM bring hold time of example XILINX in FPGA.

Embodiment 1:

A kind of ungratified method of solution FPGA retention time described in the present embodiment, mainly includes the following steps: (1) to mould Block carries out area-constrained；(2) physical location restrictions are carried out to the position of Block RAM；(3) interface with Block RAM is increased The data path of signal；(4) physical location restrictions are carried out to the interface signal of Block RAM；As shown in Fig. 1.By this reality The example solution FPGA retention time ungratified method is applied, the timing that can quickly and easily solve certain hold time is asked Topic meets requirement of the entire design to timing.

In solution FPGA retention time ungratified method described in the present embodiment, (1) is area-constrained to module progress, It is area-constrained to refer to that the module relatively high to timing requirements carries out；It is usually to be had in entire design by several module compositions Be high-speed module, have plenty of low-speed module, for example in tide server interconnection chip FPGA prototype verification system, just utilize Arrive the IP CORE(IP core of the Aurora of XILINX) to carry out high-speed communication with CPU, since resources of chip utilization is relatively more, Aurora component frequency is again high, it is therefore necessary to carry out to Aurora module area-constrained.

(2) carry out physical location restrictions to the position of Block RAM: since Aurora module has been used very much Block RAM caches the data with CPU and damp server interconnection chip respectively, carries out physical location to the position of Block RAM Constraint can better meet the requirement designed to timing.

In general method, when timing is unsatisfactory for other than temporal constraint, it is also necessary to which modification design is by splitting combination The method of logic is delayed to reduce, and the present embodiment the method avoids significantly modifying design, while also avoiding significantly Carry out temporal constraint.The data path of the interface signal of the increasing and Block RAM, referring to only need to carry out two to data It is secondary to negate, this signal is then kept by XILINX primitive, data path can be increased, meets the requirement of hold time.

After step 3, due to increasing the data path with the interface signal of Block RAM, it certainly will will affect The time is arranged in setup time() timing, while physical location restrictions are carried out to the position of Block RAM in step 2, because This, which carries out physical location restrictions by the interface to Block RAM, can meet the timing of setup time, final to meet entirely Design the requirement to timing.

Embodiment 2:

FPGA retention time ungratified method is solved described in the present embodiment, on the basis of embodiment 1, first to module Carry out area-constrained, specific implementation is as follows:

INST "u_module/u_module_inst" AREA_GROUP = "pblock_u_module_inst";

AREA_GROUP"pblock_u_module_inst"RANGE=SLICE_X0Y310:SLICE_X83Y359;

Then physical location restrictions are carried out to the position of Block RAM, specific implementation is as follows:

INST "u_module/u_module_inst/data_ram"LOC = RAMB36_X1Y59 ;

It carries out increasing the data path with the interface signal of Block RAM again, as shown in Fig. 2, specific implementation is such as Under:

wire data; wire data1; wire data2; wire dataitfc;

assign data1= ~ data;

assign data2= ~ data1;

assign dataitfc = data2;

Finally, the interface signal to Block RAM carries out physical location restrictions, specific implementation is as follows:

INST "u_module/u_module_inst/data_ram_itfc" BEL = BFF;

INST"u_module/u_module_inst/data_ram_itfc"LOC = SLICE_X33Y327.

Above-mentioned specific embodiment is only specific case of the invention, and scope of patent protection of the invention includes but is not limited to Above-mentioned specific embodiment, any meet claims of the present invention and person of an ordinary skill in the technical field is to it The appropriate change or replacement done, all shall fall within the protection scope of the present invention.

Claims

1. a kind of ungratified method of solution FPGA retention time, which is characterized in that this method specifically comprises the following steps: (1) Module is carried out area-constrained；(2) physical location restrictions are carried out to the position of Block RAM；(3) it increases with Block RAM's The data path of interface signal；(4) physical location restrictions are carried out to the interface signal of Block RAM；

(1) is area-constrained to module progress, and it is area-constrained to refer to that the module relatively high to timing requirements carries out；Specific implementation Mode is as follows:

Alias is taken to carry out area-constrained module: pblock_u_module_inst；

Region agreement is carried out to carry out area-constrained module, it is allowed to be laid out wiring, FPGA factory in the region of delimitation The constraint of quotient Xilinx is SLICE_X0Y310 to SLICE_X83Y359；

Described (3) increase and the data path of the interface signal of Block RAM, refer to and negated twice to data, are then led to It crosses XILINX primitive and keeps this signal；Specific implementation is as follows:

The title of defined variable, variable can be arbitrarily designated: data, data1, data2, dataitfc；

According to the variable of definition, variable data is negated, is then assigned to variable data1；

According to the variable of definition, variable data1 is negated, is then assigned to variable data2；

According to the variable of definition, variable data2 is assigned to variable dataitfc；

(2) carry out physical location restrictions to the position of Block RAM, and specific implementation is as follows:

Position constraint is carried out to the data_ram to be constrained, the RAM in design is allowed to constrain on the designated position in fpga chip, The constrained of FPGA manufacturer Xilinx is RAMB36_X1Y59；

(4) carry out physical location restrictions to the interface signal of Block RAM, and specific implementation is as follows:

The signal data_ram_itfc that will be constrained carries out specified binding occurrence, and FPGA manufacturer Xilinx specifies signal by BEL Data_ram_itfc binding occurrence is BFF；

Position constraint is carried out to the signal data_ram_itfc to be constrained, allows designated position of the signal bondage in fpga chip On, the constrained of FPGA manufacturer Xilinx is SLICE_X33Y327.

2. a kind of ungratified method of solution FPGA retention time according to claim 1, which is characterized in that Aurora mould Block carries out area-constrained.