CN104598195A - Method and system for improving clock stability analysis - Google Patents

Abstract

The invention discloses a method for improving clock stability analysis. The method includes the steps that 1, N sampled data are acquired and sent to a center arithmetic unit; 2, the center arithmetic unit receives the N sampled data, calculates a first accumulated value Sum(j) and sends the first accumulated value Sum(j) to a data storage unit; 3, the data storage unit receives the Sum(j) sent by the center arithmetic unit and stores the Sum(j); 4, the center arithmetic unit calls the Sum(j) form the data storage unit, calculates Sum(j+1), and sends the Sum(j+1) to the data storage unit; 5, the data storage unit stores the Sum(j+1); 6, the step 4 and the step 5 are repeated, after the center arithmetic unit calculates all Sums from Sum(1) to Sum(N-3n+1), the center arithmetic unit calculates the value (please see the formula in the specifications); 7, the center arithmetic unit calculates time deviation TDEV(ntao0), and sends the time deviation to a data display unit; 8, the data display unit receives and displays the time deviation TDEV(ntao0). The invention further discloses a system for improving clock stability analysis. An algorithm is simple, and previous calculation results can be repeatedly used.

Description

A kind of method and system improving clock stability and analyze

Technical field

The present invention relates to technical field of data processing, specifically, relate to a kind of method and system improving clock stability and analyze.

Background technology

In clock test field, MTIE (MTIE) and time deviation (TDEV) two indices are all the degree of stability representing that clock is long-term, and this two indices is extremely important in PTN and IPRAN transmission network popular now.

MTIE (MTIE) refers within a measuring period, in a given window, maximum phase change is called MTIE, is used to the peak-peak value of phase place change and a technical indicator of frequency cancellation in constraint network interface.Time deviation (TDEV) is the index of the specific composition scope using phase place on network interface.TDEV and MTIE is the two kinds of methods characterizing clock phase variation characteristic, and within same observing time, both MTIE are identical, but TDEV value just may have very big difference, and TDEV reflects this characteristic of clock signal just.Instrument calculates MTIE and TDEV after carrying out long-time clock accuracy test to testing apparatus, to judge whether this testing apparatus clock meets the standards such as ITUG.811.Wherein the algorithmic formula of TDEV is:

$\mathrm{TDEV}\left({\mathrm{n\τ}}_0\right)=\sqrt{\frac{1}{6n^2(N-3n+1)}{\mathrm{\Σ}}_{j=1}^{N-3n+1}{\left[{\mathrm{\Σ}}_{i=j}^{n+j-1}(X_{i+2n}-2X_{i+n}+X_i)\right]}^2}$

Wherein: n is the sampling number in observing time, N is the sum of data from the sample survey, τ ₀for the time interval between adjacent sampled value.

There is following shortcoming in the Time warp used when analyzing clock stability in prior art:

Very complicated by the formula of TDEV its algorithm visible, when sampling point data are large, operand is very large, low at cpu frequency, memory size is little, in the embedded OS that various software and hardware condition is all very limited, it is very painstaking that calculating TDEV shows, and tester usually needs to wait the result just seeing TDEV for a long time.

Summary of the invention

For solving the problems of the technologies described above, the invention provides a kind of method improving clock stability and analyze, comprising step:

Step 1): data acquisition unit acquires amounts to N number of sampled data, and sampled value is X ₁, X ₂x _n, the time interval between adjacent sample values is τ ₀, the sampled data in one of them watch window is n, and described N number of sampling data transmitting is delivered to central arithmetic unit;

Step 2): described central arithmetic unit receives N number of sampled data that described data acquisition unit sends, and calculates n τ according to the following equation ₀the first accumulated value Sum (j) in watch window:

$\mathrm{Sum}\left(j\right)={\mathrm{\Σ}}_{i=j}^{n+j-1}(X_{i+2n}-2X_{i+n}+X_i),$

Wherein, X _ibe i-th sampled value,

Described first accumulated value Sum (j) is sent to data storage cell by described central arithmetic unit;

Step 3): described data storage cell, receives the first accumulated value Sum (j) that described central arithmetic unit sends, and stores;

Step 4): calculate Sum (j+1), described central arithmetic unit transfers the first accumulated value Sum (j) from described data storage cell, utilizes following formula to carry out calculating Sum (j+1):

Sum(j+1)＝[Sum(j)-(X _j+2n-2X _j+n+X _j)+(X _(n+j)+2n-2X _(N+j)+n+X _(n+j))] ²，

First accumulated value Sum (j+1) is sent to described data storage cell and stores by described central arithmetic unit;

Step 5): described data storage cell, the first accumulated value Sum (j+1) receiving the transmission of described central arithmetic unit stores;

Step 6): repeat step 4) and 5), described central arithmetic unit calculates the second accumulated value after all being calculated by Sum (1) to Sum (N-3n+1) described second accumulated value calculate according to the following equation:

${\mathrm{\Σ}}_{j=1}^{N-3n+1}{\left[\mathrm{Sum}\left(j\right)\right]}^2={\left[\mathrm{Sum}\left(1\right)\right]}^2+{\left[\mathrm{Sum}\left(2\right)\right]}^2+...+{\left[\mathrm{Sum}(N-3n+1)\right]}^2$

Step 7): described central arithmetic unit calculates n τ according to the following equation ₀time deviation TDEV (n τ in watch window ₀):

$\mathrm{TDEV}\left({\mathrm{n\τ}}_0\right)=\sqrt{\frac{1}{6n^2(N-3n+1)}{\mathrm{\Σ}}_{j=1}^{N-3n+1}{\left[{\mathrm{\Σ}}_{i=j}^{n+j-1}(X_{i+2n}-2X_{i+n}+X_i)\right]}^2}$

Time deviation TDEV (the n τ that described central arithmetic unit will calculate ₀) value, be sent to data display unit display;

Step 8): described data display unit, receives time deviation TDEV (the n τ that described central arithmetic unit sends ₀) value, show.

Preferably, described sampled data, further for clock drift signal, described sampled value represents that moment that present clock arrives should arrive relative to it mistiming in moment.

Preferably, described method, carries out further in OTM2800 time tester.

Preferably, embedded system is established in described OTM2800 time tester.

Improve the system that clock stability is analyzed, this system comprises: data acquisition unit, central arithmetic unit, storage unit and data display unit, wherein,

Described data acquisition unit, couples mutually with described central arithmetic unit, and amount to N number of sampled data for gathering, sampled value is X ₁, X ₂x _n, the time interval between adjacent sample values is τ ₀, the sampled data in one of them watch window is n, and described N number of sampling data transmitting is delivered to central arithmetic unit;

Described central arithmetic unit, couple mutually with described data acquisition unit, data storage cell and data display unit respectively, for receiving N number of sampled data that described data acquisition unit sends, receiving N number of sampled data that described data acquisition unit sends, calculating n τ according to the following equation ₀the first accumulated value Sum (j) in watch window:

$\mathrm{Sum}\left(j\right)={\mathrm{\Σ}}_{i=j}^{n+j-1}(X_{i+2n}-2X_{i+n}+X_i),$

Wherein, X _ibe i-th sampled value,

Described central arithmetic unit, also for described first accumulated value Sum (j) is sent to described data storage cell;

Described data storage cell, for receiving the first accumulated value Sum (j) that described central arithmetic unit sends, and stores;

Described central arithmetic unit, also for transferring the first accumulated value Sum (j) from described data storage cell, utilizes following formula to carry out calculating first accumulated value Sum (j+1):

Sum(j+1)＝[Sum(j)-(X _j+2n-2X _j+n+X _j)+(X _(n+j)+2n-2X _(N+j)+n+X _(n+j))] ²，

Described central arithmetic unit, also stores for the first accumulated value Sum (j+1) is sent to described data storage cell;

Described data storage cell, the first accumulated value Sum (j+1) also sent for receiving described central arithmetic unit stores;

Described central arithmetic unit, after also all being calculated by Sum (1) to Sum (N-3n+1) for the process of Sum described in double counting (j+1), calculates the second accumulated value described second accumulated value calculate according to the following equation:

${\mathrm{\Σ}}_{j=1}^{N-3n+1}{\left[\mathrm{Sum}\left(j\right)\right]}^2={\left[\mathrm{Sum}\left(1\right)\right]}^2+{\left[\mathrm{Sum}\left(2\right)\right]}^2+...+{\left[\mathrm{Sum}(N-3n+1)\right]}^2;$

Described central arithmetic unit, also for calculating n τ according to the following equation ₀time deviation TDEV (n τ in watch window ₀):

$\mathrm{TDEV}\left({\mathrm{n\τ}}_0\right)=\sqrt{\frac{1}{6n^2(N-3n+1)}{\mathrm{\Σ}}_{j=1}^{N-3n+1}{\left[{\mathrm{\Σ}}_{i=j}^{n+j-1}(X_{i+2n}-2X_{i+n}+X_i)\right]}^2}$

Described central arithmetic unit, time deviation TDEV (the n τ also for calculating ₀) value, be sent to data display unit display;

Described data display unit, for receiving time deviation TDEV (the n τ that described central arithmetic unit sends ₀) value, show.

Preferably, described sampled data, further for clock drift signal, described sampled value represents that moment that present clock arrives should arrive relative to it mistiming in moment.

Preferably, the system that described raising clock stability is analyzed, is, OTM2800 time tester further

Preferably, embedded system is established in described OTM2800 time tester.

Compared with prior art, the method and system that raising clock stability of the present invention is analyzed, reach following effect:

Algorithm is simple, and can reuse former result of calculation: the analytical approach in the present invention, compared with the key algorithm part of the TDEV of prior art, greatly reduces computational complexity, in the method for prior art ${\mathrm{\Σ}}_{j=1}^{N-3n+1}{\left[{\mathrm{\Σ}}_{i=j}^{n+j-1}(X_{i+2n}-2X_{i+n}+X_i)\right]}^2$ Carry out dual cumulative process, but the method for this patent needs except first time computing the computing carrying out one-accumulate, preserve lower Sum (x), later computational complexity is each time by being then reduced to Sum (x) * (X _(x)+2n-2X _(x)+n+ X _(x))+(X _(n+x)+2n-2X _(N+x)+n+ X _(n+x)), in the computing of big data quantity, this algorithm can reduce algorithm complex greatly, saves CPU time, thus accomplishes the result of calculation providing TDEV faster.

Accompanying drawing explanation

Accompanying drawing described herein is used to provide a further understanding of the present invention, forms a part of the present invention, and schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:

Fig. 1 is the method flow diagram that prior art clock signal is analyzed;

Fig. 2 is the method flow diagram that the raising clock stability of the present embodiment one is analyzed;

Fig. 3 is the system construction drawing that the raising clock stability of the present embodiment one is analyzed.

Embodiment

As employed some vocabulary to censure specific components in the middle of instructions and claim.Those skilled in the art should understand, and hardware manufacturer may call same assembly with different noun.This specification and claims are not used as with the difference of title the mode distinguishing assembly, but are used as the criterion of differentiation with assembly difference functionally." comprising " as mentioned in the middle of instructions and claim is in the whole text an open language, therefore should be construed to " comprise but be not limited to "." roughly " refer to that in receivable error range, those skilled in the art can solve the technical problem within the scope of certain error, reach described technique effect substantially.In addition, " couple " word and comprise directly any and indirectly electric property coupling means at this.Therefore, if describe a first device in literary composition to be coupled to one second device, then represent described first device and directly can be electrically coupled to described second device, or be indirectly electrically coupled to described second device by other devices or the means that couple.Instructions subsequent descriptions is for implementing better embodiment of the present invention, and right described description is to illustrate for the purpose of rule of the present invention, and is not used to limit scope of the present invention.Protection scope of the present invention is when being as the criterion depending on the claims person of defining.

Below in conjunction with accompanying drawing, the present invention is described in further detail, but not as a limitation of the invention.

Embodiment one:

Composition graphs 2 and Fig. 3, present embodiments provide a kind of method improving clock stability and analyze, comprise the following steps:

Step 1): data acquisition unit acquires amounts to N number of sampled data, and sampled value is X ₁, X ₂x _n, the time interval between adjacent sample values is τ ₀, the sampled data in one of them watch window is n, and described N number of sampling data transmitting is delivered to central arithmetic unit;

Data acquisition unit is arranged in OTM2800 time tester of the present invention.Here budget of the Central Committee unit can be the dominant frequency 400Mhz of CPU, CPU further, can be also other arithmetical unit, be not specifically limited here.X in this step ₁, X ₂x _nbe the sampled value of clock signal data, sampled value can for being more than or equal to 100000 signal datas, and also can be less than or equal to 100000 signal datas, in the present invention, data be more, and the time of saving is also more.

Step 2): described central arithmetic unit receives N number of sampled data that described data acquisition unit sends, and calculates n τ according to the following equation ₀the first accumulated value Sum (j) in watch window:

$\mathrm{Sum}\left(j\right)={\mathrm{\Σ}}_{i=j}^{n+j-1}(X_{i+2n}-2X_{i+n}+X_i),$

Wherein, X _ibe i-th sampled value,

Described first accumulated value Sum (j) is sent to data storage cell and stores by described central arithmetic unit;

Step 3): described data storage cell, receives the first accumulated value Sum (j) that described central arithmetic unit sends, and stores;

It should be noted that: here data storage cell the first accumulated value Sum (j) is stored be conveniently subsequent calls time use, such as first time computing calculates Sum (1), so needs according to Sum (j+1)=[Sum (j)-(X when calculating Sum (2) _j+2n-2X _j+n+ X _j)+(X _(n+j)+2n-2X _(N+j)+n+ X _(n+j))] ²calculate, computation process just can call Sum (j) here, reduces CPU operation times.

Step 4): calculate Sum (j+1), described central arithmetic unit transfers the first accumulated value Sum (j) from described data storage cell, and Sum (j+1) utilizes following formula to calculate:

Sum(j+1)＝[Sum(j)-(X _j+2n-2X _j+n+X _j)+(X _(n+j)+2n-2X _(N+j)+n+X _(n+j))] ²

First accumulated value Sum (j+1) is sent to described data storage cell and stores by described central arithmetic unit;

Step 5): described data storage cell, the first accumulated value Sum (j+1) receiving the transmission of described central arithmetic unit stores;

Step 6): repeat step 4) and 5), described central arithmetic unit calculates the second accumulated value after all being calculated by Sum (1) to Sum (N-3n+1) described second accumulated value calculate according to the following equation:

${\mathrm{\Σ}}_{j=1}^{N-3n+1}{\left[\mathrm{Sum}\left(j\right)\right]}^2={\left[\mathrm{Sum}\left(1\right)\right]}^2+{\left[\mathrm{Sum}\left(2\right)\right]}^2+...+{\left[\mathrm{Sum}(N-3n+1)\right]}^2$

Step 7): described central arithmetic unit calculates n τ according to the following equation ₀time deviation TDEV (n τ in watch window ₀):

$\mathrm{TDEV}\left({\mathrm{n\τ}}_0\right)=\sqrt{\frac{1}{6n^2(N-3n+1)}{\mathrm{\Σ}}_{j=1}^{N-3n+1}{\left[{\mathrm{\Σ}}_{i=j}^{n+j-1}(X_{i+2n}-2X_{i+n}+X_i)\right]}^2}$

Time deviation TDEV (the n τ that described central arithmetic unit will calculate ₀) value, be sent to data display unit display;

Step 8): described data display unit, receives time deviation TDEV (the n τ that described central arithmetic unit sends ₀) value, show.

It should be noted that, the described sampled data of data acquisition unit acquires in the present invention, further for clock drift signal, described sampled value represents that moment that present clock arrives should arrive relative to it mistiming in moment.

Said method, all carries out in OTM2800 time tester of the present invention, and can also arrange embedded system in this OTM2800 time tester.

As can be known from Fig. 3, the present invention is a kind of system improving clock stability and analyze also, and this system comprises: data acquisition unit 301, central arithmetic unit 302, storage unit 303 and data display unit 304, wherein,

Described data acquisition unit 301, couples mutually with described central arithmetic unit 302, and amount to N number of sampled data for gathering, sampled value is X ₁, X ₂x _n, the time interval between adjacent sample values is τ ₀, the sampled data in one of them watch window is n, and described N number of sampling data transmitting is delivered to central arithmetic unit 302;

Described central arithmetic unit 302, couples mutually with described data acquisition unit 301, storage unit 303 and data display unit 304 respectively, for receiving N number of sampled data that described data acquisition unit 301 sends, calculates n τ according to the following equation ₀the first accumulated value Sum (j) in watch window:

$\mathrm{Sum}\left(j\right)={\mathrm{\Σ}}_{i=j}^{n+j-1}(X_{i+2n}-2X_{i+n}+X_i),$

Wherein, X _ibe i-th sampled value,

Described central arithmetic unit 302, also for described first accumulated value Sum (j) is sent to described data storage cell 303;

Described data storage cell 303, for receiving the first accumulated value Sum (j) that described central arithmetic unit 302 sends, and stores;

Described central arithmetic unit 302, also for transferring the first accumulated value Sum (j) from described data storage cell, utilizes following formula to carry out calculating Sum (j+1):

Sum(j+1)＝[Sum(j)-(X _j+2n-2X _j+n+X _j)+(X _(n+j)+2n-2X _(N+j)+n+X _(n+j))] ²，

Described central arithmetic unit 302, also for the first accumulated value Sum (j+1) is sent to described data storage cell 303;

Described data storage cell 303, the first accumulated value Sum (j+1) sent for receiving described central arithmetic unit 302 stores;

Described central arithmetic unit 302, after also all being calculated by Sum (1) to Sum (N-3n+1) for the process of Sum described in double counting (j+1), calculates the second accumulated value described second accumulated value calculate according to the following equation:

${\mathrm{\Σ}}_{j=1}^{N-3n+1}{\left[\mathrm{Sum}\left(j\right)\right]}^2={\left[\mathrm{Sum}\left(1\right)\right]}^2+{\left[\mathrm{Sum}\left(2\right)\right]}^2+...+{\left[\mathrm{Sum}(N-3n+1)\right]}^2;$

Here be exactly repeat " described central arithmetic unit 302, also for transferring the first accumulated value Sum (j) from described data storage cell, utilizes following formula to carry out calculating Sum (j+1):

Sum (j+1)=[Sum (j)-(X _j+2n-2X _j+n+ X _j)+(X _(n+j)+2n-2X _(N+j)+n+ X _(n+j))] ², described central arithmetic unit 302, also for the first accumulated value Sum (j+1) is sent to described data storage cell 303; Described data storage cell 303, the first accumulated value Sum (j+1) sent for receiving described central arithmetic unit 302 stores; " these functions, by Sum (1), Sum (2),, Sum (N-3n+1) all calculates, here compared to prior art, save a lot of calculating process, decrease repetitive operation.

Described central arithmetic unit 302, also for calculating n τ according to the following equation ₀time deviation TDEV (n τ in watch window ₀):

$\mathrm{TDEV}\left({\mathrm{n\τ}}_0\right)=\sqrt{\frac{1}{6n^2(N-3n+1)}{\mathrm{\Σ}}_{j=1}^{N-3n+1}{\left[{\mathrm{\Σ}}_{i=j}^{n+j-1}(X_{i+2n}-2X_{i+n}+X_i)\right]}^2}$

Described central arithmetic unit 302, time deviation TDEV (the n τ also for calculating ₀) value, be sent to data display unit 304 and show;

Described data display unit 304, for receiving time deviation TDEV (the n τ that described central arithmetic unit 302 sends ₀) value, show.

The system that raising clock stability provided by the invention is analyzed be OTM2800 time tester further, and this OTM2800 time tester can also be provided with embedded system.

Sampled data described in the present invention is clock drift signal, and sampled value represents that moment that present clock arrives should arrive relative to it mistiming in moment.Such as present clock should arrive in the 5th second, but the true time arrived is 5.1 seconds, and sampled value is then 5.1-5=0.1 second.

Technical scheme of the present invention realizes based on following formula:

As can be seen from the formula of TDEV, the part that operand is larger is

${\mathrm{\Σ}}_{j=1}^{N-3n+1}{\left[{\mathrm{\Σ}}_{i=j}^{n+j-1}(X_{i+2n}-2X_{i+n}+X_i)\right]}^2,$ Need to carry out the secondary (X of (N-3n+1) * (n+j-1) _i+2n-2X _i+n+ X _i) computing.Wherein contain a large amount of repetitive operations, waste CPU time and internal memory, so do following derivation to this formula:

As j=x, definition $\mathrm{Square}\left(x\right)={\left[{\mathrm{\Σ}}_{i=j}^{n+j-1}(X_{i+2n}-2X_{i+n}+X_i)\right]}^2$

$\begin{array}{c}={\left[{\mathrm{\Σ}}_{i=x}^{n+x-1}(X_{i+2n}-2X_{i+n}+X_i)\right]}^2\\ =[(X_{\left(x\right)+2n}-2X_{\left(x\right)+n}+X_{\left(x\right)})+(X_{(x+1)+2}-2X_{(x+1)+n}+X_{(x+1)})\\ +(X_{(x+2)+2n}-{2X}_{(x+2)+n}+X_{(x+2)})+...\\ +(X_{(n+x-1-1)+2n}-{2X}_{(N+x-1-1)+n}+X_{(n+x-1-1)})\\ +(X_{(n+x-1)+2n}-2X_{(x+x-1)+n}+X_{(n+x-1)}){]}^2\\ =[(X_{\left(x\right)+2n}-2X_{\left(x\right)+n}+X_{\left(x\right)}+(X_{(x+1)+2n}-{2X}_{(x+1)+n}+X_{(x+1)})+\\ (X_{(x+2)+2n}-{2X}_{(x+2)+n}+X_{(x+2)})+...+(X_{(n+2-2)+2n}-2X_{(N+x-2)+n}+\\ X_{(n+x-2)})+(X_{(n+x-1)+2n}-{2X}_{(N+x-1)+n}+X_{(n+x-1)}){]}^2\end{array}$

Definition Sum (x)=(X _(x)+2n-2X _(x)+n+ X _(x))+(X _(x+1)+2n-2X _(x+1)+n+

X _(x+1))+(X _(x+2)+2n-2X _(x+2)+n+X _(x+2))+…+(X _(n+x-2)+2n-

2X _(N+x-2)+n+X _(n+x-2))+(X _(n+x-1)+2n-2X _(N+x-1)+n+X _(n+x-1))

Then: Square (x)=[Sum (x)] ²

As j=x+1, definition $\mathrm{Square}(x+1)={\left[{\mathrm{\Σ}}_{i=j}^{n+j-1}(X_{i+2n}-{2x}_{i+n}+X_i)\right]}^2$

$\begin{array}{c}={\left[{\mathrm{\Σ}}_{i=x+1}^{n+x+1-1}(X_{i+2n}-{2X}_{i+n}+X_i)\right]}^2\\ =[(X_{(x+1)+2n}-{2X}_{(x+1)+n}+X_{(x+1)})+(X_{(x+1+1)+2n}-2X_{(x+1+1)+n}+\\ X_{(x+1+1)})+...+(X_{(n+x+1-1-1)+2n}-{2X}_{(N+x+1-1-1)+n}+X_{(n+x+1-1-1)})+\\ {(X_{(n+x+1-1)+2n}-2X_{(N+x+1-1)+n}+X_{(n+x+1-1)})]}^2\end{array}$

$\begin{array}{c}=[(X_{(x+1)+2n}-2X_{(x+1)+n}+X_{(x+1)})+(X_{(x+2)+2n}-2X_{(x+2)+n}+X_{(x+2)})+\\ ...+(X_{(n+x-1)+2n}-2X_{(N+x-1)+n}{+X}_{(n+x-1)})+\\ {(X_{(n+x)+2n}-2X_{(N+x)+n}+X_{(n+x)})]}^2\end{array}$

Definition Sum (x+1)=(X _(x+1)+2n-2X _(x+1)+n+ X _(x+1))+(X _(x+2)+2n-

2X _(x+2)+n+X _(x+2))+…+(X _(n+x-1)+2n-2X _(N+x-1)+n+X _(n+x-1))+

(X _(n+x)+2n-2X _(N+x)+n+X _(n+x))

Then: Square (x+1)=[Sum (x+1)] ²

So derive formula below:

Square(x+1)＝[Sum(x)-(X _(x)+2n-2X _(x)+n+X _(x))+(X _(n+x)+2n-

2X _(N+x)+n+X _(n+x))] ²

This shows each time computing can utilize last ${\mathrm{\Σ}}_{i=j}^{n+j-1}(X_{i+2n}-2X_{i+n}+X_i)$ Result.

Embodiment two:

On the basis of embodiment one, carry out analytical calculation according to the clock signal analytical approach of embodiment one and system:

In the present embodiment, utilize the system that this raising clock stability of OTM2800 time tester is analyzed, with 100000 signal datas for radix carries out computing, i.e. N=100000, n=100, τ ₀₌₁, the deadline is general 80ms, and method and system of the present invention has saved the time completing computing greatly, and wherein N or n is larger, and the time of saving is more.

Contrast test

Method in this contrast test is the method that in prior art, clock signal is analyzed, and step is as follows:

1, data acquisition unit acquires amounts to N number of sampled data, and sampled value is X ₁, X ₂x _n, the time interval between adjacent sample values is τ ₀, the sampled data in one of them watch window is n, and described N number of sampling data transmitting is delivered to central arithmetic unit;

2, described central arithmetic unit receives N number of sampled data that described data acquisition unit sends, and calculates a n τ ₀time deviation TDEV (n τ in watch window ₀), calculate according to the following equation:

$\mathrm{TDEV}\left({\mathrm{n\τ}}_0\right)=\sqrt{\frac{1}{6n^2(N-3n+1)}{\mathrm{\Σ}}_{j=1}^{N-3n+1}{\left[{\mathrm{\Σ}}_{i=j}^{n+j-1}(X_{i+2n}-2X_{i+n}+X_i)\right]}^2};$

Central arithmetic unit carries out repeatedly multiple accumulating operation, then after being multiplied by coefficient again evolution obtain the n τ of N number of data ₀time deviation TDEV (n τ in watch window ₀), be sent to described data display unit;

3, data display unit receives the n τ that central arithmetic unit sends ₀time deviation TDEV (n τ in watch window ₀), and show.

With 100000 signal datas for radix carries out computing, i.e. N=100000, n=100, τ ₀₌₁, the time of contrast test deadline deviation is 3260ms, but according to method provided by the invention, the deadline is general 80ms, and found by time contrast, the present invention has saved the deadline greatly, and wherein N or n is larger, and the time of saving is more.

Compared with prior art, the method and system that raising clock stability of the present invention is analyzed, reach following effect:

Algorithm is simple, and can reuse former result of calculation: the analytical approach in the present invention, compared with the key algorithm part of the TDEV of prior art, greatly reduces computational complexity, in the method for prior art ${\mathrm{\Σ}}_{j=1}^{N-3n+1}{\left[{\mathrm{\Σ}}_{i=j}^{n+j-1}(X_{i+2n}-2X_{i+n}+X_i)\right]}^2$ Carry out multiple accumulating operation, but method of the present invention needs to carry out one-accumulate calculating process except first time computing, preserve lower Sum (x), later computational complexity each time reduces Sum (x)-(X _(x)+2n-2X _(x)+n+ X _(x))+(X _(n+x)+2n-2X _(N+x)+n+ X _(n+x)), in the computing of big data quantity, this algorithm can reduce algorithm complex greatly, saves CPU time, thus accomplishes the result of calculation providing TDEV faster.

Above-mentioned explanation illustrate and describes some preferred embodiments of the present invention, but as previously mentioned, be to be understood that the present invention is not limited to the form disclosed by this paper, should not regard the eliminating to other embodiments as, and can be used for other combinations various, amendment and environment, and can in invention contemplated scope described herein, changed by the technology of above-mentioned instruction or association area or knowledge.And the change that those skilled in the art carry out and change do not depart from the spirit and scope of the present invention, then all should in the protection domain of claims of the present invention.

Claims (8)

1. improve the method that clock stability is analyzed, it is characterized in that, comprise step:

Step 1): data acquisition unit acquires amounts to N number of sampled data, and sampled value is X ₁, X ₂x _n, the time interval between adjacent sample values is τ ₀, the sampled data in one of them watch window is n, and described N number of sampling data transmitting is delivered to central arithmetic unit;

Step 2): described central arithmetic unit receives N number of sampled data that described data acquisition unit sends, and calculates n τ according to the following equation ₀the first accumulated value Sum (j) in watch window:

Wherein, X _ibe i-th sampled value,

Described first accumulated value Sum (j) is sent to data storage cell by described central arithmetic unit;

Step 3): described data storage cell, receives the first accumulated value Sum (j) that described central arithmetic unit sends, and stores;

Step 4): calculate Sum (j+1), described central arithmetic unit transfers the first accumulated value Sum (j) from described data storage cell, utilizes following formula to carry out calculating Sum (j+1):

Sum(j+1)＝[Sum(j)-(X _j+2n-2X _j+n+X _j)+(X _(n+j)+2n-2X _(N+j)+n+X _(n+j))] ²，

First accumulated value Sum (j+1) is sent to described data storage cell and stores by described central arithmetic unit;

Step 5): described data storage cell, the first accumulated value Sum (j+1) receiving the transmission of described central arithmetic unit stores;

Step 6): repeat step 4) and 5), described central arithmetic unit calculates the second accumulated value after all being calculated by Sum (1) to Sum (N-3n+1) described second accumulated value calculate according to the following equation:

Step 7): described central arithmetic unit calculates n τ according to the following equation ₀time deviation TDEV (n τ in watch window ₀):

Time deviation TDEV (the n τ that described central arithmetic unit will calculate ₀) value, be sent to data display unit display;

Step 8): described data display unit, receives time deviation TDEV (the n τ that described central arithmetic unit sends ₀) value, show.

2. the method analyzed of raising clock stability according to claim 1, it is characterized in that, described sampled data, is clock drift signal further, and described sampled value represents that moment that present clock arrives should arrive relative to it mistiming in moment.

3. the method for raising clock stability analysis according to claim 1 and 2, is characterized in that described method is carried out further in OTM2800 time tester.

4. the method for raising clock stability analysis according to claim 1, is characterized in that, establish embedded system in described OTM2800 time tester.

5. improve the system that clock stability is analyzed, it is characterized in that, this system comprises: data acquisition unit, central arithmetic unit, storage unit and data display unit, wherein,

Described data acquisition unit, couples mutually with described central arithmetic unit, and amount to N number of sampled data for gathering, sampled value is X ₁, X ₂x _n, the time interval between adjacent sample values is τ ₀, the sampled data in one of them watch window is n, and described N number of sampling data transmitting is delivered to central arithmetic unit;

Described central arithmetic unit, couple mutually with described data acquisition unit, data storage cell and data display unit respectively, for receiving N number of sampled data that described data acquisition unit sends, receiving N number of sampled data that described data acquisition unit sends, calculating n τ according to the following equation ₀the first accumulated value Sum (j) in watch window:

Wherein, X _ibe i-th sampled value,

Described central arithmetic unit, also for described first accumulated value Sum (j) is sent to described data storage cell;

Described data storage cell, for receiving the first accumulated value Sum (j) that described central arithmetic unit sends, and stores;

Described central arithmetic unit, also for transferring the first accumulated value Sum (j) from described data storage cell, utilizes following formula to carry out calculating first accumulated value Sum (j+1):

Sum(j+1)＝[Sum(j)-(X _j+2n-2X _j+n+X _j)+(X _(n+j)+2n-2X _(N+j)+n+X _(n+j))] ²，

Described central arithmetic unit, also stores for the first accumulated value Sum (j+1) is sent to described data storage cell;

Described data storage cell, the first accumulated value Sum (j+1) also sent for receiving described central arithmetic unit stores;

Described central arithmetic unit, after also all being calculated by Sum (1) to Sum (N-3n+1) for the process of Sum described in double counting (j+1), calculates the second accumulated value described second accumulated value calculate according to the following equation:

Described central arithmetic unit, also for calculating n τ according to the following equation ₀time deviation TDEV (n τ in watch window ₀):

Described central arithmetic unit, time deviation TDEV (the n τ also for calculating ₀) value, be sent to data display unit display;

Described data display unit, for receiving time deviation TDEV (the n τ that described central arithmetic unit sends ₀) value, show.

6. the system analyzed of raising clock stability according to claim 5, it is characterized in that, described sampled data, is clock drift signal further, and described sampled value represents that moment that present clock arrives should arrive relative to it mistiming in moment.

7. the system that the raising clock stability according to claim 5 or 6 is analyzed, is characterized in that, the system that described raising clock stability is analyzed is, OTM2800 time tester further.

8. the system of raising clock stability analysis according to claim 7, is characterized in that, establish embedded system in described OTM2800 time tester.