CN104581835A - Device and method for mapping downlink reference signal - Google Patents
Device and method for mapping downlink reference signal Download PDFInfo
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- CN104581835A CN104581835A CN201310522154.2A CN201310522154A CN104581835A CN 104581835 A CN104581835 A CN 104581835A CN 201310522154 A CN201310522154 A CN 201310522154A CN 104581835 A CN104581835 A CN 104581835A
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Abstract
The invention discloses a device and method for mapping a downlink reference signal. The device comprises a memory, a processor and a hardware accelerator, wherein the memory is used for storing a reference signal pattern; the reference signal pattern comprises a bitmap indicating distribution of the reference signal sequence in a unit time-frequency resource; the unit time-frequency resource comprises a plurality of resource particles; the bitmap at least comprises a first mark and a second mark; the first mark represents the resource particles corresponding to the first mark and used for bearing the reference signal sequence; the second mark represents the resource particles corresponding to the second mark and not used for bearing the reference signal sequence; the processor is used for generating the reference signal sequence, reading the reference signal pattern from the memory, and allocating the reference signal pattern and the reference signal sequence to the hardware accelerator; the hardware accelerator is used for mapping the reference signal sequence to the resource particles corresponding to the first mark on the basis of the reference signal pattern, so as to obtain the reference signal.
Description
Technical field
The application relates to the communications field, particularly a kind of device and method mapping downlink reference signal.
Background technology
In order to make can to communicate smoothly between base station and mobile terminal, send in the down link of information in base station to mobile terminal, usually need to map reference signal, such as: cell reference signals (Cell Reference Signal, CRS), location reference signals (Position ReferenceSignal, PRS), channel status reference signal (ChannelState Information ReferenceSignal, CSI-RS) etc.
Reference signal comprises reference signal sequence and reference signal pattern.
Reference signal sequence is a kind of pseudo random sequence of making an appointment between transmitting terminal and receiving terminal, and the situation of the reference signal sequence received by receiving terminal can be estimated the situation of channel.
Reference signal pattern is the situation that reference signal sequence distributes in unit running time-frequency resource.Consult the schematic diagram of reference signal pattern one embodiment when Fig. 1-3, Fig. 1 is prior art 1 antenna port.The schematic diagram of reference signal pattern one embodiment when Fig. 2 is prior art 2 antenna ports.The schematic diagram of reference signal pattern one embodiment when Fig. 3 is prior art 4 antenna ports.
In running time-frequency resource shown in Fig. 1, abscissa is time domain, and time domain is a subframe (Subframe), and length is 1ms, and each subframe comprises 2 time slots (Slot), and namely each slot length is 0.5ms.Adopt general cyclic prefix (CP), each slot comprises 7 symbols.Ordinate is frequency domain, and frequency domain is a Resource Block (Resource Block, RB), and each RB comprises 12 subcarriers.Know again, it is exactly a resource particle (ResourceElement, RE) that a symbol is multiplied by a subcarrier, so in figure, a lattice represents a RE.R is used in figure
0the lattice of mark represents that this RE is for carrying reference signal sequence R
0, and the lattice of figure empty represents that this RE can not be used for carrying reference signal sequence R
0(such as, this RE is for carrying data).
This RE being represented for carrying reference signal sequence in another antenna port with the RE of Shadow marks in Fig. 2, so, can not be used for transmitting any data at this antenna port.Use letter r
0the lattice of mark represents that this RE is in first antenna port, for carrying reference signal sequence R
0.Use letter r
1the lattice of mark represents that this RE is in second antenna port, for carrying reference signal sequence R
1.
This RE being represented for carrying reference signal sequence in other antenna port with the RE of Shadow marks in Fig. 3, so, can not be used for transmitting any data at this antenna port.Use letter r
0the lattice of mark represents that this RE is in first antenna port, for carrying reference signal sequence R
0.Use letter r
1the lattice of mark represents that this RE is in second antenna port, for carrying reference signal sequence R
1.Use letter r
2the lattice of mark represents that this RE is in the 3rd antenna port, for carrying reference signal sequence R
2.Use letter r
3the lattice of mark represents that this RE is in the 4th antenna port, for carrying reference signal sequence R
3.
Prior art provides the structural representation of a kind of base station one execution mode, consults Fig. 4, and Fig. 4 is the structural representation of base station one execution mode in prior art.The base station of present embodiment comprises: the hardware accelerator 410 connected in turn and ofdm signal generator 420.
Hardware accelerator 410, for according to existing protocol, produces reference signal pattern and reference signal sequence by hardware algorithm in inside certainly, and according to reference signal pattern Reference Signal sequence mapping in resource particle.
Ofdm signal generator 420 is for the data genaration time domain OFDM signal by each antenna port, and wherein, the data of described antenna port comprise reference signal and non-reference signal.
But, under this approach, due to hardware accelerator 410 by hardware algorithm at inside solidification existing protocol, generating reference signal sequence and reference signal pattern, once hardware accelerator 410 has designed, reference signal sequence or reference signal pattern have just been fixed up, thus cause adapting to the amendment of reference signal sequence or pattern in the evolution of New Deal, newly-increased reference signal in New Deal evolution can not be adapted to, poor expandability.
Summary of the invention
The technical problem that the application mainly solves is to provide the device and method mapping downlink reference signal, and can revise reference signal pattern or reference signal sequence flexibly, extensibility is strong.
For solving the problems of the technologies described above, the application's first aspect provides a kind of device mapping downlink reference signal, comprising: memory, processor and hardware accelerator; Described memory, for stored reference signal pattern, described reference signal pattern comprises the bitmap being used to indicate the distribution of reference signal sequence in unit running time-frequency resource, described unit running time-frequency resource comprises multiple resource particle, described bitmap at least comprises the first mark and the second mark, resource particle corresponding to described first mark of described first mark expression is for carrying reference signal sequence, and described second mark represents that the resource particle corresponding to described second mark is not used in and carries described reference signal sequence; Described processor, for generating reference signal sequence, and reads described reference signal pattern from described memory, and configures to described hardware accelerator by described reference signal pattern and reference signal sequence; Described hardware accelerator, reference signal is obtained for being mapped to by described reference signal sequence based on described reference signal pattern in the resource particle corresponding to described first mark, wherein, described reference signal is sent to receiving terminal and by described receiving terminal for channel estimating.
In conjunction with first aspect, in the first possible execution mode of the application's first aspect, described unit running time-frequency resource takies at least one OFDM symbol and on frequency domain, takies multiple Resource Block in time domain, wherein, in an OFDM symbol, each Resource Block takies multiple bits of described bitmap, and each bit is for carrying a mark in described bitmap.
In conjunction with the first possible execution mode of first aspect and first aspect, in the execution mode that the second of the application's first aspect is possible, also comprise: interface, be coupling between described processor and described hardware accelerator, for receiving the bitmap in the reference signal pattern of described processor generation, and give described hardware accelerator by this bitmap transmissions; Described interface comprises the multiple port of address continuous print, for transmitting multiple marks that described bitmap comprises successively.
In conjunction with first aspect, in the third possible execution mode of the application's first aspect, this reference signal sequence also for receiving the described reference signal sequence that described processor generates, and is transferred to described hardware accelerator by described interface.
The third possible execution mode of the execution mode possible in conjunction with the second of first aspect and first aspect, in the 4th kind of possible execution mode of the application's first aspect, the quantity of described multiple port is configured to be variable.
For solving the problems of the technologies described above, the application's second aspect provides the method mapping downlink reference signal, comprise: read reference signal pattern from memory, described reference signal pattern comprises the bitmap being used to indicate the distribution of reference signal sequence in unit running time-frequency resource, described unit running time-frequency resource comprises multiple resource particle, described bitmap at least comprises the first mark and the second mark, resource particle corresponding to described first mark of described first mark expression is for carrying reference signal sequence, described second mark represents that the resource particle corresponding to described second mark is not used in the described reference signal sequence of carrying, generating reference signal sequence, described reference signal pattern and reference signal sequence are configured to hardware accelerator, by described hardware accelerator, reference signal is obtained based in the resource particle that described reference signal sequence to be mapped to corresponding to described first mark by described reference signal pattern, wherein, described reference signal is sent to receiving terminal and by described receiving terminal for channel estimating.
In conjunction with second aspect, in the first possible execution mode of the application's second aspect, described unit running time-frequency resource takies at least one OFDM symbol and on frequency domain, takies multiple Resource Block in time domain, wherein, in an OFDM symbol, each Resource Block takies multiple bits of described bitmap, and each bit is for carrying a mark in described bitmap.
In conjunction with the first possible execution mode of second aspect and second aspect, in the execution mode that the second of the application's second aspect is possible, described described reference signal pattern and reference signal sequence configurations comprises to hardware accelerator: by the bitmap in reference signal pattern described in interface, and gives described hardware accelerator by this bitmap transmissions; Described interface comprises the multiple port of address continuous print, for transmitting multiple marks that described bitmap comprises successively.
In conjunction with second aspect, in the third possible execution mode of the application's second aspect, described described reference signal pattern and reference signal sequence configurations also comprises to hardware accelerator: by reference signal sequence described in described interface, and this reference signal sequence is transferred to described hardware accelerator.
The third possible execution mode of the execution mode possible in conjunction with the second of second aspect and second aspect, in the 4th kind of possible execution mode of the application's second aspect, the quantity of described multiple port is configured to be variable.
Such scheme by from memory read be used to indicate the reference signal pattern of the bitmap of the distribution of reference signal sequence unit running time-frequency resource after, generating reference signal sequence, and Reference Signal pattern and reference signal sequence configure to hardware accelerator, then hardware accelerator is passed through, obtain reference signal based in the resource particle corresponding to reference signal pattern Reference Signal sequence mapping to the first mark, realize mapping downlink reference signal.Because reference signal pattern stores in memory in the form of a bitmap, so, when needing the pattern revising reference signal pattern, only need the bitmap in corresponding modify memory, thus realize amendment reference signal pattern and newly-increased reference signal flexibly, there is strong extensibility; Stored in the form of a bitmap in memory by Reference Signal pattern, each resource particle only need carry out marking with a bit, realizes farthest decreasing the mutual flow of software and hardware.And reference signal sequence stores in memory equally, when needs amendment reference signal sequence, only need directly amendment reference signal sequence, thus achieve and revise reference signal sequence flexibly.
When antenna port has multiple, because hardware accelerator only needs the bitmap of the effective antenna port reading reference signal and effective reference signal sequence, thus save the mutual flow of software and hardware.
Accompanying drawing explanation
The schematic diagram of reference signal pattern one embodiment when Fig. 1 is prior art 1 antenna port;
The schematic diagram of reference signal pattern one embodiment when Fig. 2 is prior art 2 antenna ports;
The schematic diagram of reference signal pattern one embodiment when Fig. 3 is prior art 4 antenna ports;
Fig. 4 is the structural representation of base station one execution mode in prior art;
Fig. 5 is the structural representation of the application base station one execution mode;
Fig. 6 is the bitmap corresponding to reference signal pattern of the single port of the application's reference signal and the structural representation of reference signal sequence one execution mode;
Mapping schematic diagram when Fig. 7 is a Resource Block of symbol 4 in the application's mapping graph 1;
Fig. 8 is the bitmap corresponding to reference signal pattern of the multiport of the application's reference signal and the structural representation of reference signal sequence one execution mode;
Fig. 9 is the flow chart that the application maps method one execution mode of downlink reference signal;
Figure 10 is the flow chart that the application maps another execution mode of method of downlink reference signal.
Embodiment
In below describing, in order to illustrate instead of in order to limit, propose the detail of such as particular system structure, interface, technology and so on, thoroughly to understand the application.But, it will be clear to one skilled in the art that and also can realize the application in other execution mode not having these details.In other situation, omit the detailed description to well-known device, circuit and method, in order to avoid unnecessary details hinders the description of the application.
Consult Fig. 5, Fig. 5 is the structural representation of the application base station one execution mode.The base station of present embodiment comprises: memory 510, processor 520 and hardware accelerator 540.Wherein, processor 520 connected storage 510 and hardware accelerator 540 respectively.
Memory 510, for stored reference signal pattern, reference signal pattern comprises the bitmap being used to indicate the distribution of reference signal sequence in unit running time-frequency resource, unit running time-frequency resource comprises multiple resource particle, bitmap at least comprises the first mark and the second mark, first mark expression first marks corresponding resource particle for carrying reference signal sequence, and the second mark expression second marks corresponding resource particle and is not used in the described reference signal sequence of carrying.
Processor 520 for generating reference signal sequence, and reads reference signal pattern from memory 510, and Reference Signal pattern and reference signal sequence configure to hardware accelerator 540.
Hardware accelerator 540, for based on reference signal pattern Reference Signal sequence mapping to first mark corresponding to resource particle on obtain reference signal, wherein, reference signal be sent to receiving terminal and receiving end for channel estimating.
Alternatively, unit running time-frequency resource takies at least one OFDM symbol and on frequency domain, takies multiple Resource Block in time domain, wherein, in an OFDM symbol, each Resource Block takies multiple bits of bitmap, and each bit is for carrying a mark in described bitmap.
Alternatively, base station also comprises interface 530, and interface 530 is coupling between processor 520 and hardware accelerator 540, for the bitmap in the reference signal pattern that receiving processor 520 generates, and by this bitmap transmissions to hardware accelerator 540; Interface 530 comprises the multiple port of address continuous print, for transmitting multiple marks that bitmap comprises successively.
Alternatively, this reference signal sequence also for the reference signal sequence that receiving processor 520 generates, and is transferred to hardware accelerator 540 by interface 530.
Alternatively, the quantity of multiple port is configured to be variable.
Particularly, Fig. 6 and Fig. 7 is seen also.Fig. 6 is the bitmap corresponding to reference signal pattern of the single port of the application's reference signal and the structural representation of reference signal sequence one execution mode.Mapping schematic diagram when Fig. 7 is a Resource Block of symbol 4 in the application's mapping graph 1.
According to existing protocol, the bandwidth corresponding to a symbol is at most 110 Resource Block (Resource Block, RB).As shown in Figure 6, in the present embodiment, unit running time-frequency resource takies at least 1 symbol and on frequency domain, takies 110 Resource Block RB at the most in time domain
0~ RB
m-1, M≤110.Because 1 Resource Block comprises 12 subcarriers, so time domain includes 12 resource particle (Resource Element, RE) for 1 symbol and frequency domain in the running time-frequency resource corresponding to 1 Resource Block.As shown in Figure 7, time domain includes 12 resource particle RE for 1 symbol and frequency domain in the running time-frequency resource 720 corresponding to 1 Resource Block
0~ RE
11.With 1 bit (Bit), each resource particle can represent that whether this resource particle is for carrying reference signal sequence, such as: the first mark 611 is " 1 ", represent that this resource particle is for carrying reference signal sequence, second mark 612 is " 0 ", represents that this resource particle is not used in carrying reference signal sequence.So time domain is 1 symbol, frequency domain is that the running time-frequency resource of 1 Resource Block needs to record with 12 bits.Be appreciated that unit running time-frequency resource is only the resource that a part represents with time domain and frequency domain, its concrete unit value can set flexibly, is not limited to the citing of the present embodiment.
In the present embodiment, RE corresponding to employing first mark " 1 " represents is for carrying reference signal sequence, RE corresponding to second mark " 0 " represents is not used in carrying reference signal sequence, be understandable that, also the RE corresponding to can representing with the first mark " 1 " is in other embodiments not used in carrying reference signal sequence, and the RE corresponding to the second mark " 0 " represents is for carrying reference signal sequence.
But under existing hardware condition, byte is minimum is 16 bits, so, time domain is 1 symbol, and frequency domain is that the running time-frequency resource of 1 Resource Block can only adopt a byte (Byte) to record, wherein, low 12 (position 0-11) is valid data, and high 4 (position 12-15) is invalid data.
So the reference signal pattern in the unit running time-frequency resource will recording corresponding to a symbol and 110 Resource Block in the mode of bitmap 610, needs 16*110=1760 bit.And existing memory 510 can only read 128 at every turn, so bitmap 610 often row stores at most the reference signal carrying situation of a 128 ÷ 16=8 Resource Block, carries out digital independent to facilitate.
Memory 510 stored reference signal pattern, reference signal pattern comprises the bitmap 610 being used to indicate the distribution of reference signal sequence in unit running time-frequency resource.When needs change reference signal pattern, can data bit in corresponding change bitmap 610.Such as, the Partial Bitmap corresponding to part reference signal pattern of the situation of a Resource Block is originally " 00100001000 ", after amendment, records the Partial Bitmap corresponding to part reference signal pattern of the situation of this Resource Block for " 000100000100 ".
Processor 520 generates multiple reference signal sequence X
0~ X
k-1, K≤1320, multiple reference signal sequence is stored in memory 510 in the mode of reference signal sequence 620.In extreme situations, all resource particle in a symbol are all for transmission of reference signals.Now, 12*110=1320 reference signal sequence need be stored at most in reference signal sequence 620.Each reference signal sequence is set here and need uses 32 bits.And, same because existing memory 510 can only read 128 at every turn, so reference signal sequence 620 often row stores a 128 ÷ 32=4 reference signal sequence at most, carries out digital independent to facilitate.Processor 520 reads bitmap 610 and reference signal sequence 620 from memory 510, and bitmap 610 and reference signal sequence 620 is configured successively to hardware accelerator 540 by symbol.Wherein, bitmap 610 and the reference signal sequence 620 of each symbol can be identical, also can be different.
Hardware accelerator 540 reads bitmap 610 and reference signal sequence 620, and contraposition Figure 61 0 scans, and the resource particle corresponding to read bitmap 610 Reference Signal sequence mapping to the first mark obtains reference signal.When reading the first mark 611 in bitmap 610 when first time, first reference signal sequence X in hardware accelerator 540 Reference Signal sequence 620
0be mapped to the resource particle RE of this first mark corresponding to 611
3on, when reading the second mark 611 in bitmap 610 when second time, second reference signal sequence X in hardware accelerator 540 Reference Signal sequence 620
1be mapped to the resource particle RE of this first mark corresponding to 611
9on, the rest may be inferred, until the resource particle of all first marks corresponding to 611 is all mapped complete.
In the present embodiment, a reference signal sequence in one the first corresponding reference signal sequence 620 of mark in bitmap 610, and each reference signal sequence is revisable.In other embodiments, multiple first marks in bitmap 610 also can same reference signal sequence in corresponding reference signal sequence 620.Be specially:
When reading the first mark 611 in bitmap 610 when hardware accelerator 540 first time, first reference signal sequence X in hardware accelerator 540 Reference Signal sequence 620
0be mapped to the resource particle RE of this first mark corresponding to 611
3on, X
0for " 00000010000000000000000000000001 ".When reading the first mark 611 in bitmap 610 when hardware accelerator 540 second time, first reference signal sequence X in hardware accelerator 540 Reference Signal sequence 620
0be mapped to the resource particle RE of this first mark corresponding to 611
9on, X
0for " 00000010000000000000000000000010.The rest may be inferred, until the resource particle of all first marks corresponding to 611 is all mapped complete.
When adopting the mode of MIMO, base station is communicated with mobile terminal by multiple antenna port.Because the reference signal pattern of each port of a symbol can be identical, also can be different, so, the memory space shared by bitmap corresponding to reference signal pattern of each port can be identical, also can be different, and the value forming the element of each bitmap can be identical, also can be different.The reference signal pattern of multiple port to connect successively with the form of bitmap 610 by port number and is stored in memory 510, such as, and then store the bitmap of second port after the bitmap storage of first port, the rest may be inferred, until the bitmap of all of the port all stores complete.
Because the number of the reference signal sequence of each port of a symbol of processor 520 generation can be identical, also can be different, so the memory space shared by reference signal sequence of each port of a symbol can be identical, also can be different.Further, the value forming the element of each reference signal sequence can be identical, also can be different.The reference signal sequence of multiple port to connect successively with the form of reference signal sequence 620 by port number and is stored in memory 510, such as, and then the reference signal sequence of second port is stored after the reference signal sequence storage of first port, the rest may be inferred, until the reference signal sequence of all of the port all stores complete.And the bitmap of all of the port connects after storing again and stores the reference signal sequence of all of the port.
Particularly, see also Fig. 8, Fig. 8 is the bitmap corresponding to reference signal pattern of the multiport of the application's reference signal and the structural representation of reference signal sequence one execution mode.
Be different from above-mentioned execution mode, in present embodiment, reference signal has 8 port Port at the most
0~ Port
n-1, N≤8.
Record the reference signal pattern of multiple port in a symbol in the mode of bitmap 610, and be stored in memory 510 with the form of bitmap 610.The size of the bitmap of the reference signal pattern in each port of a symbol and the unit running time-frequency resource corresponding to 110 Resource Block is identical, takies 16*110=1760 bit.Wherein, often row stores at most the reference signal carrying situation of a 128 ÷ 16=8 Resource Block.Because the reference signal pattern of each port of a symbol can be identical, also can be different, so the memory space shared by bitmap 610 corresponding to reference signal pattern of each port can be identical, also can be different, and form the element (RB of each bitmap 610
0~ RB
m-1, M≤110) value can be identical, also can be different.Port number pressed by the reference signal pattern of multiple port, and from low address to high address, (position 0 ~ 127) connects successively with the form of bitmap 610 and be stored in memory 510, such as, and first port Port
0bitmap store after and then store second port Port
1bitmap, the rest may be inferred, until the bitmap of all of the port all stores complete.
Processor 520 generates multiple reference signal sequence X
0~ X
k-1, K≤1320, record the reference signal sequence of multiple ports of a symbol in the mode of reference signal sequence 620, multiple reference signal sequence is stored in memory 510 in the mode of reference signal sequence 620.Each port of a symbol stores at most 12*110=1320 reference signal sequence, and each reference signal sequence takies 32 bits.Wherein, often row stores a 128 ÷ 32=4 reference signal sequence at most.Because the number of the reference signal sequence of each port of a symbol can be identical, also can be different, so the memory space shared by reference signal sequence of each port of a symbol can be identical, also can be different.Further, the value forming the element of each reference signal sequence can be identical, also can be different.The reference signal sequence of multiple port to connect successively in the mode of reference signal sequence 620 by port number and is stored in memory 510, such as, and first port Port
0reference signal sequence store after and then store second port Port
1reference signal sequence, the rest may be inferred, until the reference signal sequence of all of the port all stores complete.And the bitmap of all of the port connects after storing again and stores the reference signal sequence of all of the port.
Be appreciated that the reference signal sequence that processor 520 generates can be kept in memory 510, also can directly send to hardware accelerator 540, specific implementation can set flexibly, is not limited to the citing of the present embodiment.
In present embodiment, be stored in the bitmap only describing effective port in the bitmap 610 in memory 510, the reference signal sequence 620 that processor 520 generates only describes the reference signal sequence of effective port, and effective port number is at most 8.In other embodiments, bitmap 610 also can record the bitmap of all of the port, and reference signal sequence 620 also can record the reference signal sequence of all of the port, and effective port number can be more.
Such scheme, processor 520 is by being stored in memory 510 in the form of a bitmap by the reference signal pattern of each symbol, and be unit running time-frequency resource dynamic assignment reference signal pattern and reference signal sequence by symbol, make the resource particle of hardware accelerator 540 corresponding to reference signal pattern Reference Signal sequence mapping to the first mark obtains reference signal.Because reference signal pattern is stored in memory 510 in the form of a bitmap, so, when needing the pattern revising reference signal pattern, only need the bitmap in corresponding modify memory 510, thus realize amendment reference signal pattern flexibly, achieve amendment reference signal pattern and newly-increased reference signal flexibly, there is strong extensibility.Be stored in memory 510 in the form of a bitmap by Reference Signal pattern, each resource particle only need carry out marking with a mark, realizes farthest decreasing the mutual flow of software and hardware.
And reference signal sequence is stored in memory 510 equally, when needs amendment reference signal sequence, only need directly amendment reference signal sequence, thus achieve and revise reference signal sequence flexibly.
When antenna port has multiple, because hardware accelerator 540 only needs the bitmap of the effective antenna port reading reference signal and effective reference signal sequence, thus save the mutual flow of software and hardware.
Be appreciated that, such scheme can also be used for mapping non-reference signal, such as, master sync signal (Primary Synchronization Signal, PSS), auxiliary synchronous signals (SecondarySynchronization Signal, SSS), Physical Downlink Control Channel (Enhanced PhysicalDownlink Control Channel, EPDCCH) etc. is strengthened.
Consult Fig. 9, Fig. 9 is the flow chart that the application maps method one execution mode of downlink reference signal.The method of the mapping downlink reference signal of present embodiment comprises the steps:
S901: reference signal pattern is read from memory in base station, described reference signal pattern comprises the bitmap being used to indicate the distribution of reference signal sequence in unit running time-frequency resource, described unit running time-frequency resource comprises multiple resource particle, described bitmap at least comprises the first mark and the second mark, resource particle corresponding to described first mark of described first mark expression is for carrying reference signal sequence, and described second mark represents that the resource particle corresponding to described second mark is not used in and carries described reference signal sequence.
Before needs map reference signal, the reference signal pattern of each symbol is read from memory in base station, and reference signal pattern comprises the bitmap being used to indicate the distribution of reference signal sequence in unit running time-frequency resource, and unit running time-frequency resource comprises multiple resource particle.Bitmap at least comprises the first mark and the second mark, and the first mark expression first marks corresponding resource particle for carrying reference signal sequence, and the second mark expression second marks corresponding resource particle and is not used in carrying reference signal sequence.
In the present embodiment, the reference signal pattern of each symbol can be identical, also can be different.When needs change reference signal pattern, correspondingly can change and store the mark corresponding to resource particle in bitmap in memory for carrying reference signal sequence.Be appreciated that unit running time-frequency resource is only the resource that a part represents with time domain and frequency domain, its concrete unit value can set flexibly, is not limited to the citing of the present embodiment.
S902: generating reference signal sequence.
Base station generates the reference signal sequence of each symbol, and the reference signal sequence generated stores in memory, and each reference signal sequence is revisable.When needs change reference signal sequence, correspondingly the reference signal sequence stored in memory can be changed.
S903: described reference signal pattern and reference signal sequence are configured to hardware accelerator.
Base station is from the bitmap corresponding to memory reading reference signal pattern and reference signal sequence, and the bitmap corresponding to Reference Signal pattern and reference signal sequence configure to hardware accelerator successively by symbol.Wherein, the reference signal pattern of each symbol and reference signal sequence can be identical, also can be different.
S904: by described hardware accelerator, reference signal is obtained based in the resource particle that described reference signal sequence to be mapped to corresponding to described first mark by described reference signal pattern, wherein, described reference signal is sent to receiving terminal and by described receiving terminal for channel estimating.
Base station by the bitmap corresponding to hardware accelerator reading reference signal pattern and reference signal sequence, and is scanned bitmap, and the resource particle corresponding to read bitmap Reference Signal sequence mapping to the first mark obtains reference signal.Wherein, reference signal be sent to receiving terminal and receiving end for channel estimating.
When hardware accelerator first time read in bitmap first mark time, hardware accelerator first reference signal sequence is mapped to this first mark corresponding to resource particle on.When second time read in bitmap first mark time, hardware accelerator second reference signal sequence is mapped to this first mark corresponding to resource particle on.The rest may be inferred, until the resource particle corresponding to all first marks is all mapped complete.
In the present embodiment, the quantity of reference signal sequence is multiple, the corresponding reference signal sequence of one first mark in bitmap, and each reference signal sequence is revisable.Multiple reference signal sequence is mapped in the resource particle corresponding to the first mark according to read bitmap by hardware accelerator by base station successively.In other embodiments, the quantity of reference signal sequence can be multiple, also can be single, and multiple first marks in bitmap also can corresponding same reference signal sequence, and reference signal sequence is revisable.Specifically refer to Fig. 7 and associated description, do not repeat herein.
Preferably, the effective bitmap be stored in memory is only read in base station by configure hardware accelerator, and effective reference signal sequence, to save the mutual flow of software and hardware.
Be appreciated that the reference signal sequence that base station generates can be preserved in memory, also directly can send to hardware accelerator, specific implementation can set flexibly, is not limited to the citing of the present embodiment.
Such scheme, base station is by storing the reference signal pattern of each symbol in the form of a bitmap in memory, and be unit running time-frequency resource dynamic assignment reference signal pattern and reference signal sequence by symbol, make the resource particle of hardware accelerator corresponding to reference signal pattern Reference Signal sequence mapping to the first mark obtains reference signal.Because reference signal pattern stores in memory in the form of a bitmap, so, when needing the pattern revising reference signal pattern, only need the bitmap in corresponding modify memory, thus realize amendment reference signal pattern flexibly, achieve amendment reference signal pattern and newly-increased reference signal flexibly, there is strong extensibility.Stored in the form of a bitmap in memory by Reference Signal pattern, each resource particle only need carry out marking with a mark, realizes farthest decreasing the mutual flow of software and hardware.
And reference signal sequence stores in memory equally, when needs amendment reference signal sequence, only need directly amendment reference signal sequence, thus achieve and revise reference signal sequence flexibly.
Be appreciated that, such scheme can also be used for mapping non-reference signal, such as, master sync signal (Primary Synchronization Signal, PSS), auxiliary synchronous signals (SecondarySynchronization Signal, SSS), Physical Downlink Control Channel (Enhanced PhysicalDownlink Control Channel, EPDCCH) etc. is strengthened.
Consult Figure 10, Figure 10 is the flow chart that the application maps another execution mode of method of downlink reference signal.The method of the mapping downlink reference signal of present embodiment comprises the steps:
S1001: the reference signal pattern of multiple port is read from memory in base station, described reference signal pattern comprises the bitmap being used to indicate the distribution of reference signal sequence in unit running time-frequency resource, described unit running time-frequency resource comprises multiple resource particle, described bitmap at least comprises the first mark and the second mark, resource particle corresponding to described first mark of described first mark expression is for carrying reference signal sequence, and described second mark represents that the resource particle corresponding to described second mark is not used in and carries described reference signal sequence.
Before needs map reference signal, the reference signal pattern of each symbol is read from memory in base station, and reference signal pattern comprises the bitmap being used to indicate the distribution of reference signal sequence in unit running time-frequency resource, and unit running time-frequency resource comprises multiple resource particle.Bitmap at least comprises the first mark and the second mark, and the first mark expression first marks corresponding resource particle for carrying reference signal sequence, and the second mark expression second marks corresponding resource particle and is not used in carrying reference signal sequence.
Unit running time-frequency resource takies at least one OFDM symbol and on frequency domain, takies multiple Resource Block in time domain, wherein, in an OFDM symbol, each Resource Block takies multiple bits of bitmap, and each bit is for carrying a mark in bitmap.
The bitmap corresponding to reference signal pattern storing each symbol in memory to connect arrangement successively by the order preset, and is undertaken arranging to facilitate base station to carry out digital independent by preset rules.Wherein, the quantity of multiple port is configured to be variable, and the reference signal pattern of multiple port is different.
Such as, according to existing protocol, the bandwidth corresponding to a symbol is at most 110 Resource Block.In the present embodiment, unit running time-frequency resource takies at least 1 symbol and on frequency domain, takies 110 Resource Block at the most in time domain.Because 1 Resource Block comprises 12 subcarriers, so time domain includes 12 resource particle for 1 symbol and frequency domain in the running time-frequency resource corresponding to 1 Resource Block.With 1 bit, each resource particle can represent that whether this resource particle is for carrying reference signal sequence, such as: first is labeled as " 1 ", represent that this resource particle is for carrying reference signal sequence, second is labeled as " 0 ", represents that this resource particle is not used in carrying reference signal sequence.So time domain is 1 symbol, frequency domain is that the running time-frequency resource of 1 Resource Block needs to record with 12 bits.Be appreciated that unit running time-frequency resource is only the resource that a part represents with time domain and frequency domain, its concrete unit value can set flexibly, is not limited to the citing of the present embodiment.
In the present embodiment, RE corresponding to employing first mark " 1 " represents is for carrying reference signal sequence, RE corresponding to second mark " 0 " represents is not used in carrying reference signal sequence, be understandable that, also the RE corresponding to can representing with the first mark " 1 " is in other embodiments not used in carrying reference signal sequence, and the RE corresponding to the second mark " 0 " represents is for carrying reference signal sequence.
But in view of existing hardware condition, byte is minimum is 16 bits, so, the corresponding running time-frequency resource of time domain to be 1 symbol and frequency domain be 1 Resource Block can only adopt a byte to store, wherein, low 12 (position 0-11) is valid data, and high 4 (position 12-15) is invalid data.Therefore, store the bitmap corresponding to reference signal pattern in a symbol in memory and the unit running time-frequency resource corresponding to 110 Resource Block, need to take 16*110=1760 bit.
In addition, because existing memory can only read 128 at every turn, so, conveniently carry out digital independent, store the bitmap often maximum carrying situation storing the reference signal sequence of a 128 ÷ 16=8 Resource Block of row in memory.According to such rule, in bitmap corresponding to reference signal pattern in the unit running time-frequency resource corresponding to a symbol and 110 Resource Block, the bitmap of the Resource Block included by unit running time-frequency resource is connected to arranging by the order from low address to high address successively and stores, and often capable connecting successively arranges the bitmap of storage 8 Resource Block.
In the present embodiment, base station is communicated with mobile communication by an antenna port, in other modes, multiple port also can be adopted to communicate with mobile terminal, such as, adopt the mode of MIMO.Because the reference signal pattern of each port of reference signal can be identical, also can be different, so, the memory space shared by bitmap corresponding to reference signal pattern of each port can be identical, also can be different, and the value forming the element of each bitmap can be identical, also different.The reference signal pattern of multiple port connects successively in the form of a bitmap by port number and stores in memory, such as, and then store the bitmap of second port after the bitmap storage of first port, the rest may be inferred, until the bitmap of all of the port all stores complete.
Preferably, the bitmap corresponding to reference signal pattern stored in memory only includes effective bitmap of effective port, and the bitmap corresponding to each reference signal pattern can be revised.When needs change reference signal pattern, correspondingly can change and store the mark corresponding to resource particle in bitmap in memory for carrying reference signal sequence.
In the present embodiment, the port number of reference signal is at most 8, and the number of the reference signal supported is at most 6.In other embodiments, the port number of reference signal and the number of reference signal supported can be more.
S1002: the reference signal sequence generating multiple port.
Base station generates the reference signal sequence of multiple ports of each symbol, and the reference signal sequence generated stores in memory, and each reference signal sequence is revisable.When needs change reference signal sequence, correspondingly the reference signal sequence stored in memory can be changed.
The reference signal sequence storing each symbol in memory connects successively to arranging by the order preset and stores, and is undertaken arranging to facilitate carrying out digital independent by preset rules.The stored reference burst and all bitmaps connect after storing again.
Such as, in extreme situations, all resource particle in a symbol are all for transmission of reference signals.Now, store in reference signal sequence in memory and need store at most 12*110=1320 reference signal sequence, and each reference signal sequence is set need uses 32 bits.And, same because existing memory can only read 128 at every turn, so reference signal sequence often row stores a 128 ÷ 32=4 reference signal sequence at most, carries out digital independent to facilitate base station.
When base station is communicated with mobile terminal by multiple port, such as, adopt the mode of MIMO.Because the number of the reference signal sequence of each port of a symbol can be identical, also can be different, so, the memory space shared by reference signal sequence of each port of a symbol can be identical, also can be different, further, the value forming the element of each reference signal sequence can be identical, also can be different.The reference signal sequence of multiple port connects storage in memory by port number successively with the form of reference signal sequence, such as, and then the reference signal sequence of second port is stored after the reference signal sequence storage of first port, the rest may be inferred, until the reference signal sequence of all of the port all stores complete.And the bitmap of all of the port connects after storing again and stores the reference signal sequence of all of the port.
Preferably, the reference signal sequence stored in memory only includes effective reference signal sequence of effective port, and each reference signal sequence is revisable.When needs change reference signal sequence, correspondingly the reference signal sequence stored in memory can be changed.
Be appreciated that the reference signal sequence that base station generates can be preserved in memory, also directly can send to hardware accelerator, specific implementation can set flexibly, is not limited to the citing of the present embodiment.
In the present embodiment, the reference signal pattern of each symbol can be identical, also can be different.The port number of reference signal is at most 8, and the number of the reference signal supported is at most 6.In other embodiments, the port number of reference signal and the number of reference signal supported can be more.
S1003: by the bitmap in reference signal pattern described in interface, and give described hardware accelerator by this bitmap transmissions; Described interface comprises the multiple port of address continuous print, for transmitting multiple marks that described bitmap comprises successively; By reference signal sequence described in described interface, and this reference signal sequence is transferred to described hardware accelerator.
This bitmap from the bitmap in the reference signal pattern of memory, and is transferred to hardware accelerator by symbol by interface by base station successively; Interface comprises the multiple port of address continuous print, for transmitting multiple marks that bitmap comprises successively.By the reference signal sequence of interface from memory, and this reference signal sequence is transferred to hardware accelerator successively by symbol.
S1004: by described hardware accelerator, reference signal is obtained based in the resource particle that described reference signal sequence to be mapped to corresponding to described first mark by described reference signal pattern, wherein, described reference signal is sent to receiving terminal and by described receiving terminal for channel estimating.
The bitmap that hardware accelerator receiving interface transmits successively by symbol and reference signal sequence, base station is scanned to read bitmap to bitmap by hardware accelerator, and according to read bitmap Reference Signal sequence mapping to first mark corresponding to resource particle on obtain reference signal.Wherein, reference signal be sent to receiving terminal and receiving end for channel estimating.
Alternatively, the quantity of reference signal sequence is multiple, and base station is undertaken scanning to read bitmap by configure hardware accelerator bitmap, is mapped to successively in the resource particle corresponding to the first mark according to read bitmap Reference Signal sequence.
When first time read in bitmap first mark time, hardware accelerator first reference signal sequence is mapped to this first mark corresponding to resource particle on.When second time read in bitmap first mark time, hardware accelerator second reference signal sequence is mapped to this first mark corresponding to resource particle on.The rest may be inferred, until the resource particle corresponding to all first marks is all mapped complete.
In the present embodiment, reference signal pattern and the reference signal sequence of each port of each symbol can be identical, also can be different.The corresponding reference signal sequence of one first mark in bitmap, and each reference signal sequence is revisable.In other embodiments, multiple first marks in bitmap also can corresponding same reference signal sequence, and each reference signal sequence is revisable.
Preferably, effective bitmap of effective antenna port is only read by configure hardware accelerator in base station, and effective reference signal sequence of effective antenna port, to save the mutual flow of software and hardware.
Such scheme, base station is by storing the reference signal pattern of each symbol in the form of a bitmap in memory, and be unit running time-frequency resource dynamic assignment reference signal pattern and reference signal sequence by symbol, make the resource particle of hardware accelerator corresponding to reference signal pattern Reference Signal sequence mapping to the first mark obtains reference signal.Because reference signal pattern stores in memory in the form of a bitmap, so, when needing the pattern revising reference signal pattern, only need the bitmap in corresponding modify memory, thus realize amendment reference signal pattern flexibly, achieve amendment reference signal pattern and newly-increased reference signal flexibly, there is strong extensibility.Stored in the form of a bitmap in memory by Reference Signal pattern, each resource particle only need carry out marking with a mark, realizes farthest decreasing the mutual flow of software and hardware.
And reference signal sequence stores in memory equally, when needs amendment reference signal sequence, only need directly amendment reference signal sequence, thus achieve and revise reference signal sequence flexibly.
When antenna port has multiple, because hardware accelerator only needs effective bitmap of the effective antenna port reading reference signal and effective reference signal sequence, thus save the mutual flow of software and hardware.
Be appreciated that, such scheme can also be used for mapping non-reference signal, such as, master sync signal (Primary Synchronization Signal, PSS), auxiliary synchronous signals (SecondarySynchronization Signal, SSS), Physical Downlink Control Channel (Enhanced PhysicalDownlink Control Channel, EPDCCH) etc. is strengthened.
In several execution modes that the application provides, should be understood that, disclosed system, apparatus and method, can realize by another way.Such as, device embodiments described above is only schematic, such as, the division of described module or unit, be only a kind of logic function to divide, actual can have other dividing mode when realizing, such as multiple unit or assembly can in conjunction with or another system can be integrated into, or some features can be ignored, or do not perform.Another point, shown or discussed coupling each other or direct-coupling or communication connection can be by some interfaces, and the indirect coupling of device or unit or communication connection can be electrical, machinery or other form.
The described unit illustrated as separating component or can may not be and physically separates, and the parts as unit display can be or may not be physical location, namely can be positioned at a place, or also can be distributed in multiple network element.Some or all of unit wherein can be selected according to the actual needs to realize the object of present embodiment scheme.
In addition, each functional unit in each execution mode of the application can be integrated in a processing unit, also can be that the independent physics of unit exists, also can two or more unit in a unit integrated.Above-mentioned integrated unit both can adopt the form of hardware to realize, and the form of SFU software functional unit also can be adopted to realize.
If described integrated unit using the form of SFU software functional unit realize and as independently production marketing or use time, can be stored in a computer read/write memory medium.Based on such understanding, the part that the technical scheme of the application contributes to prior art in essence in other words or all or part of of this technical scheme can embody with the form of software product, this computer software product is stored in a storage medium, comprising some instructions in order to make a computer equipment (can be personal computer, server, or the network equipment etc.) or processor (processor) perform all or part of step of method described in each execution mode of the application.And aforesaid storage medium comprises: USB flash disk, portable hard drive, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disc or CD etc. various can be program code stored medium.
Claims (10)
1. map a device for downlink reference signal, it is characterized in that, comprising: memory, processor and hardware accelerator;
Described memory, for stored reference signal pattern, described reference signal pattern comprises the bitmap being used to indicate the distribution of reference signal sequence in unit running time-frequency resource, described unit running time-frequency resource comprises multiple resource particle, described bitmap at least comprises the first mark and the second mark, resource particle corresponding to described first mark of described first mark expression is for carrying reference signal sequence, and described second mark represents that the resource particle corresponding to described second mark is not used in and carries described reference signal sequence;
Described processor, for generating reference signal sequence, and reads described reference signal pattern from described memory, and configures to described hardware accelerator by described reference signal pattern and reference signal sequence;
Described hardware accelerator, reference signal is obtained for being mapped to by described reference signal sequence based on described reference signal pattern in the resource particle corresponding to described first mark, wherein, described reference signal is sent to receiving terminal and by described receiving terminal for channel estimating.
2. device according to claim 1, it is characterized in that, described unit running time-frequency resource takies at least one OFDM symbol and on frequency domain, takies multiple Resource Block in time domain, wherein, in an OFDM symbol, each Resource Block takies multiple bits of described bitmap, and each bit is for carrying a mark in described bitmap.
3. device according to claim 1 and 2, it is characterized in that, also comprise: interface, be coupling between described processor and described hardware accelerator, for receiving the bitmap in the reference signal pattern of described processor generation, and give described hardware accelerator by this bitmap transmissions; Described interface comprises the multiple port of address continuous print, for transmitting multiple marks that described bitmap comprises successively.
4. device according to claim 3, is characterized in that, this reference signal sequence also for receiving the described reference signal sequence that described processor generates, and is transferred to described hardware accelerator by described interface.
5. the device according to claim 3 or 4, is characterized in that, the quantity of described multiple port is configured to be variable.
6. map a method for downlink reference signal, it is characterized in that, comprising:
Reference signal pattern is read from memory, described reference signal pattern comprises the bitmap being used to indicate the distribution of reference signal sequence in unit running time-frequency resource, described unit running time-frequency resource comprises multiple resource particle, described bitmap at least comprises the first mark and the second mark, resource particle corresponding to described first mark of described first mark expression is for carrying reference signal sequence, and described second mark represents that the resource particle corresponding to described second mark is not used in and carries described reference signal sequence;
Generating reference signal sequence;
Described reference signal pattern and reference signal sequence are configured to hardware accelerator;
By described hardware accelerator, reference signal is obtained based in the resource particle that described reference signal sequence to be mapped to corresponding to described first mark by described reference signal pattern, wherein, described reference signal is sent to receiving terminal and by described receiving terminal for channel estimating.
7. method according to claim 6, it is characterized in that, described unit running time-frequency resource takies at least one OFDM symbol and on frequency domain, takies multiple Resource Block in time domain, wherein, in an OFDM symbol, each Resource Block takies multiple bits of described bitmap, and each bit is for carrying a mark in described bitmap.
8. the method according to claim 6 or 7, is characterized in that, described described reference signal pattern and reference signal sequence configurations comprises to hardware accelerator:
By the bitmap in reference signal pattern described in interface, and give described hardware accelerator by this bitmap transmissions; Described interface comprises the multiple port of address continuous print, for transmitting multiple marks that described bitmap comprises successively.
9. method according to claim 8, is characterized in that, described described reference signal pattern and reference signal sequence configurations also comprises to hardware accelerator:
By reference signal sequence described in described interface, and this reference signal sequence is transferred to described hardware accelerator.
10. method according to claim 8 or claim 9, it is characterized in that, the quantity of described multiple port is configured to be variable.
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